1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019~2020, 2022 NXP 3 * Copyright 2019~2020, 2022 NXP
4 */ 4 */
5 5
6 /delete-node/ &enet1_lpcg; 6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2; 7 /delete-node/ &fec2;
8 8
9 / { !! 9 &conn_subsys {
10 conn_enet0_root_clk: clock-conn-enet0- 10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock"; 11 compatible = "fixed-clock";
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 clock-frequency = <250000000>; 13 clock-frequency = <250000000>;
14 clock-output-names = "conn_ene 14 clock-output-names = "conn_enet0_root_clk";
15 }; 15 };
16 16
17 clk_dummy: clock-dummy { <<
18 compatible = "fixed-clock"; <<
19 #clock-cells = <0>; <<
20 clock-frequency = <0>; <<
21 clock-output-names = "clk_dumm <<
22 }; <<
23 }; <<
24 <<
25 &conn_subsys { <<
26 eqos: ethernet@5b050000 { 17 eqos: ethernet@5b050000 {
27 compatible = "nxp,imx8dxl-dwma 18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
28 reg = <0x5b050000 0x10000>; 19 reg = <0x5b050000 0x10000>;
29 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
30 interrupts = <GIC_SPI 163 IRQ_ 21 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 162 IRQ_ 22 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-names = "macirq", "e !! 23 interrupt-names = "eth_wake_irq", "macirq";
33 clocks = <&eqos_lpcg IMX_LPCG_ 24 clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
34 <&eqos_lpcg IMX_LPCG_ 25 <&eqos_lpcg IMX_LPCG_CLK_6>,
35 <&eqos_lpcg IMX_LPCG_ 26 <&eqos_lpcg IMX_LPCG_CLK_0>,
36 <&eqos_lpcg IMX_LPCG_ 27 <&eqos_lpcg IMX_LPCG_CLK_5>,
37 <&eqos_lpcg IMX_LPCG_ 28 <&eqos_lpcg IMX_LPCG_CLK_2>;
38 clock-names = "stmmaceth", "pc 29 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
39 assigned-clocks = <&clk IMX_SC 30 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
40 assigned-clock-rates = <125000 31 assigned-clock-rates = <125000000>;
41 power-domains = <&pd IMX_SC_R_ 32 power-domains = <&pd IMX_SC_R_ENET_1>;
42 status = "disabled"; 33 status = "disabled";
43 }; 34 };
44 35
45 usbotg2: usb@5b0e0000 { 36 usbotg2: usb@5b0e0000 {
46 compatible = "fsl,imx8dxl-usb" !! 37 compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
47 reg = <0x5b0e0000 0x200>; 38 reg = <0x5b0e0000 0x200>;
48 interrupt-parent = <&gic>; 39 interrupt-parent = <&gic>;
49 interrupts = <GIC_SPI 166 IRQ_ 40 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
50 fsl,usbphy = <&usbphy2>; 41 fsl,usbphy = <&usbphy2>;
51 fsl,usbmisc = <&usbmisc2 0>; 42 fsl,usbmisc = <&usbmisc2 0>;
52 /* 43 /*
53 * usbotg1 and usbotg2 share o 44 * usbotg1 and usbotg2 share one clcok.
54 * scu firmware disables the a 45 * scu firmware disables the access to the clock and keeps
55 * it always on in case other 46 * it always on in case other core (M4) uses one of these.
56 */ 47 */
57 clocks = <&clk_dummy>; 48 clocks = <&clk_dummy>;
58 ahb-burst-config = <0x0>; 49 ahb-burst-config = <0x0>;
59 tx-burst-size-dword = <0x10>; 50 tx-burst-size-dword = <0x10>;
60 rx-burst-size-dword = <0x10>; 51 rx-burst-size-dword = <0x10>;
>> 52 #stream-id-cells = <1>;
61 power-domains = <&pd IMX_SC_R_ 53 power-domains = <&pd IMX_SC_R_USB_1>;
62 status = "disabled"; 54 status = "disabled";
>> 55
>> 56 clk_dummy: clock-dummy {
>> 57 compatible = "fixed-clock";
>> 58 #clock-cells = <0>;
>> 59 clock-frequency = <0>;
>> 60 clock-output-names = "clk_dummy";
>> 61 };
63 }; 62 };
64 63
65 usbmisc2: usbmisc@5b0e0200 { 64 usbmisc2: usbmisc@5b0e0200 {
66 #index-cells = <1>; 65 #index-cells = <1>;
67 compatible = "fsl,imx7ulp-usbm !! 66 compatible = "fsl,imx7ulp-usbmisc";
68 reg = <0x5b0e0200 0x200>; 67 reg = <0x5b0e0200 0x200>;
69 }; 68 };
70 69
71 usbphy2: usbphy@5b110000 { 70 usbphy2: usbphy@5b110000 {
72 compatible = "fsl,imx8dxl-usbp 71 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
73 reg = <0x5b110000 0x1000>; 72 reg = <0x5b110000 0x1000>;
74 clocks = <&usb2_2_lpcg IMX_LPC 73 clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
75 power-domains = <&pd IMX_SC_R_ 74 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
76 status = "disabled"; 75 status = "disabled";
77 }; 76 };
78 77
79 eqos_lpcg: clock-controller@5b240000 { 78 eqos_lpcg: clock-controller@5b240000 {
80 compatible = "fsl,imx8qxp-lpcg 79 compatible = "fsl,imx8qxp-lpcg";
81 reg = <0x5b240000 0x10000>; 80 reg = <0x5b240000 0x10000>;
82 #clock-cells = <1>; 81 #clock-cells = <1>;
83 clocks = <&conn_enet0_root_clk 82 clocks = <&conn_enet0_root_clk>,
84 <&conn_axi_clk>, 83 <&conn_axi_clk>,
85 <&conn_axi_clk>, 84 <&conn_axi_clk>,
86 <&clk IMX_SC_R_ENET_1 85 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
87 <&conn_ipg_clk>; 86 <&conn_ipg_clk>;
88 clock-indices = <IMX_LPCG_CLK_ 87 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
89 <IMX_LPCG_CLK_ 88 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
90 <IMX_LPCG_CLK_ 89 <IMX_LPCG_CLK_6>;
91 clock-output-names = "eqos_ptp 90 clock-output-names = "eqos_ptp",
92 "eqos_mem 91 "eqos_mem_clk",
93 "eqos_acl 92 "eqos_aclk",
94 "eqos_clk 93 "eqos_clk",
95 "eqos_csr 94 "eqos_csr_clk";
96 power-domains = <&pd IMX_SC_R_ 95 power-domains = <&pd IMX_SC_R_ENET_1>;
97 }; 96 };
98 97
99 usb2_2_lpcg: clock-controller@5b280000 98 usb2_2_lpcg: clock-controller@5b280000 {
100 compatible = "fsl,imx8qxp-lpcg 99 compatible = "fsl,imx8qxp-lpcg";
101 reg = <0x5b280000 0x10000>; 100 reg = <0x5b280000 0x10000>;
102 #clock-cells = <1>; 101 #clock-cells = <1>;
103 clock-indices = <IMX_LPCG_CLK_ 102 clock-indices = <IMX_LPCG_CLK_7>;
104 clocks = <&conn_ipg_clk>; 103 clocks = <&conn_ipg_clk>;
105 clock-output-names = "usboh3_2 104 clock-output-names = "usboh3_2_phy_ipg_clk";
106 power-domains = <&pd IMX_SC_R_ 105 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
107 }; 106 };
108 107
109 }; 108 };
110 109
111 &dma_apbh { <<
112 interrupts = <GIC_SPI 176 IRQ_TYPE_LEV <<
113 <GIC_SPI 176 IRQ_TYPE_LEV <<
114 <GIC_SPI 176 IRQ_TYPE_LEV <<
115 <GIC_SPI 176 IRQ_TYPE_LEV <<
116 }; <<
117 <<
118 &enet0_lpcg { 110 &enet0_lpcg {
119 clocks = <&conn_enet0_root_clk>, 111 clocks = <&conn_enet0_root_clk>,
120 <&conn_enet0_root_clk>, 112 <&conn_enet0_root_clk>,
121 <&conn_axi_clk>, 113 <&conn_axi_clk>,
122 <&clk IMX_SC_R_ENET_0 IMX_SC_ 114 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
123 <&conn_ipg_clk>, 115 <&conn_ipg_clk>,
124 <&conn_ipg_clk>; 116 <&conn_ipg_clk>;
125 }; 117 };
126 118
127 &fec1 { 119 &fec1 {
128 compatible = "fsl,imx8dxl-fec", "fsl,i !! 120 compatible = "fsl,imx8qm-fec";
129 interrupts = <GIC_SPI 160 IRQ_TYPE_LEV 121 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 158 IRQ_TYPE_LEV 122 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 159 IRQ_TYPE_LEV 123 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 161 IRQ_TYPE_LEV 124 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
133 assigned-clocks = <&clk IMX_SC_R_ENET_ 125 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
134 assigned-clock-rates = <125000000>; 126 assigned-clock-rates = <125000000>;
135 }; <<
136 <<
137 &gpmi { <<
138 interrupts = <GIC_SPI 174 IRQ_TYPE_LEV <<
139 }; 127 };
140 128
141 &usdhc1 { 129 &usdhc1 {
142 compatible = "fsl,imx8dxl-usdhc", "fsl 130 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
143 interrupts = <GIC_SPI 138 IRQ_TYPE_LEV 131 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
144 }; 132 };
145 133
146 &usdhc2 { 134 &usdhc2 {
147 compatible = "fsl,imx8dxl-usdhc", "fsl 135 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
148 interrupts = <GIC_SPI 139 IRQ_TYPE_LEV 136 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
149 }; 137 };
150 138
151 &usdhc3 { 139 &usdhc3 {
152 compatible = "fsl,imx8dxl-usdhc", "fsl 140 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
153 interrupts = <GIC_SPI 140 IRQ_TYPE_LEV 141 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
154 }; 142 };
155 143
156 &usbotg1 { 144 &usbotg1 {
157 interrupts = <GIC_SPI 169 IRQ_TYPE_LEV 145 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
158 /* 146 /*
159 * usbotg1 and usbotg2 share one clock 147 * usbotg1 and usbotg2 share one clock
160 * scfw disable clock access and keep 148 * scfw disable clock access and keep it always on
161 * in case other core (M4) use one of 149 * in case other core (M4) use one of these.
162 */ 150 */
163 clocks = <&clk_dummy>; 151 clocks = <&clk_dummy>;
164 }; 152 };
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