1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019~2020, 2022 NXP 3 * Copyright 2019~2020, 2022 NXP
4 */ 4 */
5 5
6 /delete-node/ &enet1_lpcg; 6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2; 7 /delete-node/ &fec2;
8 8
9 / { 9 / {
10 conn_enet0_root_clk: clock-conn-enet0- 10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock"; 11 compatible = "fixed-clock";
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 clock-frequency = <250000000>; 13 clock-frequency = <250000000>;
14 clock-output-names = "conn_ene 14 clock-output-names = "conn_enet0_root_clk";
15 }; 15 };
16 <<
17 clk_dummy: clock-dummy { <<
18 compatible = "fixed-clock"; <<
19 #clock-cells = <0>; <<
20 clock-frequency = <0>; <<
21 clock-output-names = "clk_dumm <<
22 }; <<
23 }; 16 };
24 17
25 &conn_subsys { 18 &conn_subsys {
26 eqos: ethernet@5b050000 { 19 eqos: ethernet@5b050000 {
27 compatible = "nxp,imx8dxl-dwma 20 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
28 reg = <0x5b050000 0x10000>; 21 reg = <0x5b050000 0x10000>;
29 interrupt-parent = <&gic>; 22 interrupt-parent = <&gic>;
30 interrupts = <GIC_SPI 163 IRQ_ 23 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 162 IRQ_ 24 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-names = "macirq", "e !! 25 interrupt-names = "eth_wake_irq", "macirq";
33 clocks = <&eqos_lpcg IMX_LPCG_ 26 clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
34 <&eqos_lpcg IMX_LPCG_ 27 <&eqos_lpcg IMX_LPCG_CLK_6>,
35 <&eqos_lpcg IMX_LPCG_ 28 <&eqos_lpcg IMX_LPCG_CLK_0>,
36 <&eqos_lpcg IMX_LPCG_ 29 <&eqos_lpcg IMX_LPCG_CLK_5>,
37 <&eqos_lpcg IMX_LPCG_ 30 <&eqos_lpcg IMX_LPCG_CLK_2>;
38 clock-names = "stmmaceth", "pc 31 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
39 assigned-clocks = <&clk IMX_SC 32 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
40 assigned-clock-rates = <125000 33 assigned-clock-rates = <125000000>;
41 power-domains = <&pd IMX_SC_R_ 34 power-domains = <&pd IMX_SC_R_ENET_1>;
42 status = "disabled"; 35 status = "disabled";
43 }; 36 };
44 37
45 usbotg2: usb@5b0e0000 { 38 usbotg2: usb@5b0e0000 {
46 compatible = "fsl,imx8dxl-usb" 39 compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
47 reg = <0x5b0e0000 0x200>; 40 reg = <0x5b0e0000 0x200>;
48 interrupt-parent = <&gic>; 41 interrupt-parent = <&gic>;
49 interrupts = <GIC_SPI 166 IRQ_ 42 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
50 fsl,usbphy = <&usbphy2>; 43 fsl,usbphy = <&usbphy2>;
51 fsl,usbmisc = <&usbmisc2 0>; 44 fsl,usbmisc = <&usbmisc2 0>;
52 /* 45 /*
53 * usbotg1 and usbotg2 share o 46 * usbotg1 and usbotg2 share one clcok.
54 * scu firmware disables the a 47 * scu firmware disables the access to the clock and keeps
55 * it always on in case other 48 * it always on in case other core (M4) uses one of these.
56 */ 49 */
57 clocks = <&clk_dummy>; 50 clocks = <&clk_dummy>;
58 ahb-burst-config = <0x0>; 51 ahb-burst-config = <0x0>;
59 tx-burst-size-dword = <0x10>; 52 tx-burst-size-dword = <0x10>;
60 rx-burst-size-dword = <0x10>; 53 rx-burst-size-dword = <0x10>;
61 power-domains = <&pd IMX_SC_R_ 54 power-domains = <&pd IMX_SC_R_USB_1>;
62 status = "disabled"; 55 status = "disabled";
>> 56
>> 57 clk_dummy: clock-dummy {
>> 58 compatible = "fixed-clock";
>> 59 #clock-cells = <0>;
>> 60 clock-frequency = <0>;
>> 61 clock-output-names = "clk_dummy";
>> 62 };
63 }; 63 };
64 64
65 usbmisc2: usbmisc@5b0e0200 { 65 usbmisc2: usbmisc@5b0e0200 {
66 #index-cells = <1>; 66 #index-cells = <1>;
67 compatible = "fsl,imx7ulp-usbm 67 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
68 reg = <0x5b0e0200 0x200>; 68 reg = <0x5b0e0200 0x200>;
69 }; 69 };
70 70
71 usbphy2: usbphy@5b110000 { 71 usbphy2: usbphy@5b110000 {
72 compatible = "fsl,imx8dxl-usbp 72 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
73 reg = <0x5b110000 0x1000>; 73 reg = <0x5b110000 0x1000>;
74 clocks = <&usb2_2_lpcg IMX_LPC 74 clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
75 power-domains = <&pd IMX_SC_R_ 75 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
76 status = "disabled"; 76 status = "disabled";
77 }; 77 };
78 78
79 eqos_lpcg: clock-controller@5b240000 { 79 eqos_lpcg: clock-controller@5b240000 {
80 compatible = "fsl,imx8qxp-lpcg 80 compatible = "fsl,imx8qxp-lpcg";
81 reg = <0x5b240000 0x10000>; 81 reg = <0x5b240000 0x10000>;
82 #clock-cells = <1>; 82 #clock-cells = <1>;
83 clocks = <&conn_enet0_root_clk 83 clocks = <&conn_enet0_root_clk>,
84 <&conn_axi_clk>, 84 <&conn_axi_clk>,
85 <&conn_axi_clk>, 85 <&conn_axi_clk>,
86 <&clk IMX_SC_R_ENET_1 86 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
87 <&conn_ipg_clk>; 87 <&conn_ipg_clk>;
88 clock-indices = <IMX_LPCG_CLK_ 88 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
89 <IMX_LPCG_CLK_ 89 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
90 <IMX_LPCG_CLK_ 90 <IMX_LPCG_CLK_6>;
91 clock-output-names = "eqos_ptp 91 clock-output-names = "eqos_ptp",
92 "eqos_mem 92 "eqos_mem_clk",
93 "eqos_acl 93 "eqos_aclk",
94 "eqos_clk 94 "eqos_clk",
95 "eqos_csr 95 "eqos_csr_clk";
96 power-domains = <&pd IMX_SC_R_ 96 power-domains = <&pd IMX_SC_R_ENET_1>;
97 }; 97 };
98 98
99 usb2_2_lpcg: clock-controller@5b280000 99 usb2_2_lpcg: clock-controller@5b280000 {
100 compatible = "fsl,imx8qxp-lpcg 100 compatible = "fsl,imx8qxp-lpcg";
101 reg = <0x5b280000 0x10000>; 101 reg = <0x5b280000 0x10000>;
102 #clock-cells = <1>; 102 #clock-cells = <1>;
103 clock-indices = <IMX_LPCG_CLK_ 103 clock-indices = <IMX_LPCG_CLK_7>;
104 clocks = <&conn_ipg_clk>; 104 clocks = <&conn_ipg_clk>;
105 clock-output-names = "usboh3_2 105 clock-output-names = "usboh3_2_phy_ipg_clk";
106 power-domains = <&pd IMX_SC_R_ 106 power-domains = <&pd IMX_SC_R_USB_1_PHY>;
107 }; 107 };
108 108
109 }; 109 };
110 110
111 &dma_apbh { <<
112 interrupts = <GIC_SPI 176 IRQ_TYPE_LEV <<
113 <GIC_SPI 176 IRQ_TYPE_LEV <<
114 <GIC_SPI 176 IRQ_TYPE_LEV <<
115 <GIC_SPI 176 IRQ_TYPE_LEV <<
116 }; <<
117 <<
118 &enet0_lpcg { 111 &enet0_lpcg {
119 clocks = <&conn_enet0_root_clk>, 112 clocks = <&conn_enet0_root_clk>,
120 <&conn_enet0_root_clk>, 113 <&conn_enet0_root_clk>,
121 <&conn_axi_clk>, 114 <&conn_axi_clk>,
122 <&clk IMX_SC_R_ENET_0 IMX_SC_ 115 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
123 <&conn_ipg_clk>, 116 <&conn_ipg_clk>,
124 <&conn_ipg_clk>; 117 <&conn_ipg_clk>;
125 }; 118 };
126 119
127 &fec1 { 120 &fec1 {
128 compatible = "fsl,imx8dxl-fec", "fsl,i 121 compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
129 interrupts = <GIC_SPI 160 IRQ_TYPE_LEV 122 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 158 IRQ_TYPE_LEV 123 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 159 IRQ_TYPE_LEV 124 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 161 IRQ_TYPE_LEV 125 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
133 assigned-clocks = <&clk IMX_SC_R_ENET_ 126 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
134 assigned-clock-rates = <125000000>; 127 assigned-clock-rates = <125000000>;
135 }; <<
136 <<
137 &gpmi { <<
138 interrupts = <GIC_SPI 174 IRQ_TYPE_LEV <<
139 }; 128 };
140 129
141 &usdhc1 { 130 &usdhc1 {
142 compatible = "fsl,imx8dxl-usdhc", "fsl 131 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
143 interrupts = <GIC_SPI 138 IRQ_TYPE_LEV 132 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
144 }; 133 };
145 134
146 &usdhc2 { 135 &usdhc2 {
147 compatible = "fsl,imx8dxl-usdhc", "fsl 136 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
148 interrupts = <GIC_SPI 139 IRQ_TYPE_LEV 137 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
149 }; 138 };
150 139
151 &usdhc3 { 140 &usdhc3 {
152 compatible = "fsl,imx8dxl-usdhc", "fsl 141 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
153 interrupts = <GIC_SPI 140 IRQ_TYPE_LEV 142 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
154 }; 143 };
155 144
156 &usbotg1 { 145 &usbotg1 {
157 interrupts = <GIC_SPI 169 IRQ_TYPE_LEV 146 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
158 /* 147 /*
159 * usbotg1 and usbotg2 share one clock 148 * usbotg1 and usbotg2 share one clock
160 * scfw disable clock access and keep 149 * scfw disable clock access and keep it always on
161 * in case other core (M4) use one of 150 * in case other core (M4) use one of these.
162 */ 151 */
163 clocks = <&clk_dummy>; 152 clocks = <&clk_dummy>;
164 }; 153 };
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