1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019~2020, 2022 NXP 3 * Copyright 2019~2020, 2022 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8-clock.h> 6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h> 7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h> <<
9 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h> 12 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { 20 aliases {
22 ethernet0 = &fec1; 21 ethernet0 = &fec1;
23 ethernet1 = &eqos; 22 ethernet1 = &eqos;
24 gpio0 = &lsio_gpio0; 23 gpio0 = &lsio_gpio0;
25 gpio1 = &lsio_gpio1; 24 gpio1 = &lsio_gpio1;
26 gpio2 = &lsio_gpio2; 25 gpio2 = &lsio_gpio2;
27 gpio3 = &lsio_gpio3; 26 gpio3 = &lsio_gpio3;
28 gpio4 = &lsio_gpio4; 27 gpio4 = &lsio_gpio4;
29 gpio5 = &lsio_gpio5; 28 gpio5 = &lsio_gpio5;
30 gpio6 = &lsio_gpio6; 29 gpio6 = &lsio_gpio6;
31 gpio7 = &lsio_gpio7; 30 gpio7 = &lsio_gpio7;
32 mu1 = &lsio_mu1; 31 mu1 = &lsio_mu1;
33 }; 32 };
34 33
35 cpus: cpus { 34 cpus: cpus {
36 #address-cells = <2>; 35 #address-cells = <2>;
37 #size-cells = <0>; 36 #size-cells = <0>;
38 37
39 /* We have 1 clusters with 2 C 38 /* We have 1 clusters with 2 Cortex-A35 cores */
40 A35_0: cpu@0 { 39 A35_0: cpu@0 {
41 device_type = "cpu"; 40 device_type = "cpu";
42 compatible = "arm,cort 41 compatible = "arm,cortex-a35";
43 reg = <0x0 0x0>; 42 reg = <0x0 0x0>;
44 enable-method = "psci" 43 enable-method = "psci";
45 next-level-cache = <&A 44 next-level-cache = <&A35_L2>;
46 clocks = <&clk IMX_SC_ 45 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
47 #cooling-cells = <2>; 46 #cooling-cells = <2>;
48 operating-points-v2 = 47 operating-points-v2 = <&a35_opp_table>;
49 }; 48 };
50 49
51 A35_1: cpu@1 { 50 A35_1: cpu@1 {
52 device_type = "cpu"; 51 device_type = "cpu";
53 compatible = "arm,cort 52 compatible = "arm,cortex-a35";
54 reg = <0x0 0x1>; 53 reg = <0x0 0x1>;
55 enable-method = "psci" 54 enable-method = "psci";
56 next-level-cache = <&A 55 next-level-cache = <&A35_L2>;
57 clocks = <&clk IMX_SC_ 56 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
58 #cooling-cells = <2>; 57 #cooling-cells = <2>;
59 operating-points-v2 = 58 operating-points-v2 = <&a35_opp_table>;
60 }; 59 };
61 60
62 A35_L2: l2-cache0 { 61 A35_L2: l2-cache0 {
63 compatible = "cache"; 62 compatible = "cache";
64 cache-level = <2>; 63 cache-level = <2>;
65 cache-unified; 64 cache-unified;
66 }; 65 };
67 }; 66 };
68 67
69 a35_opp_table: opp-table { 68 a35_opp_table: opp-table {
70 compatible = "operating-points 69 compatible = "operating-points-v2";
71 opp-shared; 70 opp-shared;
72 71
73 opp-900000000 { 72 opp-900000000 {
74 opp-hz = /bits/ 64 <90 73 opp-hz = /bits/ 64 <900000000>;
75 opp-microvolt = <10000 74 opp-microvolt = <1000000>;
76 clock-latency-ns = <15 75 clock-latency-ns = <150000>;
77 }; 76 };
78 77
79 opp-1200000000 { 78 opp-1200000000 {
80 opp-hz = /bits/ 64 <12 79 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <11000 80 opp-microvolt = <1100000>;
82 clock-latency-ns = <15 81 clock-latency-ns = <150000>;
83 opp-suspend; 82 opp-suspend;
84 }; 83 };
85 }; 84 };
86 85
87 gic: interrupt-controller@51a00000 { 86 gic: interrupt-controller@51a00000 {
88 compatible = "arm,gic-v3"; 87 compatible = "arm,gic-v3";
89 reg = <0x0 0x51a00000 0 0x1000 88 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
90 <0x0 0x51b00000 0 0xc000 89 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
91 #interrupt-cells = <3>; 90 #interrupt-cells = <3>;
92 interrupt-controller; 91 interrupt-controller;
93 interrupts = <GIC_PPI 9 IRQ_TY 92 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
94 }; 93 };
95 94
96 reserved-memory { 95 reserved-memory {
97 #address-cells = <2>; 96 #address-cells = <2>;
98 #size-cells = <2>; 97 #size-cells = <2>;
99 ranges; 98 ranges;
100 99
101 dsp_reserved: dsp@92400000 { 100 dsp_reserved: dsp@92400000 {
102 reg = <0 0x92400000 0 101 reg = <0 0x92400000 0 0x2000000>;
103 no-map; 102 no-map;
104 }; 103 };
105 }; 104 };
106 105
107 pmu { 106 pmu {
108 compatible = "arm,cortex-a35-p !! 107 compatible = "arm,armv8-pmuv3";
109 interrupts = <GIC_PPI 7 IRQ_TY 108 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
110 }; 109 };
111 110
112 psci { 111 psci {
113 compatible = "arm,psci-1.0"; 112 compatible = "arm,psci-1.0";
114 method = "smc"; 113 method = "smc";
115 }; 114 };
116 115
117 system-controller { 116 system-controller {
118 compatible = "fsl,imx-scu"; 117 compatible = "fsl,imx-scu";
119 mbox-names = "tx0", 118 mbox-names = "tx0",
120 "rx0", 119 "rx0",
121 "gip3"; 120 "gip3";
122 mboxes = <&lsio_mu1 0 0 121 mboxes = <&lsio_mu1 0 0
123 &lsio_mu1 1 0 122 &lsio_mu1 1 0
124 &lsio_mu1 3 3>; 123 &lsio_mu1 3 3>;
125 124
126 pd: power-controller { 125 pd: power-controller {
127 compatible = "fsl,imx8 126 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";
128 #power-domain-cells = 127 #power-domain-cells = <1>;
129 }; 128 };
130 129
131 clk: clock-controller { 130 clk: clock-controller {
132 compatible = "fsl,imx8 131 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
133 #clock-cells = <2>; 132 #clock-cells = <2>;
134 }; 133 };
135 134
136 scu_gpio: gpio { 135 scu_gpio: gpio {
137 compatible = "fsl,imx8 136 compatible = "fsl,imx8qxp-sc-gpio";
138 gpio-controller; 137 gpio-controller;
139 #gpio-cells = <2>; 138 #gpio-cells = <2>;
140 }; 139 };
141 140
142 iomuxc: pinctrl { 141 iomuxc: pinctrl {
143 compatible = "fsl,imx8 142 compatible = "fsl,imx8dxl-iomuxc";
144 }; 143 };
145 144
146 ocotp: ocotp { 145 ocotp: ocotp {
147 compatible = "fsl,imx8 146 compatible = "fsl,imx8qxp-scu-ocotp";
148 #address-cells = <1>; 147 #address-cells = <1>;
149 #size-cells = <1>; 148 #size-cells = <1>;
150 149
151 fec_mac0: mac@2c4 { 150 fec_mac0: mac@2c4 {
152 reg = <0x2c4 6 151 reg = <0x2c4 6>;
153 }; 152 };
154 153
155 fec_mac1: mac@2c6 { 154 fec_mac1: mac@2c6 {
156 reg = <0x2c6 6 155 reg = <0x2c6 6>;
157 }; 156 };
158 }; 157 };
159 158
160 rtc: rtc { 159 rtc: rtc {
161 compatible = "fsl,imx8 160 compatible = "fsl,imx8qxp-sc-rtc";
162 }; 161 };
163 162
164 sc_pwrkey: keys { 163 sc_pwrkey: keys {
165 compatible = "fsl,imx8 164 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
166 linux,keycodes = <KEY_ 165 linux,keycodes = <KEY_POWER>;
167 wakeup-source; 166 wakeup-source;
168 }; 167 };
169 168
170 watchdog { 169 watchdog {
171 compatible = "fsl,imx8 170 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";
172 timeout-sec = <60>; 171 timeout-sec = <60>;
173 }; 172 };
174 173
175 tsens: thermal-sensor { 174 tsens: thermal-sensor {
176 compatible = "fsl,imx8 175 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";
177 #thermal-sensor-cells 176 #thermal-sensor-cells = <1>;
178 }; 177 };
179 }; 178 };
180 179
181 timer { 180 timer {
182 compatible = "arm,armv8-timer" 181 compatible = "arm,armv8-timer";
183 interrupts = <GIC_PPI 13 IRQ_T 182 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
184 <GIC_PPI 14 IRQ_T 183 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
185 <GIC_PPI 11 IRQ_T 184 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
186 <GIC_PPI 10 IRQ_T 185 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
187 }; 186 };
188 187
189 thermal_zones: thermal-zones { 188 thermal_zones: thermal-zones {
190 cpu-thermal { 189 cpu-thermal {
191 polling-delay-passive 190 polling-delay-passive = <250>;
192 polling-delay = <2000> 191 polling-delay = <2000>;
193 thermal-sensors = <&ts 192 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
194 193
195 trips { 194 trips {
196 cpu_alert0: tr 195 cpu_alert0: trip0 {
197 temper 196 temperature = <107000>;
198 hyster 197 hysteresis = <2000>;
199 type = 198 type = "passive";
200 }; 199 };
201 cpu_crit0: tri 200 cpu_crit0: trip1 {
202 temper 201 temperature = <127000>;
203 hyster 202 hysteresis = <2000>;
204 type = 203 type = "critical";
205 }; 204 };
206 }; 205 };
207 206
208 cooling-maps { 207 cooling-maps {
209 map0 { 208 map0 {
210 trip = 209 trip = <&cpu_alert0>;
211 coolin 210 cooling-device =
212 <&A35_ 211 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
213 <&A35_ 212 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 }; 213 };
215 }; 214 };
216 }; 215 };
217 }; 216 };
218 217
219 /* The two values below cannot be chan 218 /* The two values below cannot be changed by the board */
220 xtal32k: clock-xtal32k { 219 xtal32k: clock-xtal32k {
221 compatible = "fixed-clock"; 220 compatible = "fixed-clock";
222 #clock-cells = <0>; 221 #clock-cells = <0>;
223 clock-frequency = <32768>; 222 clock-frequency = <32768>;
224 clock-output-names = "xtal_32K 223 clock-output-names = "xtal_32KHz";
225 }; 224 };
226 225
227 xtal24m: clock-xtal24m { 226 xtal24m: clock-xtal24m {
228 compatible = "fixed-clock"; 227 compatible = "fixed-clock";
229 #clock-cells = <0>; 228 #clock-cells = <0>;
230 clock-frequency = <24000000>; 229 clock-frequency = <24000000>;
231 clock-output-names = "xtal_24M 230 clock-output-names = "xtal_24MHz";
232 }; 231 };
233 232
234 /* sorted in register address */ 233 /* sorted in register address */
235 #include "imx8-ss-cm40.dtsi" <<
236 #include "imx8-ss-adma.dtsi" 234 #include "imx8-ss-adma.dtsi"
237 #include "imx8-ss-conn.dtsi" 235 #include "imx8-ss-conn.dtsi"
238 #include "imx8-ss-ddr.dtsi" 236 #include "imx8-ss-ddr.dtsi"
239 #include "imx8-ss-lsio.dtsi" 237 #include "imx8-ss-lsio.dtsi"
240 }; 238 };
241 239
242 #include "imx8dxl-ss-adma.dtsi" 240 #include "imx8dxl-ss-adma.dtsi"
243 #include "imx8dxl-ss-conn.dtsi" 241 #include "imx8dxl-ss-conn.dtsi"
244 #include "imx8dxl-ss-lsio.dtsi" 242 #include "imx8dxl-ss-lsio.dtsi"
245 #include "imx8dxl-ss-ddr.dtsi" 243 #include "imx8dxl-ss-ddr.dtsi"
246 <<
247 &cm40_intmux { <<
248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL <<
249 <GIC_SPI 9 IRQ_TYPE_LEVEL <<
250 <GIC_SPI 10 IRQ_TYPE_LEVE <<
251 <GIC_SPI 11 IRQ_TYPE_LEVE <<
252 <GIC_SPI 12 IRQ_TYPE_LEVE <<
253 <GIC_SPI 13 IRQ_TYPE_LEVE <<
254 <GIC_SPI 14 IRQ_TYPE_LEVE <<
255 <GIC_SPI 15 IRQ_TYPE_LEVE <<
256 }; <<
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