1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm.dtsi"
11
12 / {
13 model = "Data Modul i.MX8M Mini eDM SB
14 compatible = "dmo,imx8mm-data-modul-ed
15
16 aliases {
17 rtc0 = &rtc;
18 rtc1 = &snvs_rtc;
19 };
20
21 chosen {
22 stdout-path = &uart3;
23 };
24
25 memory@40000000 {
26 device_type = "memory";
27 /* There are 1/2/4 GiB options
28 reg = <0x0 0x40000000 0 0x4000
29 };
30
31 backlight: backlight {
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_ba
35 brightness-levels = <0 1 10 20
36 default-brightness-level = <7>
37 enable-gpios = <&gpio3 0 GPIO_
38 pwms = <&pwm1 0 5000000 0>;
39 /* Disabled by default, unless
40 status = "disabled";
41 };
42
43 clk_xtal25: clk-xtal25 {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
47 };
48
49 clk_xtal32k: clk-xtal32k {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <32768>;
53 };
54
55 panel: panel {
56 backlight = <&backlight>;
57 power-supply = <®_panel_vcc
58 /* Disabled by default, unless
59 status = "disabled";
60 };
61
62 reg_panel_vcc: regulator-panel-vcc {
63 compatible = "regulator-fixed"
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_panel_vc
66 regulator-name = "PANEL_VCC";
67 regulator-min-microvolt = <500
68 regulator-max-microvolt = <500
69 gpio = <&gpio3 6 0>;
70 enable-active-high;
71 /* Disabled by default, unless
72 status = "disabled";
73 };
74
75 reg_usdhc2_vcc: regulator-usdhc2-vcc {
76 compatible = "regulator-fixed"
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usdhc2_v
79 regulator-name = "V_3V3_SD";
80 regulator-min-microvolt = <330
81 regulator-max-microvolt = <330
82 gpio = <&gpio2 19 0>;
83 enable-active-high;
84 };
85
86 watchdog {
87 /* TPS3813 */
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_watchdog
90 compatible = "linux,wdt-gpio";
91 always-running;
92 gpios = <&gpio1 8 GPIO_ACTIVE_
93 hw_algo = "level";
94 /* Reset triggers in 2..3 seco
95 hw_margin_ms = <1500>;
96 /* Disabled by default */
97 status = "disabled";
98 };
99 };
100
101 &A53_0 {
102 cpu-supply = <&buck2_reg>;
103 };
104
105 &A53_1 {
106 cpu-supply = <&buck2_reg>;
107 };
108
109 &A53_2 {
110 cpu-supply = <&buck2_reg>;
111 };
112
113 &A53_3 {
114 cpu-supply = <&buck2_reg>;
115 };
116
117 &ddrc {
118 operating-points-v2 = <&ddrc_opp_table
119
120 ddrc_opp_table: opp-table {
121 compatible = "operating-points
122
123 opp-25000000 {
124 opp-hz = /bits/ 64 <25
125 };
126
127 opp-100000000 {
128 opp-hz = /bits/ 64 <10
129 };
130
131 opp-750000000 {
132 opp-hz = /bits/ 64 <75
133 };
134 };
135 };
136
137 &ecspi1 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ecspi1>;
140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
141 status = "okay";
142
143 flash@0 { /* W25Q128FVSI */
144 compatible = "jedec,spi-nor";
145 m25p,fast-read;
146 spi-max-frequency = <50000000>
147 reg = <0>;
148 };
149 };
150
151 &ecspi2 { /* Feature connector SPI */
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_ecspi2>;
154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
155 /* Disabled by default, unless feature
156 status = "disabled";
157 };
158
159 &ecspi3 { /* Display connector SPI */
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_ecspi3>;
162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>
163 /* Disabled by default, unless display
164 status = "disabled";
165 };
166
167 &fec1 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_fec1>;
170 phy-mode = "rgmii-id";
171 phy-handle = <&fec1_phy_bcm>;
172 phy-supply = <&buck4_reg>;
173 fsl,magic-packet;
174 status = "okay";
175
176 mdio {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 /* Atheros AR8031 PHY */
181 fec1_phy_ath: ethernet-phy@0 {
182 compatible = "ethernet
183 reg = <0>;
184 /*
185 * Dedicated ENET_WOL#
186 * can wake the SoC up
187 */
188 interrupts-extended =
189 reset-gpios = <&gpio1
190 reset-assert-us = <100
191 reset-deassert-us = <1
192 qca,keep-pll-enabled;
193 vddio-supply = <&vddio
194 status = "disabled";
195
196 vddio: vddio-regulator
197 regulator-name
198 regulator-min-
199 regulator-max-
200 };
201
202 vddh: vddh-regulator {
203 regulator-name
204 };
205 };
206
207 /* Broadcom BCM54213PE PHY */
208 fec1_phy_bcm: ethernet-phy@1 {
209 compatible = "ethernet
210 reg = <1>;
211 /*
212 * Dedicated ENET_INT#
213 * unused, the PHY doe
214 * interrupt.
215 */
216 reset-gpios = <&gpio1
217 reset-assert-us = <100
218 reset-deassert-us = <1
219 };
220 };
221 };
222
223 &gpio1 {
224 gpio-line-names =
225 "", "ENET_RST#", "WDOG_B#", "P
226 "", "M2-B_PCIE_RST#", "M2-B_PC
227 "WDOG_KICK#", "M2-B_PCIE_CLKRE
228 "USB1_OTG_ID_3V3", "ENET_WOL#"
229 "", "", "", "ENET_INT#",
230 "", "", "", "", "", "", "", ""
231 "", "", "", "", "", "", "", ""
232 };
233
234 &gpio2 {
235 gpio-line-names =
236 "MEMCFG2", "MEMCFG1", "DSI_RES
237 "M2-B_FULL_CARD_PWROFF_1V8#",
238 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#
239 "MEMCFG0", "WDOG_EN",
240 "M2-B_W_DISABLE1_WWAN_1V8#", "
241 "", "", "", "",
242 "", "", "", "SD2_RESET#", "",
243 "", "", "", "", "", "", "", ""
244 };
245
246 &gpio3 {
247 gpio-line-names =
248 "BL_ENABLE_1V8", "PG_V_IN_VAR#
249 "", "", "TFT_ENABLE_1V8", "GRA
250 "CSI_PD_1V8", "CSI_RESET_1V8#"
251 "", "", "", "",
252 "", "", "", "M2-B_WAKE_WWAN_1V
253 "M2-B_RESET_1V8#", "", "", "",
254 "", "", "", "", "", "", "", ""
255 };
256
257 &gpio4 {
258 gpio-line-names =
259 "NC0", "NC1", "BOOTCFG0", "BOO
260 "BOOTCFG2", "BOOTCFG3", "BOOTC
261 "BOOTCFG6", "BOOTCFG7", "NC10"
262 "BOOTCFG8", "BOOTCFG9", "BOOTC
263 "BOOTCFG12", "BOOTCFG13", "BOO
264 "NC20", "", "", "",
265 "", "CAN_INT#", "CAN_RST#", "G
266 "DIS_USB_DN2", "", "", "";
267 };
268
269 &gpio5 {
270 gpio-line-names =
271 "", "DIS_USB_DN1", "USBHUB_RES
272 "GPIO5_IO04", "", "", "",
273 "", "SPI1_CS#", "", "",
274 "", "SPI2_CS#", "I2C1_SCL_3V3"
275 "I2C2_SCL_3V3", "I2C2_SDA_3V3"
276 "I2C4_SCL_3V3", "I2C4_SDA_3V3"
277 "", "SPI3_CS#", "", "", "", ""
278 };
279
280 &i2c1 {
281 /* IMX8MM ERRATA e7805 -- I2C is limit
282 clock-frequency = <100000>;
283 pinctrl-names = "default", "gpio";
284 pinctrl-0 = <&pinctrl_i2c1>;
285 pinctrl-1 = <&pinctrl_i2c1_gpio>;
286 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI
287 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI
288 status = "okay";
289
290 pmic: pmic@4b {
291 compatible = "rohm,bd71847";
292 reg = <0x4b>;
293 #clock-cells = <0>;
294 clocks = <&clk_xtal32k>;
295 clock-output-names = "clk-32k-
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_pmic>;
298 interrupt-parent = <&gpio1>;
299 interrupts = <3 IRQ_TYPE_EDGE_
300 rohm,reset-snvs-powered;
301
302 /*
303 * i.MX 8M Mini Data Sheet for
304 * 3.1.3 Operating ranges
305 * MIMX8MM4DVTLZAA
306 */
307 regulators {
308 /* VDD_SOC */
309 buck1_reg: BUCK1 {
310 regulator-name
311 regulator-min-
312 regulator-max-
313 regulator-boot
314 regulator-alwa
315 regulator-ramp
316 };
317
318 /* VDD_ARM */
319 buck2_reg: BUCK2 {
320 regulator-name
321 regulator-min-
322 regulator-max-
323 regulator-boot
324 regulator-alwa
325 regulator-ramp
326 rohm,dvs-run-v
327 rohm,dvs-idle-
328 };
329
330 /* VDD_DRAM, BUCK5 */
331 buck3_reg: BUCK3 {
332 regulator-name
333 /* 1.5 GHz DDR
334 regulator-min-
335 regulator-max-
336 regulator-boot
337 regulator-alwa
338 };
339
340 /* 3V3_VDD, BUCK6 */
341 buck4_reg: BUCK4 {
342 regulator-name
343 regulator-min-
344 regulator-max-
345 regulator-boot
346 regulator-alwa
347 };
348
349 /* 1V8_VDD, BUCK7 */
350 buck5_reg: BUCK5 {
351 regulator-name
352 regulator-min-
353 regulator-max-
354 regulator-boot
355 regulator-alwa
356 };
357
358 /* 1V1_NVCC_DRAM, BUCK
359 buck6_reg: BUCK6 {
360 regulator-name
361 regulator-min-
362 regulator-max-
363 regulator-boot
364 regulator-alwa
365 };
366
367 /* 1V8_NVCC_SNVS */
368 ldo1_reg: LDO1 {
369 regulator-name
370 regulator-min-
371 regulator-max-
372 regulator-boot
373 regulator-alwa
374 };
375
376 /* 0V8_VDD_SNVS */
377 ldo2_reg: LDO2 {
378 regulator-name
379 regulator-min-
380 regulator-max-
381 regulator-boot
382 regulator-alwa
383 };
384
385 /* 1V8_VDDA */
386 ldo3_reg: LDO3 {
387 regulator-name
388 regulator-min-
389 regulator-max-
390 regulator-boot
391 regulator-alwa
392 };
393
394 /* 0V9_VDD_PHY */
395 ldo4_reg: LDO4 {
396 regulator-name
397 regulator-min-
398 regulator-max-
399 regulator-boot
400 regulator-alwa
401 };
402
403 /* 1V2_VDD_PHY */
404 ldo6_reg: LDO6 {
405 regulator-name
406 regulator-min-
407 regulator-max-
408 regulator-boot
409 regulator-alwa
410 };
411 };
412 };
413 };
414
415 &i2c2 {
416 /* IMX8MM ERRATA e7805 -- I2C is limit
417 clock-frequency = <100000>;
418 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c2>;
420 pinctrl-1 = <&pinctrl_i2c2_gpio>;
421 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI
422 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI
423 status = "okay";
424
425 usb-hub@2c {
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_usb_hub>
428 compatible = "microchip,usb251
429 reg = <0x2c>;
430 individual-port-switching;
431 reset-gpios = <&gpio5 2 GPIO_A
432 self-powered;
433 };
434
435 eeprom: eeprom@50 {
436 compatible = "atmel,24c32";
437 reg = <0x50>;
438 pagesize = <32>;
439 };
440
441 rtc: rtc@68 {
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_rtc>;
444 compatible = "st,m41t62";
445 reg = <0x68>;
446 interrupts-extended = <&gpio1
447 };
448
449 pcieclk: clk@6a {
450 compatible = "renesas,9fgv0241
451 reg = <0x6a>;
452 clocks = <&clk_xtal25>;
453 #clock-cells = <1>;
454 };
455 };
456
457 &i2c3 { /* Display connector I2C */
458 /* IMX8MM ERRATA e7805 -- I2C is limit
459 clock-frequency = <320000>;
460 pinctrl-names = "default", "gpio";
461 pinctrl-0 = <&pinctrl_i2c3>;
462 pinctrl-1 = <&pinctrl_i2c3_gpio>;
463 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI
464 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI
465 status = "okay";
466 };
467
468 &i2c4 { /* Feature connector I2C */
469 /* IMX8MM ERRATA e7805 -- I2C is limit
470 clock-frequency = <320000>;
471 pinctrl-names = "default", "gpio";
472 pinctrl-0 = <&pinctrl_i2c4>;
473 pinctrl-1 = <&pinctrl_i2c4_gpio>;
474 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI
475 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI
476 status = "okay";
477 };
478
479 &iomuxc {
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_hog_feature>, <&
482 <&pinctrl_hog_panel>, <&pi
483 <&pinctrl_panel_expansion>
484
485 pinctrl_ecspi1: ecspi1-grp {
486 fsl,pins = <
487 MX8MM_IOMUXC_ECSPI1_SC
488 MX8MM_IOMUXC_ECSPI1_MO
489 MX8MM_IOMUXC_ECSPI1_MI
490 MX8MM_IOMUXC_ECSPI1_SS
491 >;
492 };
493
494 pinctrl_ecspi2: ecspi2-grp {
495 fsl,pins = <
496 MX8MM_IOMUXC_ECSPI2_SC
497 MX8MM_IOMUXC_ECSPI2_MO
498 MX8MM_IOMUXC_ECSPI2_MI
499 MX8MM_IOMUXC_ECSPI2_SS
500 >;
501 };
502
503 pinctrl_ecspi3: ecspi3-grp {
504 fsl,pins = <
505 MX8MM_IOMUXC_UART1_RXD
506 MX8MM_IOMUXC_UART1_TXD
507 MX8MM_IOMUXC_UART2_RXD
508 MX8MM_IOMUXC_UART2_TXD
509 >;
510 };
511
512 pinctrl_fec1: fec1-grp {
513 fsl,pins = <
514 MX8MM_IOMUXC_ENET_MDC_
515 MX8MM_IOMUXC_ENET_MDIO
516 MX8MM_IOMUXC_ENET_RD0_
517 MX8MM_IOMUXC_ENET_RD1_
518 MX8MM_IOMUXC_ENET_RD2_
519 MX8MM_IOMUXC_ENET_RD3_
520 MX8MM_IOMUXC_ENET_RXC_
521 MX8MM_IOMUXC_ENET_RX_C
522 MX8MM_IOMUXC_ENET_TD0_
523 MX8MM_IOMUXC_ENET_TD1_
524 MX8MM_IOMUXC_ENET_TD2_
525 MX8MM_IOMUXC_ENET_TD3_
526 MX8MM_IOMUXC_ENET_TXC_
527 MX8MM_IOMUXC_ENET_TX_C
528 /* ENET_RST# */
529 MX8MM_IOMUXC_GPIO1_IO0
530 /* ENET_WOL# */
531 MX8MM_IOMUXC_GPIO1_IO1
532 /* ENET_INT# */
533 MX8MM_IOMUXC_GPIO1_IO1
534 >;
535 };
536
537 pinctrl_hog_feature: hog-feature-grp {
538 fsl,pins = <
539 /* GPIO4_IO27 */
540 MX8MM_IOMUXC_SAI2_MCLK
541 /* GPIO5_IO03 */
542 MX8MM_IOMUXC_SPDIF_TX_
543 /* GPIO5_IO04 */
544 MX8MM_IOMUXC_SPDIF_RX_
545
546 /* CAN_INT# */
547 MX8MM_IOMUXC_SAI2_TXC_
548 /* CAN_RST# */
549 MX8MM_IOMUXC_SAI2_TXD0
550 >;
551 };
552
553 pinctrl_hog_panel: hog-panel-grp {
554 fsl,pins = <
555 /* GRAPHICS_GPIO0_1V8
556 MX8MM_IOMUXC_NAND_DATA
557 >;
558 };
559
560 pinctrl_hog_misc: hog-misc-grp {
561 fsl,pins = <
562 /* PG_V_IN_VAR# */
563 MX8MM_IOMUXC_NAND_CE0_
564 /* CSI_PD_1V8 */
565 MX8MM_IOMUXC_NAND_DATA
566 /* CSI_RESET_1V8# */
567 MX8MM_IOMUXC_NAND_DATA
568
569 /* DIS_USB_DN1 */
570 MX8MM_IOMUXC_SAI3_TXD_
571 /* DIS_USB_DN2 */
572 MX8MM_IOMUXC_SAI3_RXFS
573
574 /* EEPROM_WP_1V8# */
575 MX8MM_IOMUXC_SD1_DATA3
576 /* PCIE_CLK_GEN_CLKPWR
577 MX8MM_IOMUXC_SD1_DATA4
578 /* GRAPHICS_PRSNT_1V8#
579 MX8MM_IOMUXC_SD1_DATA5
580
581 /* CLK_CCM_CLKO1_3V3 *
582 MX8MM_IOMUXC_GPIO1_IO1
583 >;
584 };
585
586 pinctrl_hog_sbc: hog-sbc-grp {
587 fsl,pins = <
588 /* MEMCFG[0..2] straps
589 MX8MM_IOMUXC_SD1_DATA6
590 MX8MM_IOMUXC_SD1_CMD_G
591 MX8MM_IOMUXC_SD1_CLK_G
592
593 /* BOOT_CFG[0..15] str
594 MX8MM_IOMUXC_SAI1_RXD0
595 MX8MM_IOMUXC_SAI1_RXD1
596 MX8MM_IOMUXC_SAI1_RXD2
597 MX8MM_IOMUXC_SAI1_RXD3
598 MX8MM_IOMUXC_SAI1_RXD4
599 MX8MM_IOMUXC_SAI1_RXD5
600 MX8MM_IOMUXC_SAI1_RXD6
601 MX8MM_IOMUXC_SAI1_RXD7
602 MX8MM_IOMUXC_SAI1_TXD0
603 MX8MM_IOMUXC_SAI1_TXD1
604 MX8MM_IOMUXC_SAI1_TXD2
605 MX8MM_IOMUXC_SAI1_TXD3
606 MX8MM_IOMUXC_SAI1_TXD4
607 MX8MM_IOMUXC_SAI1_TXD5
608 MX8MM_IOMUXC_SAI1_TXD6
609 MX8MM_IOMUXC_SAI1_TXD7
610
611 /* Not connected pins
612 MX8MM_IOMUXC_SAI1_MCLK
613 MX8MM_IOMUXC_SAI1_TXFS
614 MX8MM_IOMUXC_SAI1_TXC_
615 MX8MM_IOMUXC_SAI1_RXFS
616 MX8MM_IOMUXC_SAI1_RXC_
617 >;
618 };
619
620 pinctrl_i2c1: i2c1-grp {
621 fsl,pins = <
622 MX8MM_IOMUXC_I2C1_SCL_
623 MX8MM_IOMUXC_I2C1_SDA_
624 >;
625 };
626
627 pinctrl_i2c1_gpio: i2c1-gpio-grp {
628 fsl,pins = <
629 MX8MM_IOMUXC_I2C1_SCL_
630 MX8MM_IOMUXC_I2C1_SDA_
631 >;
632 };
633
634 pinctrl_i2c2: i2c2-grp {
635 fsl,pins = <
636 MX8MM_IOMUXC_I2C2_SCL_
637 MX8MM_IOMUXC_I2C2_SDA_
638 >;
639 };
640
641 pinctrl_i2c2_gpio: i2c2-gpio-grp {
642 fsl,pins = <
643 MX8MM_IOMUXC_I2C2_SCL_
644 MX8MM_IOMUXC_I2C2_SDA_
645 >;
646 };
647
648 pinctrl_i2c3: i2c3-grp {
649 fsl,pins = <
650 MX8MM_IOMUXC_I2C3_SCL_
651 MX8MM_IOMUXC_I2C3_SDA_
652 >;
653 };
654
655 pinctrl_i2c3_gpio: i2c3-gpio-grp {
656 fsl,pins = <
657 MX8MM_IOMUXC_I2C3_SCL_
658 MX8MM_IOMUXC_I2C3_SDA_
659 >;
660 };
661
662 pinctrl_i2c4: i2c4-grp {
663 fsl,pins = <
664 MX8MM_IOMUXC_I2C4_SCL_
665 MX8MM_IOMUXC_I2C4_SDA_
666 >;
667 };
668
669 pinctrl_i2c4_gpio: i2c4-gpio-grp {
670 fsl,pins = <
671 MX8MM_IOMUXC_I2C4_SCL_
672 MX8MM_IOMUXC_I2C4_SDA_
673 >;
674 };
675
676 pinctrl_panel_backlight: panel-backlig
677 fsl,pins = <
678 /* BL_ENABLE_1V8 */
679 MX8MM_IOMUXC_NAND_ALE_
680 >;
681 };
682
683 pinctrl_panel_expansion: panel-expansi
684 fsl,pins = <
685 /* DSI_RESET_1V8# */
686 MX8MM_IOMUXC_SD1_DATA0
687 /* DSI_IRQ_1V8# */
688 MX8MM_IOMUXC_SD1_DATA1
689 >;
690 };
691
692 pinctrl_panel_vcc_reg: panel-vcc-grp {
693 fsl,pins = <
694 /* TFT_ENABLE_1V8 */
695 MX8MM_IOMUXC_NAND_DATA
696 >;
697 };
698
699 pinctrl_panel_pwm: panel-pwm-grp {
700 fsl,pins = <
701 /* BL_PWM_3V3 */
702 MX8MM_IOMUXC_SPDIF_EXT
703 >;
704 };
705
706 pinctrl_pcie0: pcie-grp {
707 fsl,pins = <
708 /* M2-B_RESET_1V8# */
709 MX8MM_IOMUXC_SAI5_RXC_
710 /* M2-B_PCIE_RST# */
711 MX8MM_IOMUXC_GPIO1_IO0
712 /* M2-B_FULL_CARD_PWRO
713 MX8MM_IOMUXC_SD1_DATA2
714 /* M2-B_W_DISABLE1_WWA
715 MX8MM_IOMUXC_SD1_RESET
716 /* M2-B_W_DISABLE2_GPS
717 MX8MM_IOMUXC_SD1_STROB
718 /* CLK_M2_32K768 */
719 MX8MM_IOMUXC_GPIO1_IO0
720 /* M2-B_WAKE_WWAN_1V8#
721 MX8MM_IOMUXC_SAI5_RXFS
722 /* M2-B_PCIE_WAKE# */
723 MX8MM_IOMUXC_GPIO1_IO0
724 /* M2-B_PCIE_CLKREQ# *
725 MX8MM_IOMUXC_GPIO1_IO0
726 >;
727 };
728
729 pinctrl_pmic: pmic-grp {
730 fsl,pins = <
731 MX8MM_IOMUXC_GPIO1_IO0
732 >;
733 };
734
735 pinctrl_rtc: rtc-grp {
736 fsl,pins = <
737 /* RTC_IRQ# */
738 MX8MM_IOMUXC_GPIO1_IO0
739 >;
740 };
741
742 pinctrl_sai5: sai5-grp {
743 fsl,pins = <
744 MX8MM_IOMUXC_SAI5_MCLK
745 MX8MM_IOMUXC_SAI5_RXD0
746 MX8MM_IOMUXC_SAI5_RXD1
747 MX8MM_IOMUXC_SAI5_RXD2
748 MX8MM_IOMUXC_SAI5_RXD3
749 >;
750 };
751
752 pinctrl_uart1: uart1-grp {
753 fsl,pins = <
754 MX8MM_IOMUXC_SAI2_RXC_
755 MX8MM_IOMUXC_SAI2_RXD0
756 MX8MM_IOMUXC_SAI2_RXFS
757 MX8MM_IOMUXC_SAI2_TXFS
758 >;
759 };
760
761 pinctrl_uart2: uart2-grp {
762 fsl,pins = <
763 MX8MM_IOMUXC_SAI3_RXC_
764 MX8MM_IOMUXC_SAI3_RXD_
765 MX8MM_IOMUXC_SAI3_TXC_
766 MX8MM_IOMUXC_SAI3_TXFS
767 >;
768 };
769
770 pinctrl_uart3: uart3-grp {
771 fsl,pins = <
772 MX8MM_IOMUXC_UART3_RXD
773 MX8MM_IOMUXC_UART3_TXD
774 >;
775 };
776
777 pinctrl_uart4: uart4-grp {
778 fsl,pins = <
779 MX8MM_IOMUXC_UART4_RXD
780 MX8MM_IOMUXC_UART4_TXD
781 >;
782 };
783
784 pinctrl_usb_hub: usb-hub-grp {
785 fsl,pins = <
786 /* USBHUB_RESET# */
787 MX8MM_IOMUXC_SAI3_MCLK
788 >;
789 };
790
791 pinctrl_usb_otg1: usb-otg1-grp {
792 fsl,pins = <
793 MX8MM_IOMUXC_GPIO1_IO1
794 MX8MM_IOMUXC_GPIO1_IO1
795 MX8MM_IOMUXC_GPIO1_IO1
796 >;
797 };
798
799 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg
800 fsl,pins = <
801 MX8MM_IOMUXC_SD2_RESET
802 >;
803 };
804
805 pinctrl_usdhc2: usdhc2-grp {
806 fsl,pins = <
807 MX8MM_IOMUXC_SD2_CLK_U
808 MX8MM_IOMUXC_SD2_CMD_U
809 MX8MM_IOMUXC_SD2_DATA0
810 MX8MM_IOMUXC_SD2_DATA1
811 MX8MM_IOMUXC_SD2_DATA2
812 MX8MM_IOMUXC_SD2_DATA3
813 MX8MM_IOMUXC_SD2_WP_US
814 MX8MM_IOMUXC_SD2_CD_B_
815 MX8MM_IOMUXC_GPIO1_IO0
816 >;
817 };
818
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g
820 fsl,pins = <
821 MX8MM_IOMUXC_SD2_CLK_U
822 MX8MM_IOMUXC_SD2_CMD_U
823 MX8MM_IOMUXC_SD2_DATA0
824 MX8MM_IOMUXC_SD2_DATA1
825 MX8MM_IOMUXC_SD2_DATA2
826 MX8MM_IOMUXC_SD2_DATA3
827 MX8MM_IOMUXC_SD2_WP_US
828 MX8MM_IOMUXC_SD2_CD_B_
829 MX8MM_IOMUXC_GPIO1_IO0
830 >;
831 };
832
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g
834 fsl,pins = <
835 MX8MM_IOMUXC_SD2_CLK_U
836 MX8MM_IOMUXC_SD2_CMD_U
837 MX8MM_IOMUXC_SD2_DATA0
838 MX8MM_IOMUXC_SD2_DATA1
839 MX8MM_IOMUXC_SD2_DATA2
840 MX8MM_IOMUXC_SD2_DATA3
841 MX8MM_IOMUXC_SD2_WP_US
842 MX8MM_IOMUXC_SD2_CD_B_
843 MX8MM_IOMUXC_GPIO1_IO0
844 >;
845 };
846
847 pinctrl_usdhc3: usdhc3-grp {
848 fsl,pins = <
849 MX8MM_IOMUXC_NAND_WE_B
850 MX8MM_IOMUXC_NAND_WP_B
851 MX8MM_IOMUXC_NAND_DATA
852 MX8MM_IOMUXC_NAND_DATA
853 MX8MM_IOMUXC_NAND_DATA
854 MX8MM_IOMUXC_NAND_DATA
855 MX8MM_IOMUXC_NAND_RE_B
856 MX8MM_IOMUXC_NAND_CE2_
857 MX8MM_IOMUXC_NAND_CE3_
858 MX8MM_IOMUXC_NAND_CLE_
859 MX8MM_IOMUXC_NAND_CE1_
860 MX8MM_IOMUXC_NAND_READ
861 >;
862 };
863
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g
865 fsl,pins = <
866 MX8MM_IOMUXC_NAND_WE_B
867 MX8MM_IOMUXC_NAND_WP_B
868 MX8MM_IOMUXC_NAND_DATA
869 MX8MM_IOMUXC_NAND_DATA
870 MX8MM_IOMUXC_NAND_DATA
871 MX8MM_IOMUXC_NAND_DATA
872 MX8MM_IOMUXC_NAND_RE_B
873 MX8MM_IOMUXC_NAND_CE2_
874 MX8MM_IOMUXC_NAND_CE3_
875 MX8MM_IOMUXC_NAND_CLE_
876 MX8MM_IOMUXC_NAND_CE1_
877 MX8MM_IOMUXC_NAND_READ
878 >;
879 };
880
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g
882 fsl,pins = <
883 MX8MM_IOMUXC_NAND_WE_B
884 MX8MM_IOMUXC_NAND_WP_B
885 MX8MM_IOMUXC_NAND_DATA
886 MX8MM_IOMUXC_NAND_DATA
887 MX8MM_IOMUXC_NAND_DATA
888 MX8MM_IOMUXC_NAND_DATA
889 MX8MM_IOMUXC_NAND_RE_B
890 MX8MM_IOMUXC_NAND_CE2_
891 MX8MM_IOMUXC_NAND_CE3_
892 MX8MM_IOMUXC_NAND_CLE_
893 MX8MM_IOMUXC_NAND_CE1_
894 MX8MM_IOMUXC_NAND_READ
895 >;
896 };
897
898 pinctrl_watchdog_gpio: watchdog-gpio-g
899 fsl,pins = <
900 /* WDOG_B# */
901 MX8MM_IOMUXC_GPIO1_IO0
902 /* WDOG_EN -- ungate W
903 MX8MM_IOMUXC_SD1_DATA7
904 /* WDOG_KICK# / WDI */
905 MX8MM_IOMUXC_GPIO1_IO0
906 >;
907 };
908 };
909
910 &pcie_phy {
911 fsl,clkreq-unsupported; /* CLKREQ_B is
912 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
913 fsl,tx-deemph-gen1 = <0x2d>;
914 fsl,tx-deemph-gen2 = <0xf>;
915 clocks = <&pcieclk 0>;
916 status = "okay";
917 };
918
919 &pcie0 {
920 pinctrl-names = "default";
921 pinctrl-0 = <&pinctrl_pcie0>;
922 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW
923 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
924 <&clk IMX8MM_CLK_PCIE1_AUX>;
925 assigned-clocks = <&clk IMX8MM_CLK_PCI
926 <&clk IMX8MM_CLK_PCI
927 assigned-clock-rates = <10000000>, <25
928 assigned-clock-parents = <&clk IMX8MM_
929 <&clk IMX8MM_
930 status = "okay";
931 };
932
933 &pwm1 {
934 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_panel_pwm>;
936 /* Disabled by default, unless display
937 status = "disabled";
938 };
939
940 &sai5 {
941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_sai5>;
943 fsl,sai-mclk-direction-output;
944 /* Input into codec PLL */
945 assigned-clocks = <&clk IMX8MM_CLK_SAI
946 assigned-clock-parents = <&clk IMX8MM_
947 assigned-clock-rates = <22579200>;
948 /* Disabled by default, unless display
949 status = "disabled";
950 };
951
952 &snvs_rtc {
953 clocks = <&pmic>;
954 };
955
956 &uart1 {
957 pinctrl-names = "default";
958 pinctrl-0 = <&pinctrl_uart1>;
959 uart-has-rtscts;
960 status = "disabled";
961 };
962
963 &uart2 {
964 pinctrl-names = "default";
965 pinctrl-0 = <&pinctrl_uart2>;
966 status = "disabled";
967 };
968
969 &uart3 { /* A53 Debug */
970 pinctrl-names = "default";
971 pinctrl-0 = <&pinctrl_uart3>;
972 status = "okay";
973 };
974
975 &uart4 { /* M4 Debug */
976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_uart4>;
978 /* UART4 is reserved for CM and RDC bl
979 status = "disabled";
980 };
981
982 &usbotg1 {
983 pinctrl-names = "default";
984 pinctrl-0 = <&pinctrl_usb_otg1>;
985 dr_mode = "otg";
986 status = "okay";
987 };
988
989 &usbotg2 {
990 disable-over-current;
991 dr_mode = "host";
992 status = "okay";
993 };
994
995 &usdhc2 { /* MicroSD */
996 assigned-clocks = <&clk IMX8MM_CLK_USD
997 pinctrl-names = "default", "state_100m
998 pinctrl-0 = <&pinctrl_usdhc2>;
999 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
1000 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
1001 bus-width = <4>;
1002 vmmc-supply = <®_usdhc2_vcc>;
1003 status = "okay";
1004 };
1005
1006 &usdhc3 { /* eMMC */
1007 assigned-clocks = <&clk IMX8MM_CLK_US
1008 assigned-clock-rates = <400000000>;
1009 pinctrl-names = "default", "state_100
1010 pinctrl-0 = <&pinctrl_usdhc3>;
1011 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
1012 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
1013 bus-width = <8>;
1014 non-removable;
1015 vmmc-supply = <&buck4_reg>;
1016 vqmmc-supply = <&buck5_reg>;
1017 status = "okay";
1018 };
1019
1020 &wdog1 {
1021 status = "okay";
1022 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.