1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Marek Vasut <marex@denx.de> 3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/net/qca-ar803x.h> 8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h> 9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm.dtsi" 10 #include "imx8mm.dtsi"
11 11
12 / { 12 / {
13 model = "Data Modul i.MX8M Mini eDM SB 13 model = "Data Modul i.MX8M Mini eDM SBC";
14 compatible = "dmo,imx8mm-data-modul-ed 14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
15 15
16 aliases { 16 aliases {
17 rtc0 = &rtc; 17 rtc0 = &rtc;
18 rtc1 = &snvs_rtc; 18 rtc1 = &snvs_rtc;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = &uart3; 22 stdout-path = &uart3;
23 }; 23 };
24 24
25 memory@40000000 { 25 memory@40000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 /* There are 1/2/4 GiB options 27 /* There are 1/2/4 GiB options, adjusted by bootloader. */
28 reg = <0x0 0x40000000 0 0x4000 28 reg = <0x0 0x40000000 0 0x40000000>;
29 }; 29 };
30 30
31 backlight: backlight { 31 backlight: backlight {
32 compatible = "pwm-backlight"; 32 compatible = "pwm-backlight";
33 pinctrl-names = "default"; 33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_ba 34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
36 default-brightness-level = <7> 36 default-brightness-level = <7>;
37 enable-gpios = <&gpio3 0 GPIO_ 37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>; 38 pwms = <&pwm1 0 5000000 0>;
39 /* Disabled by default, unless 39 /* Disabled by default, unless display board plugged in. */
40 status = "disabled"; 40 status = "disabled";
41 }; 41 };
42 42
43 clk_xtal25: clk-xtal25 { 43 clk_xtal25: clk-xtal25 {
44 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <25000000>; 46 clock-frequency = <25000000>;
47 }; 47 };
48 48
49 clk_xtal32k: clk-xtal32k { 49 clk_xtal32k: clk-xtal32k {
50 compatible = "fixed-clock"; 50 compatible = "fixed-clock";
51 #clock-cells = <0>; 51 #clock-cells = <0>;
52 clock-frequency = <32768>; 52 clock-frequency = <32768>;
53 }; 53 };
54 54
55 panel: panel { 55 panel: panel {
56 backlight = <&backlight>; 56 backlight = <&backlight>;
57 power-supply = <®_panel_vcc 57 power-supply = <®_panel_vcc>;
58 /* Disabled by default, unless 58 /* Disabled by default, unless display board plugged in. */
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 reg_panel_vcc: regulator-panel-vcc { 62 reg_panel_vcc: regulator-panel-vcc {
63 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_panel_vc 65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
66 regulator-name = "PANEL_VCC"; 66 regulator-name = "PANEL_VCC";
67 regulator-min-microvolt = <500 67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <500 68 regulator-max-microvolt = <5000000>;
69 gpio = <&gpio3 6 0>; 69 gpio = <&gpio3 6 0>;
70 enable-active-high; 70 enable-active-high;
71 /* Disabled by default, unless 71 /* Disabled by default, unless display board plugged in. */
72 status = "disabled"; 72 status = "disabled";
73 }; 73 };
74 74
75 reg_usdhc2_vcc: regulator-usdhc2-vcc { 75 reg_usdhc2_vcc: regulator-usdhc2-vcc {
76 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
77 pinctrl-names = "default"; 77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usdhc2_v 78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
79 regulator-name = "V_3V3_SD"; 79 regulator-name = "V_3V3_SD";
80 regulator-min-microvolt = <330 80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <330 81 regulator-max-microvolt = <3300000>;
82 gpio = <&gpio2 19 0>; 82 gpio = <&gpio2 19 0>;
83 enable-active-high; 83 enable-active-high;
84 }; 84 };
85 85
86 watchdog { 86 watchdog {
87 /* TPS3813 */ 87 /* TPS3813 */
88 pinctrl-names = "default"; 88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_watchdog 89 pinctrl-0 = <&pinctrl_watchdog_gpio>;
90 compatible = "linux,wdt-gpio"; 90 compatible = "linux,wdt-gpio";
91 always-running; 91 always-running;
92 gpios = <&gpio1 8 GPIO_ACTIVE_ 92 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
93 hw_algo = "level"; 93 hw_algo = "level";
94 /* Reset triggers in 2..3 seco 94 /* Reset triggers in 2..3 seconds */
95 hw_margin_ms = <1500>; 95 hw_margin_ms = <1500>;
96 /* Disabled by default */ 96 /* Disabled by default */
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99 }; 99 };
100 100
101 &A53_0 { 101 &A53_0 {
102 cpu-supply = <&buck2_reg>; 102 cpu-supply = <&buck2_reg>;
103 }; 103 };
104 104
105 &A53_1 { 105 &A53_1 {
106 cpu-supply = <&buck2_reg>; 106 cpu-supply = <&buck2_reg>;
107 }; 107 };
108 108
109 &A53_2 { 109 &A53_2 {
110 cpu-supply = <&buck2_reg>; 110 cpu-supply = <&buck2_reg>;
111 }; 111 };
112 112
113 &A53_3 { 113 &A53_3 {
114 cpu-supply = <&buck2_reg>; 114 cpu-supply = <&buck2_reg>;
115 }; 115 };
116 116
117 &ddrc { 117 &ddrc {
118 operating-points-v2 = <&ddrc_opp_table 118 operating-points-v2 = <&ddrc_opp_table>;
119 119
120 ddrc_opp_table: opp-table { 120 ddrc_opp_table: opp-table {
121 compatible = "operating-points 121 compatible = "operating-points-v2";
122 122
123 opp-25000000 { 123 opp-25000000 {
124 opp-hz = /bits/ 64 <25 124 opp-hz = /bits/ 64 <25000000>;
125 }; 125 };
126 126
127 opp-100000000 { 127 opp-100000000 {
128 opp-hz = /bits/ 64 <10 128 opp-hz = /bits/ 64 <100000000>;
129 }; 129 };
130 130
131 opp-750000000 { 131 opp-750000000 {
132 opp-hz = /bits/ 64 <75 132 opp-hz = /bits/ 64 <750000000>;
133 }; 133 };
134 }; 134 };
135 }; 135 };
136 136
137 &ecspi1 { 137 &ecspi1 {
138 pinctrl-names = "default"; 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ecspi1>; 139 pinctrl-0 = <&pinctrl_ecspi1>;
140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
141 status = "okay"; 141 status = "okay";
142 142
143 flash@0 { /* W25Q128FVSI */ 143 flash@0 { /* W25Q128FVSI */
144 compatible = "jedec,spi-nor"; 144 compatible = "jedec,spi-nor";
145 m25p,fast-read; 145 m25p,fast-read;
146 spi-max-frequency = <50000000> 146 spi-max-frequency = <50000000>;
147 reg = <0>; 147 reg = <0>;
148 }; 148 };
149 }; 149 };
150 150
151 &ecspi2 { /* Feature connector SPI */ 151 &ecspi2 { /* Feature connector SPI */
152 pinctrl-names = "default"; 152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_ecspi2>; 153 pinctrl-0 = <&pinctrl_ecspi2>;
154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
155 /* Disabled by default, unless feature 155 /* Disabled by default, unless feature board plugged in. */
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 158
159 &ecspi3 { /* Display connector SPI */ 159 &ecspi3 { /* Display connector SPI */
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_ecspi3>; 161 pinctrl-0 = <&pinctrl_ecspi3>;
162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW> 162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
163 /* Disabled by default, unless display 163 /* Disabled by default, unless display board plugged in. */
164 status = "disabled"; 164 status = "disabled";
165 }; 165 };
166 166
167 &fec1 { 167 &fec1 {
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_fec1>; 169 pinctrl-0 = <&pinctrl_fec1>;
170 phy-mode = "rgmii-id"; 170 phy-mode = "rgmii-id";
171 phy-handle = <&fec1_phy_bcm>; !! 171 phy-handle = <&fec1_phy>;
172 phy-supply = <&buck4_reg>; 172 phy-supply = <&buck4_reg>;
173 fsl,magic-packet; 173 fsl,magic-packet;
174 status = "okay"; 174 status = "okay";
175 175
176 mdio { 176 mdio {
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <0>; 178 #size-cells = <0>;
179 179
180 /* Atheros AR8031 PHY */ 180 /* Atheros AR8031 PHY */
181 fec1_phy_ath: ethernet-phy@0 { !! 181 fec1_phy: ethernet-phy@0 {
182 compatible = "ethernet 182 compatible = "ethernet-phy-ieee802.3-c22";
183 reg = <0>; 183 reg = <0>;
184 /* 184 /*
185 * Dedicated ENET_WOL# 185 * Dedicated ENET_WOL# signal is unused, the PHY
186 * can wake the SoC up 186 * can wake the SoC up via INT signal as well.
187 */ 187 */
188 interrupts-extended = 188 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
189 reset-gpios = <&gpio1 189 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
190 reset-assert-us = <100 190 reset-assert-us = <10000>;
191 reset-deassert-us = <1 191 reset-deassert-us = <10000>;
192 qca,keep-pll-enabled; 192 qca,keep-pll-enabled;
193 vddio-supply = <&vddio 193 vddio-supply = <&vddio>;
194 status = "disabled"; <<
195 194
196 vddio: vddio-regulator 195 vddio: vddio-regulator {
197 regulator-name 196 regulator-name = "VDDIO";
198 regulator-min- 197 regulator-min-microvolt = <1800000>;
199 regulator-max- 198 regulator-max-microvolt = <1800000>;
200 }; 199 };
201 200
202 vddh: vddh-regulator { 201 vddh: vddh-regulator {
203 regulator-name 202 regulator-name = "VDDH";
204 }; 203 };
205 }; <<
206 <<
207 /* Broadcom BCM54213PE PHY */ <<
208 fec1_phy_bcm: ethernet-phy@1 { <<
209 compatible = "ethernet <<
210 reg = <1>; <<
211 /* <<
212 * Dedicated ENET_INT# <<
213 * unused, the PHY doe <<
214 * interrupt. <<
215 */ <<
216 reset-gpios = <&gpio1 <<
217 reset-assert-us = <100 <<
218 reset-deassert-us = <1 <<
219 }; 204 };
220 }; 205 };
221 }; 206 };
222 207
223 &gpio1 { 208 &gpio1 {
224 gpio-line-names = 209 gpio-line-names =
225 "", "ENET_RST#", "WDOG_B#", "P 210 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
226 "", "M2-B_PCIE_RST#", "M2-B_PC 211 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
227 "WDOG_KICK#", "M2-B_PCIE_CLKRE 212 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
228 "USB1_OTG_ID_3V3", "ENET_WOL#" 213 "USB1_OTG_ID_3V3", "ENET_WOL#",
229 "", "", "", "ENET_INT#", 214 "", "", "", "ENET_INT#",
230 "", "", "", "", "", "", "", "" 215 "", "", "", "", "", "", "", "",
231 "", "", "", "", "", "", "", "" 216 "", "", "", "", "", "", "", "";
232 }; 217 };
233 218
234 &gpio2 { 219 &gpio2 {
235 gpio-line-names = 220 gpio-line-names =
236 "MEMCFG2", "MEMCFG1", "DSI_RES 221 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
237 "M2-B_FULL_CARD_PWROFF_1V8#", 222 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
238 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8# 223 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
239 "MEMCFG0", "WDOG_EN", 224 "MEMCFG0", "WDOG_EN",
240 "M2-B_W_DISABLE1_WWAN_1V8#", " 225 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
241 "", "", "", "", 226 "", "", "", "",
242 "", "", "", "SD2_RESET#", "", 227 "", "", "", "SD2_RESET#", "", "", "", "",
243 "", "", "", "", "", "", "", "" 228 "", "", "", "", "", "", "", "";
244 }; 229 };
245 230
246 &gpio3 { 231 &gpio3 {
247 gpio-line-names = 232 gpio-line-names =
248 "BL_ENABLE_1V8", "PG_V_IN_VAR# 233 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
249 "", "", "TFT_ENABLE_1V8", "GRA 234 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
250 "CSI_PD_1V8", "CSI_RESET_1V8#" 235 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
251 "", "", "", "", 236 "", "", "", "",
252 "", "", "", "M2-B_WAKE_WWAN_1V 237 "", "", "", "M2-B_WAKE_WWAN_1V8#",
253 "M2-B_RESET_1V8#", "", "", "", 238 "M2-B_RESET_1V8#", "", "", "",
254 "", "", "", "", "", "", "", "" 239 "", "", "", "", "", "", "", "";
255 }; 240 };
256 241
257 &gpio4 { 242 &gpio4 {
258 gpio-line-names = 243 gpio-line-names =
259 "NC0", "NC1", "BOOTCFG0", "BOO 244 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
260 "BOOTCFG2", "BOOTCFG3", "BOOTC 245 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
261 "BOOTCFG6", "BOOTCFG7", "NC10" 246 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
262 "BOOTCFG8", "BOOTCFG9", "BOOTC 247 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
263 "BOOTCFG12", "BOOTCFG13", "BOO 248 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
264 "NC20", "", "", "", 249 "NC20", "", "", "",
265 "", "CAN_INT#", "CAN_RST#", "G 250 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
266 "DIS_USB_DN2", "", "", ""; 251 "DIS_USB_DN2", "", "", "";
267 }; 252 };
268 253
269 &gpio5 { 254 &gpio5 {
270 gpio-line-names = 255 gpio-line-names =
271 "", "DIS_USB_DN1", "USBHUB_RES 256 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
272 "GPIO5_IO04", "", "", "", 257 "GPIO5_IO04", "", "", "",
273 "", "SPI1_CS#", "", "", 258 "", "SPI1_CS#", "", "",
274 "", "SPI2_CS#", "I2C1_SCL_3V3" 259 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
275 "I2C2_SCL_3V3", "I2C2_SDA_3V3" 260 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
276 "I2C4_SCL_3V3", "I2C4_SDA_3V3" 261 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
277 "", "SPI3_CS#", "", "", "", "" 262 "", "SPI3_CS#", "", "", "", "", "", "";
278 }; 263 };
279 264
280 &i2c1 { 265 &i2c1 {
281 /* IMX8MM ERRATA e7805 -- I2C is limit 266 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
282 clock-frequency = <100000>; 267 clock-frequency = <100000>;
283 pinctrl-names = "default", "gpio"; 268 pinctrl-names = "default", "gpio";
284 pinctrl-0 = <&pinctrl_i2c1>; 269 pinctrl-0 = <&pinctrl_i2c1>;
285 pinctrl-1 = <&pinctrl_i2c1_gpio>; 270 pinctrl-1 = <&pinctrl_i2c1_gpio>;
286 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
287 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
288 status = "okay"; 273 status = "okay";
289 274
290 pmic: pmic@4b { 275 pmic: pmic@4b {
291 compatible = "rohm,bd71847"; 276 compatible = "rohm,bd71847";
292 reg = <0x4b>; 277 reg = <0x4b>;
293 #clock-cells = <0>; 278 #clock-cells = <0>;
294 clocks = <&clk_xtal32k>; 279 clocks = <&clk_xtal32k>;
295 clock-output-names = "clk-32k- 280 clock-output-names = "clk-32k-out";
296 pinctrl-names = "default"; 281 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_pmic>; 282 pinctrl-0 = <&pinctrl_pmic>;
298 interrupt-parent = <&gpio1>; 283 interrupt-parent = <&gpio1>;
299 interrupts = <3 IRQ_TYPE_EDGE_ 284 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
300 rohm,reset-snvs-powered; 285 rohm,reset-snvs-powered;
301 286
302 /* 287 /*
303 * i.MX 8M Mini Data Sheet for 288 * i.MX 8M Mini Data Sheet for Consumer Products
304 * 3.1.3 Operating ranges 289 * 3.1.3 Operating ranges
305 * MIMX8MM4DVTLZAA 290 * MIMX8MM4DVTLZAA
306 */ 291 */
307 regulators { 292 regulators {
308 /* VDD_SOC */ 293 /* VDD_SOC */
309 buck1_reg: BUCK1 { 294 buck1_reg: BUCK1 {
310 regulator-name 295 regulator-name = "buck1";
311 regulator-min- 296 regulator-min-microvolt = <850000>;
312 regulator-max- 297 regulator-max-microvolt = <850000>;
313 regulator-boot 298 regulator-boot-on;
314 regulator-alwa 299 regulator-always-on;
315 regulator-ramp 300 regulator-ramp-delay = <1250>;
316 }; 301 };
317 302
318 /* VDD_ARM */ 303 /* VDD_ARM */
319 buck2_reg: BUCK2 { 304 buck2_reg: BUCK2 {
320 regulator-name 305 regulator-name = "buck2";
321 regulator-min- 306 regulator-min-microvolt = <850000>;
322 regulator-max- 307 regulator-max-microvolt = <1050000>;
323 regulator-boot 308 regulator-boot-on;
324 regulator-alwa 309 regulator-always-on;
325 regulator-ramp 310 regulator-ramp-delay = <1250>;
326 rohm,dvs-run-v 311 rohm,dvs-run-voltage = <1000000>;
327 rohm,dvs-idle- 312 rohm,dvs-idle-voltage = <950000>;
328 }; 313 };
329 314
330 /* VDD_DRAM, BUCK5 */ 315 /* VDD_DRAM, BUCK5 */
331 buck3_reg: BUCK3 { 316 buck3_reg: BUCK3 {
332 regulator-name 317 regulator-name = "buck3";
333 /* 1.5 GHz DDR 318 /* 1.5 GHz DDR bus clock */
334 regulator-min- 319 regulator-min-microvolt = <900000>;
335 regulator-max- 320 regulator-max-microvolt = <1000000>;
336 regulator-boot 321 regulator-boot-on;
337 regulator-alwa 322 regulator-always-on;
338 }; 323 };
339 324
340 /* 3V3_VDD, BUCK6 */ 325 /* 3V3_VDD, BUCK6 */
341 buck4_reg: BUCK4 { 326 buck4_reg: BUCK4 {
342 regulator-name 327 regulator-name = "buck4";
343 regulator-min- 328 regulator-min-microvolt = <3300000>;
344 regulator-max- 329 regulator-max-microvolt = <3300000>;
345 regulator-boot 330 regulator-boot-on;
346 regulator-alwa 331 regulator-always-on;
347 }; 332 };
348 333
349 /* 1V8_VDD, BUCK7 */ 334 /* 1V8_VDD, BUCK7 */
350 buck5_reg: BUCK5 { 335 buck5_reg: BUCK5 {
351 regulator-name 336 regulator-name = "buck5";
352 regulator-min- 337 regulator-min-microvolt = <1800000>;
353 regulator-max- 338 regulator-max-microvolt = <1800000>;
354 regulator-boot 339 regulator-boot-on;
355 regulator-alwa 340 regulator-always-on;
356 }; 341 };
357 342
358 /* 1V1_NVCC_DRAM, BUCK 343 /* 1V1_NVCC_DRAM, BUCK8 */
359 buck6_reg: BUCK6 { 344 buck6_reg: BUCK6 {
360 regulator-name 345 regulator-name = "buck6";
361 regulator-min- 346 regulator-min-microvolt = <1100000>;
362 regulator-max- 347 regulator-max-microvolt = <1100000>;
363 regulator-boot 348 regulator-boot-on;
364 regulator-alwa 349 regulator-always-on;
365 }; 350 };
366 351
367 /* 1V8_NVCC_SNVS */ 352 /* 1V8_NVCC_SNVS */
368 ldo1_reg: LDO1 { 353 ldo1_reg: LDO1 {
369 regulator-name 354 regulator-name = "ldo1";
370 regulator-min- 355 regulator-min-microvolt = <1800000>;
371 regulator-max- 356 regulator-max-microvolt = <1800000>;
372 regulator-boot 357 regulator-boot-on;
373 regulator-alwa 358 regulator-always-on;
374 }; 359 };
375 360
376 /* 0V8_VDD_SNVS */ 361 /* 0V8_VDD_SNVS */
377 ldo2_reg: LDO2 { 362 ldo2_reg: LDO2 {
378 regulator-name 363 regulator-name = "ldo2";
379 regulator-min- 364 regulator-min-microvolt = <800000>;
380 regulator-max- 365 regulator-max-microvolt = <800000>;
381 regulator-boot 366 regulator-boot-on;
382 regulator-alwa 367 regulator-always-on;
383 }; 368 };
384 369
385 /* 1V8_VDDA */ 370 /* 1V8_VDDA */
386 ldo3_reg: LDO3 { 371 ldo3_reg: LDO3 {
387 regulator-name 372 regulator-name = "ldo3";
388 regulator-min- 373 regulator-min-microvolt = <1800000>;
389 regulator-max- 374 regulator-max-microvolt = <1800000>;
390 regulator-boot 375 regulator-boot-on;
391 regulator-alwa 376 regulator-always-on;
392 }; 377 };
393 378
394 /* 0V9_VDD_PHY */ 379 /* 0V9_VDD_PHY */
395 ldo4_reg: LDO4 { 380 ldo4_reg: LDO4 {
396 regulator-name 381 regulator-name = "ldo4";
397 regulator-min- 382 regulator-min-microvolt = <900000>;
398 regulator-max- 383 regulator-max-microvolt = <900000>;
399 regulator-boot 384 regulator-boot-on;
400 regulator-alwa 385 regulator-always-on;
401 }; 386 };
402 387
403 /* 1V2_VDD_PHY */ 388 /* 1V2_VDD_PHY */
404 ldo6_reg: LDO6 { 389 ldo6_reg: LDO6 {
405 regulator-name 390 regulator-name = "ldo6";
406 regulator-min- 391 regulator-min-microvolt = <1200000>;
407 regulator-max- 392 regulator-max-microvolt = <1200000>;
408 regulator-boot 393 regulator-boot-on;
409 regulator-alwa 394 regulator-always-on;
410 }; 395 };
411 }; 396 };
412 }; 397 };
413 }; 398 };
414 399
415 &i2c2 { 400 &i2c2 {
416 /* IMX8MM ERRATA e7805 -- I2C is limit 401 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
417 clock-frequency = <100000>; 402 clock-frequency = <100000>;
418 pinctrl-names = "default", "gpio"; 403 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c2>; 404 pinctrl-0 = <&pinctrl_i2c2>;
420 pinctrl-1 = <&pinctrl_i2c2_gpio>; 405 pinctrl-1 = <&pinctrl_i2c2_gpio>;
421 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 406 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
422 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 407 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
423 status = "okay"; 408 status = "okay";
424 409
425 usb-hub@2c { 410 usb-hub@2c {
426 pinctrl-names = "default"; 411 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_usb_hub> 412 pinctrl-0 = <&pinctrl_usb_hub>;
428 compatible = "microchip,usb251 413 compatible = "microchip,usb2514bi";
429 reg = <0x2c>; 414 reg = <0x2c>;
430 individual-port-switching; 415 individual-port-switching;
431 reset-gpios = <&gpio5 2 GPIO_A 416 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
432 self-powered; 417 self-powered;
433 }; 418 };
434 419
435 eeprom: eeprom@50 { 420 eeprom: eeprom@50 {
436 compatible = "atmel,24c32"; 421 compatible = "atmel,24c32";
437 reg = <0x50>; 422 reg = <0x50>;
438 pagesize = <32>; 423 pagesize = <32>;
439 }; 424 };
440 425
441 rtc: rtc@68 { 426 rtc: rtc@68 {
442 pinctrl-names = "default"; 427 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_rtc>; 428 pinctrl-0 = <&pinctrl_rtc>;
444 compatible = "st,m41t62"; 429 compatible = "st,m41t62";
445 reg = <0x68>; 430 reg = <0x68>;
446 interrupts-extended = <&gpio1 431 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
447 }; 432 };
448 433
449 pcieclk: clk@6a { 434 pcieclk: clk@6a {
450 compatible = "renesas,9fgv0241 435 compatible = "renesas,9fgv0241";
451 reg = <0x6a>; 436 reg = <0x6a>;
452 clocks = <&clk_xtal25>; 437 clocks = <&clk_xtal25>;
453 #clock-cells = <1>; 438 #clock-cells = <1>;
454 }; 439 };
455 }; 440 };
456 441
457 &i2c3 { /* Display connector I2C */ 442 &i2c3 { /* Display connector I2C */
458 /* IMX8MM ERRATA e7805 -- I2C is limit 443 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
459 clock-frequency = <320000>; 444 clock-frequency = <320000>;
460 pinctrl-names = "default", "gpio"; 445 pinctrl-names = "default", "gpio";
461 pinctrl-0 = <&pinctrl_i2c3>; 446 pinctrl-0 = <&pinctrl_i2c3>;
462 pinctrl-1 = <&pinctrl_i2c3_gpio>; 447 pinctrl-1 = <&pinctrl_i2c3_gpio>;
463 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 448 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
464 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 449 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
465 status = "okay"; 450 status = "okay";
466 }; 451 };
467 452
468 &i2c4 { /* Feature connector I2C */ 453 &i2c4 { /* Feature connector I2C */
469 /* IMX8MM ERRATA e7805 -- I2C is limit 454 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
470 clock-frequency = <320000>; 455 clock-frequency = <320000>;
471 pinctrl-names = "default", "gpio"; 456 pinctrl-names = "default", "gpio";
472 pinctrl-0 = <&pinctrl_i2c4>; 457 pinctrl-0 = <&pinctrl_i2c4>;
473 pinctrl-1 = <&pinctrl_i2c4_gpio>; 458 pinctrl-1 = <&pinctrl_i2c4_gpio>;
474 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 459 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
475 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 460 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
476 status = "okay"; 461 status = "okay";
477 }; 462 };
478 463
479 &iomuxc { 464 &iomuxc {
480 pinctrl-names = "default"; 465 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_hog_feature>, <& 466 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
482 <&pinctrl_hog_panel>, <&pi 467 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
483 <&pinctrl_panel_expansion> 468 <&pinctrl_panel_expansion>;
484 469
485 pinctrl_ecspi1: ecspi1-grp { 470 pinctrl_ecspi1: ecspi1-grp {
486 fsl,pins = < 471 fsl,pins = <
487 MX8MM_IOMUXC_ECSPI1_SC 472 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
488 MX8MM_IOMUXC_ECSPI1_MO 473 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
489 MX8MM_IOMUXC_ECSPI1_MI 474 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
490 MX8MM_IOMUXC_ECSPI1_SS 475 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
491 >; 476 >;
492 }; 477 };
493 478
494 pinctrl_ecspi2: ecspi2-grp { 479 pinctrl_ecspi2: ecspi2-grp {
495 fsl,pins = < 480 fsl,pins = <
496 MX8MM_IOMUXC_ECSPI2_SC 481 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
497 MX8MM_IOMUXC_ECSPI2_MO 482 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
498 MX8MM_IOMUXC_ECSPI2_MI 483 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
499 MX8MM_IOMUXC_ECSPI2_SS 484 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
500 >; 485 >;
501 }; 486 };
502 487
503 pinctrl_ecspi3: ecspi3-grp { 488 pinctrl_ecspi3: ecspi3-grp {
504 fsl,pins = < 489 fsl,pins = <
505 MX8MM_IOMUXC_UART1_RXD 490 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
506 MX8MM_IOMUXC_UART1_TXD 491 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
507 MX8MM_IOMUXC_UART2_RXD 492 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
508 MX8MM_IOMUXC_UART2_TXD 493 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
509 >; 494 >;
510 }; 495 };
511 496
512 pinctrl_fec1: fec1-grp { 497 pinctrl_fec1: fec1-grp {
513 fsl,pins = < 498 fsl,pins = <
514 MX8MM_IOMUXC_ENET_MDC_ 499 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MM_IOMUXC_ENET_MDIO 500 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
516 MX8MM_IOMUXC_ENET_RD0_ 501 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
517 MX8MM_IOMUXC_ENET_RD1_ 502 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
518 MX8MM_IOMUXC_ENET_RD2_ 503 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
519 MX8MM_IOMUXC_ENET_RD3_ 504 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
520 MX8MM_IOMUXC_ENET_RXC_ 505 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
521 MX8MM_IOMUXC_ENET_RX_C 506 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
522 MX8MM_IOMUXC_ENET_TD0_ 507 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
523 MX8MM_IOMUXC_ENET_TD1_ 508 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
524 MX8MM_IOMUXC_ENET_TD2_ 509 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
525 MX8MM_IOMUXC_ENET_TD3_ 510 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
526 MX8MM_IOMUXC_ENET_TXC_ 511 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
527 MX8MM_IOMUXC_ENET_TX_C 512 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 /* ENET_RST# */ 513 /* ENET_RST# */
529 MX8MM_IOMUXC_GPIO1_IO0 514 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
530 /* ENET_WOL# */ 515 /* ENET_WOL# */
531 MX8MM_IOMUXC_GPIO1_IO1 516 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
532 /* ENET_INT# */ 517 /* ENET_INT# */
533 MX8MM_IOMUXC_GPIO1_IO1 518 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
534 >; 519 >;
535 }; 520 };
536 521
537 pinctrl_hog_feature: hog-feature-grp { 522 pinctrl_hog_feature: hog-feature-grp {
538 fsl,pins = < 523 fsl,pins = <
539 /* GPIO4_IO27 */ 524 /* GPIO4_IO27 */
540 MX8MM_IOMUXC_SAI2_MCLK 525 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
541 /* GPIO5_IO03 */ 526 /* GPIO5_IO03 */
542 MX8MM_IOMUXC_SPDIF_TX_ 527 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
543 /* GPIO5_IO04 */ 528 /* GPIO5_IO04 */
544 MX8MM_IOMUXC_SPDIF_RX_ 529 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
545 530
546 /* CAN_INT# */ 531 /* CAN_INT# */
547 MX8MM_IOMUXC_SAI2_TXC_ 532 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
548 /* CAN_RST# */ 533 /* CAN_RST# */
549 MX8MM_IOMUXC_SAI2_TXD0 534 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
550 >; 535 >;
551 }; 536 };
552 537
553 pinctrl_hog_panel: hog-panel-grp { 538 pinctrl_hog_panel: hog-panel-grp {
554 fsl,pins = < 539 fsl,pins = <
555 /* GRAPHICS_GPIO0_1V8 540 /* GRAPHICS_GPIO0_1V8 */
556 MX8MM_IOMUXC_NAND_DATA 541 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
557 >; 542 >;
558 }; 543 };
559 544
560 pinctrl_hog_misc: hog-misc-grp { 545 pinctrl_hog_misc: hog-misc-grp {
561 fsl,pins = < 546 fsl,pins = <
562 /* PG_V_IN_VAR# */ 547 /* PG_V_IN_VAR# */
563 MX8MM_IOMUXC_NAND_CE0_ 548 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
564 /* CSI_PD_1V8 */ 549 /* CSI_PD_1V8 */
565 MX8MM_IOMUXC_NAND_DATA 550 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
566 /* CSI_RESET_1V8# */ 551 /* CSI_RESET_1V8# */
567 MX8MM_IOMUXC_NAND_DATA 552 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
568 553
569 /* DIS_USB_DN1 */ 554 /* DIS_USB_DN1 */
570 MX8MM_IOMUXC_SAI3_TXD_ 555 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
571 /* DIS_USB_DN2 */ 556 /* DIS_USB_DN2 */
572 MX8MM_IOMUXC_SAI3_RXFS 557 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
573 558
574 /* EEPROM_WP_1V8# */ 559 /* EEPROM_WP_1V8# */
575 MX8MM_IOMUXC_SD1_DATA3 560 MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
576 /* PCIE_CLK_GEN_CLKPWR 561 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
577 MX8MM_IOMUXC_SD1_DATA4 562 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
578 /* GRAPHICS_PRSNT_1V8# 563 /* GRAPHICS_PRSNT_1V8# */
579 MX8MM_IOMUXC_SD1_DATA5 564 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
580 565
581 /* CLK_CCM_CLKO1_3V3 * 566 /* CLK_CCM_CLKO1_3V3 */
582 MX8MM_IOMUXC_GPIO1_IO1 567 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
583 >; 568 >;
584 }; 569 };
585 570
586 pinctrl_hog_sbc: hog-sbc-grp { 571 pinctrl_hog_sbc: hog-sbc-grp {
587 fsl,pins = < 572 fsl,pins = <
588 /* MEMCFG[0..2] straps 573 /* MEMCFG[0..2] straps */
589 MX8MM_IOMUXC_SD1_DATA6 574 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
590 MX8MM_IOMUXC_SD1_CMD_G 575 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
591 MX8MM_IOMUXC_SD1_CLK_G 576 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
592 577
593 /* BOOT_CFG[0..15] str 578 /* BOOT_CFG[0..15] straps */
594 MX8MM_IOMUXC_SAI1_RXD0 579 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
595 MX8MM_IOMUXC_SAI1_RXD1 580 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
596 MX8MM_IOMUXC_SAI1_RXD2 581 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
597 MX8MM_IOMUXC_SAI1_RXD3 582 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
598 MX8MM_IOMUXC_SAI1_RXD4 583 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
599 MX8MM_IOMUXC_SAI1_RXD5 584 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
600 MX8MM_IOMUXC_SAI1_RXD6 585 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
601 MX8MM_IOMUXC_SAI1_RXD7 586 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
602 MX8MM_IOMUXC_SAI1_TXD0 587 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
603 MX8MM_IOMUXC_SAI1_TXD1 588 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
604 MX8MM_IOMUXC_SAI1_TXD2 589 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
605 MX8MM_IOMUXC_SAI1_TXD3 590 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
606 MX8MM_IOMUXC_SAI1_TXD4 591 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
607 MX8MM_IOMUXC_SAI1_TXD5 592 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
608 MX8MM_IOMUXC_SAI1_TXD6 593 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
609 MX8MM_IOMUXC_SAI1_TXD7 594 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
610 595
611 /* Not connected pins 596 /* Not connected pins */
612 MX8MM_IOMUXC_SAI1_MCLK 597 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
613 MX8MM_IOMUXC_SAI1_TXFS 598 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
614 MX8MM_IOMUXC_SAI1_TXC_ 599 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
615 MX8MM_IOMUXC_SAI1_RXFS 600 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
616 MX8MM_IOMUXC_SAI1_RXC_ 601 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
617 >; 602 >;
618 }; 603 };
619 604
620 pinctrl_i2c1: i2c1-grp { 605 pinctrl_i2c1: i2c1-grp {
621 fsl,pins = < 606 fsl,pins = <
622 MX8MM_IOMUXC_I2C1_SCL_ 607 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
623 MX8MM_IOMUXC_I2C1_SDA_ 608 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
624 >; 609 >;
625 }; 610 };
626 611
627 pinctrl_i2c1_gpio: i2c1-gpio-grp { 612 pinctrl_i2c1_gpio: i2c1-gpio-grp {
628 fsl,pins = < 613 fsl,pins = <
629 MX8MM_IOMUXC_I2C1_SCL_ 614 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
630 MX8MM_IOMUXC_I2C1_SDA_ 615 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
631 >; 616 >;
632 }; 617 };
633 618
634 pinctrl_i2c2: i2c2-grp { 619 pinctrl_i2c2: i2c2-grp {
635 fsl,pins = < 620 fsl,pins = <
636 MX8MM_IOMUXC_I2C2_SCL_ 621 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
637 MX8MM_IOMUXC_I2C2_SDA_ 622 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
638 >; 623 >;
639 }; 624 };
640 625
641 pinctrl_i2c2_gpio: i2c2-gpio-grp { 626 pinctrl_i2c2_gpio: i2c2-gpio-grp {
642 fsl,pins = < 627 fsl,pins = <
643 MX8MM_IOMUXC_I2C2_SCL_ 628 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
644 MX8MM_IOMUXC_I2C2_SDA_ 629 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
645 >; 630 >;
646 }; 631 };
647 632
648 pinctrl_i2c3: i2c3-grp { 633 pinctrl_i2c3: i2c3-grp {
649 fsl,pins = < 634 fsl,pins = <
650 MX8MM_IOMUXC_I2C3_SCL_ 635 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
651 MX8MM_IOMUXC_I2C3_SDA_ 636 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
652 >; 637 >;
653 }; 638 };
654 639
655 pinctrl_i2c3_gpio: i2c3-gpio-grp { 640 pinctrl_i2c3_gpio: i2c3-gpio-grp {
656 fsl,pins = < 641 fsl,pins = <
657 MX8MM_IOMUXC_I2C3_SCL_ 642 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
658 MX8MM_IOMUXC_I2C3_SDA_ 643 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
659 >; 644 >;
660 }; 645 };
661 646
662 pinctrl_i2c4: i2c4-grp { 647 pinctrl_i2c4: i2c4-grp {
663 fsl,pins = < 648 fsl,pins = <
664 MX8MM_IOMUXC_I2C4_SCL_ 649 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
665 MX8MM_IOMUXC_I2C4_SDA_ 650 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
666 >; 651 >;
667 }; 652 };
668 653
669 pinctrl_i2c4_gpio: i2c4-gpio-grp { 654 pinctrl_i2c4_gpio: i2c4-gpio-grp {
670 fsl,pins = < 655 fsl,pins = <
671 MX8MM_IOMUXC_I2C4_SCL_ 656 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
672 MX8MM_IOMUXC_I2C4_SDA_ 657 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
673 >; 658 >;
674 }; 659 };
675 660
676 pinctrl_panel_backlight: panel-backlig 661 pinctrl_panel_backlight: panel-backlight-grp {
677 fsl,pins = < 662 fsl,pins = <
678 /* BL_ENABLE_1V8 */ 663 /* BL_ENABLE_1V8 */
679 MX8MM_IOMUXC_NAND_ALE_ 664 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
680 >; 665 >;
681 }; 666 };
682 667
683 pinctrl_panel_expansion: panel-expansi 668 pinctrl_panel_expansion: panel-expansion-grp {
684 fsl,pins = < 669 fsl,pins = <
685 /* DSI_RESET_1V8# */ 670 /* DSI_RESET_1V8# */
686 MX8MM_IOMUXC_SD1_DATA0 671 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
687 /* DSI_IRQ_1V8# */ 672 /* DSI_IRQ_1V8# */
688 MX8MM_IOMUXC_SD1_DATA1 673 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
689 >; 674 >;
690 }; 675 };
691 676
692 pinctrl_panel_vcc_reg: panel-vcc-grp { 677 pinctrl_panel_vcc_reg: panel-vcc-grp {
693 fsl,pins = < 678 fsl,pins = <
694 /* TFT_ENABLE_1V8 */ 679 /* TFT_ENABLE_1V8 */
695 MX8MM_IOMUXC_NAND_DATA 680 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
696 >; 681 >;
697 }; 682 };
698 683
699 pinctrl_panel_pwm: panel-pwm-grp { 684 pinctrl_panel_pwm: panel-pwm-grp {
700 fsl,pins = < 685 fsl,pins = <
701 /* BL_PWM_3V3 */ 686 /* BL_PWM_3V3 */
702 MX8MM_IOMUXC_SPDIF_EXT 687 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
703 >; 688 >;
704 }; 689 };
705 690
706 pinctrl_pcie0: pcie-grp { 691 pinctrl_pcie0: pcie-grp {
707 fsl,pins = < 692 fsl,pins = <
708 /* M2-B_RESET_1V8# */ 693 /* M2-B_RESET_1V8# */
709 MX8MM_IOMUXC_SAI5_RXC_ 694 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
710 /* M2-B_PCIE_RST# */ 695 /* M2-B_PCIE_RST# */
711 MX8MM_IOMUXC_GPIO1_IO0 696 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
712 /* M2-B_FULL_CARD_PWRO 697 /* M2-B_FULL_CARD_PWROFF_1V8# */
713 MX8MM_IOMUXC_SD1_DATA2 698 MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
714 /* M2-B_W_DISABLE1_WWA 699 /* M2-B_W_DISABLE1_WWAN_1V8# */
715 MX8MM_IOMUXC_SD1_RESET 700 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
716 /* M2-B_W_DISABLE2_GPS 701 /* M2-B_W_DISABLE2_GPS_1V8# */
717 MX8MM_IOMUXC_SD1_STROB 702 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
718 /* CLK_M2_32K768 */ 703 /* CLK_M2_32K768 */
719 MX8MM_IOMUXC_GPIO1_IO0 704 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
720 /* M2-B_WAKE_WWAN_1V8# 705 /* M2-B_WAKE_WWAN_1V8# */
721 MX8MM_IOMUXC_SAI5_RXFS 706 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
722 /* M2-B_PCIE_WAKE# */ 707 /* M2-B_PCIE_WAKE# */
723 MX8MM_IOMUXC_GPIO1_IO0 708 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
724 /* M2-B_PCIE_CLKREQ# * 709 /* M2-B_PCIE_CLKREQ# */
725 MX8MM_IOMUXC_GPIO1_IO0 710 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
726 >; 711 >;
727 }; 712 };
728 713
729 pinctrl_pmic: pmic-grp { 714 pinctrl_pmic: pmic-grp {
730 fsl,pins = < 715 fsl,pins = <
731 MX8MM_IOMUXC_GPIO1_IO0 716 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
732 >; 717 >;
733 }; 718 };
734 719
735 pinctrl_rtc: rtc-grp { 720 pinctrl_rtc: rtc-grp {
736 fsl,pins = < 721 fsl,pins = <
737 /* RTC_IRQ# */ 722 /* RTC_IRQ# */
738 MX8MM_IOMUXC_GPIO1_IO0 723 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
739 >; 724 >;
740 }; 725 };
741 726
742 pinctrl_sai5: sai5-grp { 727 pinctrl_sai5: sai5-grp {
743 fsl,pins = < 728 fsl,pins = <
744 MX8MM_IOMUXC_SAI5_MCLK 729 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
745 MX8MM_IOMUXC_SAI5_RXD0 730 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
746 MX8MM_IOMUXC_SAI5_RXD1 731 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
747 MX8MM_IOMUXC_SAI5_RXD2 732 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
748 MX8MM_IOMUXC_SAI5_RXD3 733 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
749 >; 734 >;
750 }; 735 };
751 736
752 pinctrl_uart1: uart1-grp { 737 pinctrl_uart1: uart1-grp {
753 fsl,pins = < 738 fsl,pins = <
754 MX8MM_IOMUXC_SAI2_RXC_ 739 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
755 MX8MM_IOMUXC_SAI2_RXD0 740 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
756 MX8MM_IOMUXC_SAI2_RXFS 741 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
757 MX8MM_IOMUXC_SAI2_TXFS 742 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
758 >; 743 >;
759 }; 744 };
760 745
761 pinctrl_uart2: uart2-grp { 746 pinctrl_uart2: uart2-grp {
762 fsl,pins = < 747 fsl,pins = <
763 MX8MM_IOMUXC_SAI3_RXC_ 748 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
764 MX8MM_IOMUXC_SAI3_RXD_ 749 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
765 MX8MM_IOMUXC_SAI3_TXC_ 750 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
766 MX8MM_IOMUXC_SAI3_TXFS 751 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
767 >; 752 >;
768 }; 753 };
769 754
770 pinctrl_uart3: uart3-grp { 755 pinctrl_uart3: uart3-grp {
771 fsl,pins = < 756 fsl,pins = <
772 MX8MM_IOMUXC_UART3_RXD 757 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
773 MX8MM_IOMUXC_UART3_TXD 758 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
774 >; 759 >;
775 }; 760 };
776 761
777 pinctrl_uart4: uart4-grp { 762 pinctrl_uart4: uart4-grp {
778 fsl,pins = < 763 fsl,pins = <
779 MX8MM_IOMUXC_UART4_RXD 764 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
780 MX8MM_IOMUXC_UART4_TXD 765 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
781 >; 766 >;
782 }; 767 };
783 768
784 pinctrl_usb_hub: usb-hub-grp { 769 pinctrl_usb_hub: usb-hub-grp {
785 fsl,pins = < 770 fsl,pins = <
786 /* USBHUB_RESET# */ 771 /* USBHUB_RESET# */
787 MX8MM_IOMUXC_SAI3_MCLK 772 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
788 >; 773 >;
789 }; 774 };
790 775
791 pinctrl_usb_otg1: usb-otg1-grp { 776 pinctrl_usb_otg1: usb-otg1-grp {
792 fsl,pins = < 777 fsl,pins = <
793 MX8MM_IOMUXC_GPIO1_IO1 778 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
794 MX8MM_IOMUXC_GPIO1_IO1 779 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
795 MX8MM_IOMUXC_GPIO1_IO1 780 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
796 >; 781 >;
797 }; 782 };
798 783
799 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg 784 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
800 fsl,pins = < 785 fsl,pins = <
801 MX8MM_IOMUXC_SD2_RESET 786 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
802 >; 787 >;
803 }; 788 };
804 789
805 pinctrl_usdhc2: usdhc2-grp { 790 pinctrl_usdhc2: usdhc2-grp {
806 fsl,pins = < 791 fsl,pins = <
807 MX8MM_IOMUXC_SD2_CLK_U 792 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
808 MX8MM_IOMUXC_SD2_CMD_U 793 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
809 MX8MM_IOMUXC_SD2_DATA0 794 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
810 MX8MM_IOMUXC_SD2_DATA1 795 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
811 MX8MM_IOMUXC_SD2_DATA2 796 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
812 MX8MM_IOMUXC_SD2_DATA3 797 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
813 MX8MM_IOMUXC_SD2_WP_US 798 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
814 MX8MM_IOMUXC_SD2_CD_B_ 799 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
815 MX8MM_IOMUXC_GPIO1_IO0 800 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 801 >;
817 }; 802 };
818 803
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g 804 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
820 fsl,pins = < 805 fsl,pins = <
821 MX8MM_IOMUXC_SD2_CLK_U 806 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
822 MX8MM_IOMUXC_SD2_CMD_U 807 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
823 MX8MM_IOMUXC_SD2_DATA0 808 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
824 MX8MM_IOMUXC_SD2_DATA1 809 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
825 MX8MM_IOMUXC_SD2_DATA2 810 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
826 MX8MM_IOMUXC_SD2_DATA3 811 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
827 MX8MM_IOMUXC_SD2_WP_US 812 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
828 MX8MM_IOMUXC_SD2_CD_B_ 813 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
829 MX8MM_IOMUXC_GPIO1_IO0 814 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
830 >; 815 >;
831 }; 816 };
832 817
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g 818 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
834 fsl,pins = < 819 fsl,pins = <
835 MX8MM_IOMUXC_SD2_CLK_U 820 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
836 MX8MM_IOMUXC_SD2_CMD_U 821 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
837 MX8MM_IOMUXC_SD2_DATA0 822 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
838 MX8MM_IOMUXC_SD2_DATA1 823 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
839 MX8MM_IOMUXC_SD2_DATA2 824 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
840 MX8MM_IOMUXC_SD2_DATA3 825 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
841 MX8MM_IOMUXC_SD2_WP_US 826 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
842 MX8MM_IOMUXC_SD2_CD_B_ 827 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
843 MX8MM_IOMUXC_GPIO1_IO0 828 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
844 >; 829 >;
845 }; 830 };
846 831
847 pinctrl_usdhc3: usdhc3-grp { 832 pinctrl_usdhc3: usdhc3-grp {
848 fsl,pins = < 833 fsl,pins = <
849 MX8MM_IOMUXC_NAND_WE_B 834 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
850 MX8MM_IOMUXC_NAND_WP_B 835 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
851 MX8MM_IOMUXC_NAND_DATA 836 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
852 MX8MM_IOMUXC_NAND_DATA 837 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
853 MX8MM_IOMUXC_NAND_DATA 838 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
854 MX8MM_IOMUXC_NAND_DATA 839 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
855 MX8MM_IOMUXC_NAND_RE_B 840 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
856 MX8MM_IOMUXC_NAND_CE2_ 841 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
857 MX8MM_IOMUXC_NAND_CE3_ 842 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
858 MX8MM_IOMUXC_NAND_CLE_ 843 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
859 MX8MM_IOMUXC_NAND_CE1_ 844 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
860 MX8MM_IOMUXC_NAND_READ 845 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
861 >; 846 >;
862 }; 847 };
863 848
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g 849 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
865 fsl,pins = < 850 fsl,pins = <
866 MX8MM_IOMUXC_NAND_WE_B 851 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
867 MX8MM_IOMUXC_NAND_WP_B 852 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
868 MX8MM_IOMUXC_NAND_DATA 853 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
869 MX8MM_IOMUXC_NAND_DATA 854 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
870 MX8MM_IOMUXC_NAND_DATA 855 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
871 MX8MM_IOMUXC_NAND_DATA 856 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
872 MX8MM_IOMUXC_NAND_RE_B 857 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
873 MX8MM_IOMUXC_NAND_CE2_ 858 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
874 MX8MM_IOMUXC_NAND_CE3_ 859 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
875 MX8MM_IOMUXC_NAND_CLE_ 860 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
876 MX8MM_IOMUXC_NAND_CE1_ 861 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
877 MX8MM_IOMUXC_NAND_READ 862 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
878 >; 863 >;
879 }; 864 };
880 865
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g 866 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
882 fsl,pins = < 867 fsl,pins = <
883 MX8MM_IOMUXC_NAND_WE_B 868 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
884 MX8MM_IOMUXC_NAND_WP_B 869 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
885 MX8MM_IOMUXC_NAND_DATA 870 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
886 MX8MM_IOMUXC_NAND_DATA 871 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
887 MX8MM_IOMUXC_NAND_DATA 872 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
888 MX8MM_IOMUXC_NAND_DATA 873 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
889 MX8MM_IOMUXC_NAND_RE_B 874 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
890 MX8MM_IOMUXC_NAND_CE2_ 875 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
891 MX8MM_IOMUXC_NAND_CE3_ 876 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
892 MX8MM_IOMUXC_NAND_CLE_ 877 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
893 MX8MM_IOMUXC_NAND_CE1_ 878 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
894 MX8MM_IOMUXC_NAND_READ 879 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
895 >; 880 >;
896 }; 881 };
897 882
898 pinctrl_watchdog_gpio: watchdog-gpio-g 883 pinctrl_watchdog_gpio: watchdog-gpio-grp {
899 fsl,pins = < 884 fsl,pins = <
900 /* WDOG_B# */ 885 /* WDOG_B# */
901 MX8MM_IOMUXC_GPIO1_IO0 886 MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
902 /* WDOG_EN -- ungate W 887 /* WDOG_EN -- ungate WDT RESET# signal propagation */
903 MX8MM_IOMUXC_SD1_DATA7 888 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
904 /* WDOG_KICK# / WDI */ 889 /* WDOG_KICK# / WDI */
905 MX8MM_IOMUXC_GPIO1_IO0 890 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
906 >; 891 >;
907 }; 892 };
908 }; 893 };
909 894
910 &pcie_phy { 895 &pcie_phy {
911 fsl,clkreq-unsupported; /* CLKREQ_B is 896 fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
912 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 897 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
913 fsl,tx-deemph-gen1 = <0x2d>; 898 fsl,tx-deemph-gen1 = <0x2d>;
914 fsl,tx-deemph-gen2 = <0xf>; 899 fsl,tx-deemph-gen2 = <0xf>;
915 clocks = <&pcieclk 0>; 900 clocks = <&pcieclk 0>;
916 status = "okay"; 901 status = "okay";
917 }; 902 };
918 903
919 &pcie0 { 904 &pcie0 {
920 pinctrl-names = "default"; 905 pinctrl-names = "default";
921 pinctrl-0 = <&pinctrl_pcie0>; 906 pinctrl-0 = <&pinctrl_pcie0>;
922 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW 907 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
923 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 908 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
924 <&clk IMX8MM_CLK_PCIE1_AUX>; 909 <&clk IMX8MM_CLK_PCIE1_AUX>;
925 assigned-clocks = <&clk IMX8MM_CLK_PCI 910 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
926 <&clk IMX8MM_CLK_PCI 911 <&clk IMX8MM_CLK_PCIE1_CTRL>;
927 assigned-clock-rates = <10000000>, <25 912 assigned-clock-rates = <10000000>, <250000000>;
928 assigned-clock-parents = <&clk IMX8MM_ 913 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
929 <&clk IMX8MM_ 914 <&clk IMX8MM_SYS_PLL2_250M>;
930 status = "okay"; 915 status = "okay";
931 }; 916 };
932 917
933 &pwm1 { 918 &pwm1 {
934 pinctrl-names = "default"; 919 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_panel_pwm>; 920 pinctrl-0 = <&pinctrl_panel_pwm>;
936 /* Disabled by default, unless display 921 /* Disabled by default, unless display board plugged in. */
937 status = "disabled"; 922 status = "disabled";
938 }; 923 };
939 924
940 &sai5 { 925 &sai5 {
941 pinctrl-names = "default"; 926 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_sai5>; 927 pinctrl-0 = <&pinctrl_sai5>;
943 fsl,sai-mclk-direction-output; 928 fsl,sai-mclk-direction-output;
944 /* Input into codec PLL */ 929 /* Input into codec PLL */
945 assigned-clocks = <&clk IMX8MM_CLK_SAI 930 assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
946 assigned-clock-parents = <&clk IMX8MM_ 931 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
947 assigned-clock-rates = <22579200>; 932 assigned-clock-rates = <22579200>;
948 /* Disabled by default, unless display 933 /* Disabled by default, unless display board plugged in. */
949 status = "disabled"; 934 status = "disabled";
950 }; 935 };
951 936
952 &snvs_rtc { 937 &snvs_rtc {
953 clocks = <&pmic>; 938 clocks = <&pmic>;
954 }; 939 };
955 940
956 &uart1 { 941 &uart1 {
957 pinctrl-names = "default"; 942 pinctrl-names = "default";
958 pinctrl-0 = <&pinctrl_uart1>; 943 pinctrl-0 = <&pinctrl_uart1>;
959 uart-has-rtscts; 944 uart-has-rtscts;
960 status = "disabled"; 945 status = "disabled";
961 }; 946 };
962 947
963 &uart2 { 948 &uart2 {
964 pinctrl-names = "default"; 949 pinctrl-names = "default";
965 pinctrl-0 = <&pinctrl_uart2>; 950 pinctrl-0 = <&pinctrl_uart2>;
966 status = "disabled"; 951 status = "disabled";
967 }; 952 };
968 953
969 &uart3 { /* A53 Debug */ 954 &uart3 { /* A53 Debug */
970 pinctrl-names = "default"; 955 pinctrl-names = "default";
971 pinctrl-0 = <&pinctrl_uart3>; 956 pinctrl-0 = <&pinctrl_uart3>;
972 status = "okay"; 957 status = "okay";
973 }; 958 };
974 959
975 &uart4 { /* M4 Debug */ 960 &uart4 { /* M4 Debug */
976 pinctrl-names = "default"; 961 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_uart4>; 962 pinctrl-0 = <&pinctrl_uart4>;
978 /* UART4 is reserved for CM and RDC bl 963 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
979 status = "disabled"; 964 status = "disabled";
980 }; 965 };
981 966
982 &usbotg1 { 967 &usbotg1 {
983 pinctrl-names = "default"; 968 pinctrl-names = "default";
984 pinctrl-0 = <&pinctrl_usb_otg1>; 969 pinctrl-0 = <&pinctrl_usb_otg1>;
985 dr_mode = "otg"; 970 dr_mode = "otg";
986 status = "okay"; 971 status = "okay";
987 }; 972 };
988 973
989 &usbotg2 { 974 &usbotg2 {
990 disable-over-current; 975 disable-over-current;
991 dr_mode = "host"; 976 dr_mode = "host";
992 status = "okay"; 977 status = "okay";
993 }; 978 };
994 979
995 &usdhc2 { /* MicroSD */ 980 &usdhc2 { /* MicroSD */
996 assigned-clocks = <&clk IMX8MM_CLK_USD 981 assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
997 pinctrl-names = "default", "state_100m 982 pinctrl-names = "default", "state_100mhz", "state_200mhz";
998 pinctrl-0 = <&pinctrl_usdhc2>; 983 pinctrl-0 = <&pinctrl_usdhc2>;
999 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 984 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
1000 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 985 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
1001 bus-width = <4>; 986 bus-width = <4>;
1002 vmmc-supply = <®_usdhc2_vcc>; 987 vmmc-supply = <®_usdhc2_vcc>;
1003 status = "okay"; 988 status = "okay";
1004 }; 989 };
1005 990
1006 &usdhc3 { /* eMMC */ 991 &usdhc3 { /* eMMC */
1007 assigned-clocks = <&clk IMX8MM_CLK_US 992 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
1008 assigned-clock-rates = <400000000>; 993 assigned-clock-rates = <400000000>;
1009 pinctrl-names = "default", "state_100 994 pinctrl-names = "default", "state_100mhz", "state_200mhz";
1010 pinctrl-0 = <&pinctrl_usdhc3>; 995 pinctrl-0 = <&pinctrl_usdhc3>;
1011 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 996 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
1012 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 997 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
1013 bus-width = <8>; 998 bus-width = <8>;
1014 non-removable; 999 non-removable;
1015 vmmc-supply = <&buck4_reg>; 1000 vmmc-supply = <&buck4_reg>;
1016 vqmmc-supply = <&buck5_reg>; 1001 vqmmc-supply = <&buck5_reg>;
1017 status = "okay"; 1002 status = "okay";
1018 }; 1003 };
1019 1004
1020 &wdog1 { 1005 &wdog1 {
1021 status = "okay"; 1006 status = "okay";
1022 }; 1007 };
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