1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Marek Vasut <marex@denx.de> 3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/net/qca-ar803x.h> 8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h> 9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm.dtsi" 10 #include "imx8mm.dtsi"
11 11
12 / { 12 / {
13 model = "Data Modul i.MX8M Mini eDM SB 13 model = "Data Modul i.MX8M Mini eDM SBC";
14 compatible = "dmo,imx8mm-data-modul-ed 14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
15 15
16 aliases { 16 aliases {
17 rtc0 = &rtc; 17 rtc0 = &rtc;
18 rtc1 = &snvs_rtc; 18 rtc1 = &snvs_rtc;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = &uart3; 22 stdout-path = &uart3;
23 }; 23 };
24 24
25 memory@40000000 { 25 memory@40000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 /* There are 1/2/4 GiB options 27 /* There are 1/2/4 GiB options, adjusted by bootloader. */
28 reg = <0x0 0x40000000 0 0x4000 28 reg = <0x0 0x40000000 0 0x40000000>;
29 }; 29 };
30 30
31 backlight: backlight { 31 backlight: backlight {
32 compatible = "pwm-backlight"; 32 compatible = "pwm-backlight";
33 pinctrl-names = "default"; 33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_ba 34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
36 default-brightness-level = <7> 36 default-brightness-level = <7>;
37 enable-gpios = <&gpio3 0 GPIO_ 37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>; 38 pwms = <&pwm1 0 5000000 0>;
39 /* Disabled by default, unless 39 /* Disabled by default, unless display board plugged in. */
40 status = "disabled"; 40 status = "disabled";
41 }; 41 };
42 42
43 clk_xtal25: clk-xtal25 { 43 clk_xtal25: clk-xtal25 {
44 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <25000000>; 46 clock-frequency = <25000000>;
47 }; 47 };
48 48
49 clk_xtal32k: clk-xtal32k { 49 clk_xtal32k: clk-xtal32k {
50 compatible = "fixed-clock"; 50 compatible = "fixed-clock";
51 #clock-cells = <0>; 51 #clock-cells = <0>;
52 clock-frequency = <32768>; 52 clock-frequency = <32768>;
53 }; 53 };
54 54
55 panel: panel { 55 panel: panel {
56 backlight = <&backlight>; 56 backlight = <&backlight>;
57 power-supply = <®_panel_vcc 57 power-supply = <®_panel_vcc>;
58 /* Disabled by default, unless 58 /* Disabled by default, unless display board plugged in. */
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 reg_panel_vcc: regulator-panel-vcc { 62 reg_panel_vcc: regulator-panel-vcc {
63 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_panel_vc 65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
66 regulator-name = "PANEL_VCC"; 66 regulator-name = "PANEL_VCC";
67 regulator-min-microvolt = <500 67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <500 68 regulator-max-microvolt = <5000000>;
69 gpio = <&gpio3 6 0>; 69 gpio = <&gpio3 6 0>;
70 enable-active-high; 70 enable-active-high;
71 /* Disabled by default, unless 71 /* Disabled by default, unless display board plugged in. */
72 status = "disabled"; 72 status = "disabled";
73 }; 73 };
74 74
75 reg_usdhc2_vcc: regulator-usdhc2-vcc { 75 reg_usdhc2_vcc: regulator-usdhc2-vcc {
76 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
77 pinctrl-names = "default"; 77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usdhc2_v 78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
79 regulator-name = "V_3V3_SD"; 79 regulator-name = "V_3V3_SD";
80 regulator-min-microvolt = <330 80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <330 81 regulator-max-microvolt = <3300000>;
82 gpio = <&gpio2 19 0>; 82 gpio = <&gpio2 19 0>;
83 enable-active-high; 83 enable-active-high;
84 }; 84 };
85 85
86 watchdog { 86 watchdog {
87 /* TPS3813 */ 87 /* TPS3813 */
88 pinctrl-names = "default"; 88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_watchdog 89 pinctrl-0 = <&pinctrl_watchdog_gpio>;
90 compatible = "linux,wdt-gpio"; 90 compatible = "linux,wdt-gpio";
91 always-running; 91 always-running;
92 gpios = <&gpio1 8 GPIO_ACTIVE_ 92 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
93 hw_algo = "level"; 93 hw_algo = "level";
94 /* Reset triggers in 2..3 seco 94 /* Reset triggers in 2..3 seconds */
95 hw_margin_ms = <1500>; 95 hw_margin_ms = <1500>;
96 /* Disabled by default */ 96 /* Disabled by default */
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99 }; 99 };
100 100
101 &A53_0 { 101 &A53_0 {
102 cpu-supply = <&buck2_reg>; 102 cpu-supply = <&buck2_reg>;
103 }; 103 };
104 104
105 &A53_1 { 105 &A53_1 {
106 cpu-supply = <&buck2_reg>; 106 cpu-supply = <&buck2_reg>;
107 }; 107 };
108 108
109 &A53_2 { 109 &A53_2 {
110 cpu-supply = <&buck2_reg>; 110 cpu-supply = <&buck2_reg>;
111 }; 111 };
112 112
113 &A53_3 { 113 &A53_3 {
114 cpu-supply = <&buck2_reg>; 114 cpu-supply = <&buck2_reg>;
115 }; 115 };
116 116
117 &ddrc { 117 &ddrc {
118 operating-points-v2 = <&ddrc_opp_table 118 operating-points-v2 = <&ddrc_opp_table>;
119 119
120 ddrc_opp_table: opp-table { 120 ddrc_opp_table: opp-table {
121 compatible = "operating-points 121 compatible = "operating-points-v2";
122 122
123 opp-25000000 { 123 opp-25000000 {
124 opp-hz = /bits/ 64 <25 124 opp-hz = /bits/ 64 <25000000>;
125 }; 125 };
126 126
127 opp-100000000 { 127 opp-100000000 {
128 opp-hz = /bits/ 64 <10 128 opp-hz = /bits/ 64 <100000000>;
129 }; 129 };
130 130
131 opp-750000000 { 131 opp-750000000 {
132 opp-hz = /bits/ 64 <75 132 opp-hz = /bits/ 64 <750000000>;
133 }; 133 };
134 }; 134 };
135 }; 135 };
136 136
137 &ecspi1 { 137 &ecspi1 {
138 pinctrl-names = "default"; 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_ecspi1>; 139 pinctrl-0 = <&pinctrl_ecspi1>;
140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 140 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
141 status = "okay"; 141 status = "okay";
142 142
143 flash@0 { /* W25Q128FVSI */ 143 flash@0 { /* W25Q128FVSI */
144 compatible = "jedec,spi-nor"; 144 compatible = "jedec,spi-nor";
145 m25p,fast-read; 145 m25p,fast-read;
146 spi-max-frequency = <50000000> 146 spi-max-frequency = <50000000>;
147 reg = <0>; 147 reg = <0>;
148 }; 148 };
149 }; 149 };
150 150
151 &ecspi2 { /* Feature connector SPI */ 151 &ecspi2 { /* Feature connector SPI */
152 pinctrl-names = "default"; 152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_ecspi2>; 153 pinctrl-0 = <&pinctrl_ecspi2>;
154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 154 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
155 /* Disabled by default, unless feature 155 /* Disabled by default, unless feature board plugged in. */
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 158
159 &ecspi3 { /* Display connector SPI */ 159 &ecspi3 { /* Display connector SPI */
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_ecspi3>; 161 pinctrl-0 = <&pinctrl_ecspi3>;
162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW> 162 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
163 /* Disabled by default, unless display 163 /* Disabled by default, unless display board plugged in. */
164 status = "disabled"; 164 status = "disabled";
165 }; 165 };
166 166
167 &fec1 { 167 &fec1 {
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_fec1>; 169 pinctrl-0 = <&pinctrl_fec1>;
170 phy-mode = "rgmii-id"; 170 phy-mode = "rgmii-id";
171 phy-handle = <&fec1_phy_bcm>; 171 phy-handle = <&fec1_phy_bcm>;
172 phy-supply = <&buck4_reg>; 172 phy-supply = <&buck4_reg>;
173 fsl,magic-packet; 173 fsl,magic-packet;
174 status = "okay"; 174 status = "okay";
175 175
176 mdio { 176 mdio {
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <0>; 178 #size-cells = <0>;
179 179
180 /* Atheros AR8031 PHY */ 180 /* Atheros AR8031 PHY */
181 fec1_phy_ath: ethernet-phy@0 { 181 fec1_phy_ath: ethernet-phy@0 {
182 compatible = "ethernet 182 compatible = "ethernet-phy-ieee802.3-c22";
183 reg = <0>; 183 reg = <0>;
184 /* 184 /*
185 * Dedicated ENET_WOL# 185 * Dedicated ENET_WOL# signal is unused, the PHY
186 * can wake the SoC up 186 * can wake the SoC up via INT signal as well.
187 */ 187 */
188 interrupts-extended = 188 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
189 reset-gpios = <&gpio1 189 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
190 reset-assert-us = <100 190 reset-assert-us = <10000>;
191 reset-deassert-us = <1 191 reset-deassert-us = <10000>;
192 qca,keep-pll-enabled; 192 qca,keep-pll-enabled;
193 vddio-supply = <&vddio 193 vddio-supply = <&vddio>;
194 status = "disabled"; 194 status = "disabled";
195 195
196 vddio: vddio-regulator 196 vddio: vddio-regulator {
197 regulator-name 197 regulator-name = "VDDIO";
198 regulator-min- 198 regulator-min-microvolt = <1800000>;
199 regulator-max- 199 regulator-max-microvolt = <1800000>;
200 }; 200 };
201 201
202 vddh: vddh-regulator { 202 vddh: vddh-regulator {
203 regulator-name 203 regulator-name = "VDDH";
204 }; 204 };
205 }; 205 };
206 206
207 /* Broadcom BCM54213PE PHY */ 207 /* Broadcom BCM54213PE PHY */
208 fec1_phy_bcm: ethernet-phy@1 { 208 fec1_phy_bcm: ethernet-phy@1 {
209 compatible = "ethernet 209 compatible = "ethernet-phy-ieee802.3-c22";
210 reg = <1>; 210 reg = <1>;
211 /* 211 /*
212 * Dedicated ENET_INT# 212 * Dedicated ENET_INT# and ENET_WOL# signals are
213 * unused, the PHY doe 213 * unused, the PHY does not provide cable detect
214 * interrupt. 214 * interrupt.
215 */ 215 */
216 reset-gpios = <&gpio1 216 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
217 reset-assert-us = <100 217 reset-assert-us = <10000>;
218 reset-deassert-us = <1 218 reset-deassert-us = <10000>;
219 }; 219 };
220 }; 220 };
221 }; 221 };
222 222
223 &gpio1 { 223 &gpio1 {
224 gpio-line-names = 224 gpio-line-names =
225 "", "ENET_RST#", "WDOG_B#", "P 225 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
226 "", "M2-B_PCIE_RST#", "M2-B_PC 226 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
227 "WDOG_KICK#", "M2-B_PCIE_CLKRE 227 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
228 "USB1_OTG_ID_3V3", "ENET_WOL#" 228 "USB1_OTG_ID_3V3", "ENET_WOL#",
229 "", "", "", "ENET_INT#", 229 "", "", "", "ENET_INT#",
230 "", "", "", "", "", "", "", "" 230 "", "", "", "", "", "", "", "",
231 "", "", "", "", "", "", "", "" 231 "", "", "", "", "", "", "", "";
232 }; 232 };
233 233
234 &gpio2 { 234 &gpio2 {
235 gpio-line-names = 235 gpio-line-names =
236 "MEMCFG2", "MEMCFG1", "DSI_RES 236 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
237 "M2-B_FULL_CARD_PWROFF_1V8#", 237 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
238 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8# 238 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
239 "MEMCFG0", "WDOG_EN", 239 "MEMCFG0", "WDOG_EN",
240 "M2-B_W_DISABLE1_WWAN_1V8#", " 240 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
241 "", "", "", "", 241 "", "", "", "",
242 "", "", "", "SD2_RESET#", "", 242 "", "", "", "SD2_RESET#", "", "", "", "",
243 "", "", "", "", "", "", "", "" 243 "", "", "", "", "", "", "", "";
244 }; 244 };
245 245
246 &gpio3 { 246 &gpio3 {
247 gpio-line-names = 247 gpio-line-names =
248 "BL_ENABLE_1V8", "PG_V_IN_VAR# 248 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
249 "", "", "TFT_ENABLE_1V8", "GRA 249 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
250 "CSI_PD_1V8", "CSI_RESET_1V8#" 250 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
251 "", "", "", "", 251 "", "", "", "",
252 "", "", "", "M2-B_WAKE_WWAN_1V 252 "", "", "", "M2-B_WAKE_WWAN_1V8#",
253 "M2-B_RESET_1V8#", "", "", "", 253 "M2-B_RESET_1V8#", "", "", "",
254 "", "", "", "", "", "", "", "" 254 "", "", "", "", "", "", "", "";
255 }; 255 };
256 256
257 &gpio4 { 257 &gpio4 {
258 gpio-line-names = 258 gpio-line-names =
259 "NC0", "NC1", "BOOTCFG0", "BOO 259 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
260 "BOOTCFG2", "BOOTCFG3", "BOOTC 260 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
261 "BOOTCFG6", "BOOTCFG7", "NC10" 261 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
262 "BOOTCFG8", "BOOTCFG9", "BOOTC 262 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
263 "BOOTCFG12", "BOOTCFG13", "BOO 263 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
264 "NC20", "", "", "", 264 "NC20", "", "", "",
265 "", "CAN_INT#", "CAN_RST#", "G 265 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
266 "DIS_USB_DN2", "", "", ""; 266 "DIS_USB_DN2", "", "", "";
267 }; 267 };
268 268
269 &gpio5 { 269 &gpio5 {
270 gpio-line-names = 270 gpio-line-names =
271 "", "DIS_USB_DN1", "USBHUB_RES 271 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
272 "GPIO5_IO04", "", "", "", 272 "GPIO5_IO04", "", "", "",
273 "", "SPI1_CS#", "", "", 273 "", "SPI1_CS#", "", "",
274 "", "SPI2_CS#", "I2C1_SCL_3V3" 274 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
275 "I2C2_SCL_3V3", "I2C2_SDA_3V3" 275 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
276 "I2C4_SCL_3V3", "I2C4_SDA_3V3" 276 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
277 "", "SPI3_CS#", "", "", "", "" 277 "", "SPI3_CS#", "", "", "", "", "", "";
278 }; 278 };
279 279
280 &i2c1 { 280 &i2c1 {
281 /* IMX8MM ERRATA e7805 -- I2C is limit 281 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
282 clock-frequency = <100000>; 282 clock-frequency = <100000>;
283 pinctrl-names = "default", "gpio"; 283 pinctrl-names = "default", "gpio";
284 pinctrl-0 = <&pinctrl_i2c1>; 284 pinctrl-0 = <&pinctrl_i2c1>;
285 pinctrl-1 = <&pinctrl_i2c1_gpio>; 285 pinctrl-1 = <&pinctrl_i2c1_gpio>;
286 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 286 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
287 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 287 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
288 status = "okay"; 288 status = "okay";
289 289
290 pmic: pmic@4b { 290 pmic: pmic@4b {
291 compatible = "rohm,bd71847"; 291 compatible = "rohm,bd71847";
292 reg = <0x4b>; 292 reg = <0x4b>;
293 #clock-cells = <0>; 293 #clock-cells = <0>;
294 clocks = <&clk_xtal32k>; 294 clocks = <&clk_xtal32k>;
295 clock-output-names = "clk-32k- 295 clock-output-names = "clk-32k-out";
296 pinctrl-names = "default"; 296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_pmic>; 297 pinctrl-0 = <&pinctrl_pmic>;
298 interrupt-parent = <&gpio1>; 298 interrupt-parent = <&gpio1>;
299 interrupts = <3 IRQ_TYPE_EDGE_ 299 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
300 rohm,reset-snvs-powered; 300 rohm,reset-snvs-powered;
301 301
302 /* 302 /*
303 * i.MX 8M Mini Data Sheet for 303 * i.MX 8M Mini Data Sheet for Consumer Products
304 * 3.1.3 Operating ranges 304 * 3.1.3 Operating ranges
305 * MIMX8MM4DVTLZAA 305 * MIMX8MM4DVTLZAA
306 */ 306 */
307 regulators { 307 regulators {
308 /* VDD_SOC */ 308 /* VDD_SOC */
309 buck1_reg: BUCK1 { 309 buck1_reg: BUCK1 {
310 regulator-name 310 regulator-name = "buck1";
311 regulator-min- 311 regulator-min-microvolt = <850000>;
312 regulator-max- 312 regulator-max-microvolt = <850000>;
313 regulator-boot 313 regulator-boot-on;
314 regulator-alwa 314 regulator-always-on;
315 regulator-ramp 315 regulator-ramp-delay = <1250>;
316 }; 316 };
317 317
318 /* VDD_ARM */ 318 /* VDD_ARM */
319 buck2_reg: BUCK2 { 319 buck2_reg: BUCK2 {
320 regulator-name 320 regulator-name = "buck2";
321 regulator-min- 321 regulator-min-microvolt = <850000>;
322 regulator-max- 322 regulator-max-microvolt = <1050000>;
323 regulator-boot 323 regulator-boot-on;
324 regulator-alwa 324 regulator-always-on;
325 regulator-ramp 325 regulator-ramp-delay = <1250>;
326 rohm,dvs-run-v 326 rohm,dvs-run-voltage = <1000000>;
327 rohm,dvs-idle- 327 rohm,dvs-idle-voltage = <950000>;
328 }; 328 };
329 329
330 /* VDD_DRAM, BUCK5 */ 330 /* VDD_DRAM, BUCK5 */
331 buck3_reg: BUCK3 { 331 buck3_reg: BUCK3 {
332 regulator-name 332 regulator-name = "buck3";
333 /* 1.5 GHz DDR 333 /* 1.5 GHz DDR bus clock */
334 regulator-min- 334 regulator-min-microvolt = <900000>;
335 regulator-max- 335 regulator-max-microvolt = <1000000>;
336 regulator-boot 336 regulator-boot-on;
337 regulator-alwa 337 regulator-always-on;
338 }; 338 };
339 339
340 /* 3V3_VDD, BUCK6 */ 340 /* 3V3_VDD, BUCK6 */
341 buck4_reg: BUCK4 { 341 buck4_reg: BUCK4 {
342 regulator-name 342 regulator-name = "buck4";
343 regulator-min- 343 regulator-min-microvolt = <3300000>;
344 regulator-max- 344 regulator-max-microvolt = <3300000>;
345 regulator-boot 345 regulator-boot-on;
346 regulator-alwa 346 regulator-always-on;
347 }; 347 };
348 348
349 /* 1V8_VDD, BUCK7 */ 349 /* 1V8_VDD, BUCK7 */
350 buck5_reg: BUCK5 { 350 buck5_reg: BUCK5 {
351 regulator-name 351 regulator-name = "buck5";
352 regulator-min- 352 regulator-min-microvolt = <1800000>;
353 regulator-max- 353 regulator-max-microvolt = <1800000>;
354 regulator-boot 354 regulator-boot-on;
355 regulator-alwa 355 regulator-always-on;
356 }; 356 };
357 357
358 /* 1V1_NVCC_DRAM, BUCK 358 /* 1V1_NVCC_DRAM, BUCK8 */
359 buck6_reg: BUCK6 { 359 buck6_reg: BUCK6 {
360 regulator-name 360 regulator-name = "buck6";
361 regulator-min- 361 regulator-min-microvolt = <1100000>;
362 regulator-max- 362 regulator-max-microvolt = <1100000>;
363 regulator-boot 363 regulator-boot-on;
364 regulator-alwa 364 regulator-always-on;
365 }; 365 };
366 366
367 /* 1V8_NVCC_SNVS */ 367 /* 1V8_NVCC_SNVS */
368 ldo1_reg: LDO1 { 368 ldo1_reg: LDO1 {
369 regulator-name 369 regulator-name = "ldo1";
370 regulator-min- 370 regulator-min-microvolt = <1800000>;
371 regulator-max- 371 regulator-max-microvolt = <1800000>;
372 regulator-boot 372 regulator-boot-on;
373 regulator-alwa 373 regulator-always-on;
374 }; 374 };
375 375
376 /* 0V8_VDD_SNVS */ 376 /* 0V8_VDD_SNVS */
377 ldo2_reg: LDO2 { 377 ldo2_reg: LDO2 {
378 regulator-name 378 regulator-name = "ldo2";
379 regulator-min- 379 regulator-min-microvolt = <800000>;
380 regulator-max- 380 regulator-max-microvolt = <800000>;
381 regulator-boot 381 regulator-boot-on;
382 regulator-alwa 382 regulator-always-on;
383 }; 383 };
384 384
385 /* 1V8_VDDA */ 385 /* 1V8_VDDA */
386 ldo3_reg: LDO3 { 386 ldo3_reg: LDO3 {
387 regulator-name 387 regulator-name = "ldo3";
388 regulator-min- 388 regulator-min-microvolt = <1800000>;
389 regulator-max- 389 regulator-max-microvolt = <1800000>;
390 regulator-boot 390 regulator-boot-on;
391 regulator-alwa 391 regulator-always-on;
392 }; 392 };
393 393
394 /* 0V9_VDD_PHY */ 394 /* 0V9_VDD_PHY */
395 ldo4_reg: LDO4 { 395 ldo4_reg: LDO4 {
396 regulator-name 396 regulator-name = "ldo4";
397 regulator-min- 397 regulator-min-microvolt = <900000>;
398 regulator-max- 398 regulator-max-microvolt = <900000>;
399 regulator-boot 399 regulator-boot-on;
400 regulator-alwa 400 regulator-always-on;
401 }; 401 };
402 402
403 /* 1V2_VDD_PHY */ 403 /* 1V2_VDD_PHY */
404 ldo6_reg: LDO6 { 404 ldo6_reg: LDO6 {
405 regulator-name 405 regulator-name = "ldo6";
406 regulator-min- 406 regulator-min-microvolt = <1200000>;
407 regulator-max- 407 regulator-max-microvolt = <1200000>;
408 regulator-boot 408 regulator-boot-on;
409 regulator-alwa 409 regulator-always-on;
410 }; 410 };
411 }; 411 };
412 }; 412 };
413 }; 413 };
414 414
415 &i2c2 { 415 &i2c2 {
416 /* IMX8MM ERRATA e7805 -- I2C is limit 416 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
417 clock-frequency = <100000>; 417 clock-frequency = <100000>;
418 pinctrl-names = "default", "gpio"; 418 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c2>; 419 pinctrl-0 = <&pinctrl_i2c2>;
420 pinctrl-1 = <&pinctrl_i2c2_gpio>; 420 pinctrl-1 = <&pinctrl_i2c2_gpio>;
421 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 421 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
422 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 422 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
423 status = "okay"; 423 status = "okay";
424 424
425 usb-hub@2c { 425 usb-hub@2c {
426 pinctrl-names = "default"; 426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_usb_hub> 427 pinctrl-0 = <&pinctrl_usb_hub>;
428 compatible = "microchip,usb251 428 compatible = "microchip,usb2514bi";
429 reg = <0x2c>; 429 reg = <0x2c>;
430 individual-port-switching; 430 individual-port-switching;
431 reset-gpios = <&gpio5 2 GPIO_A 431 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
432 self-powered; 432 self-powered;
433 }; 433 };
434 434
435 eeprom: eeprom@50 { 435 eeprom: eeprom@50 {
436 compatible = "atmel,24c32"; 436 compatible = "atmel,24c32";
437 reg = <0x50>; 437 reg = <0x50>;
438 pagesize = <32>; 438 pagesize = <32>;
439 }; 439 };
440 440
441 rtc: rtc@68 { 441 rtc: rtc@68 {
442 pinctrl-names = "default"; 442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_rtc>; 443 pinctrl-0 = <&pinctrl_rtc>;
444 compatible = "st,m41t62"; 444 compatible = "st,m41t62";
445 reg = <0x68>; 445 reg = <0x68>;
446 interrupts-extended = <&gpio1 446 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
447 }; 447 };
448 448
449 pcieclk: clk@6a { 449 pcieclk: clk@6a {
450 compatible = "renesas,9fgv0241 450 compatible = "renesas,9fgv0241";
451 reg = <0x6a>; 451 reg = <0x6a>;
452 clocks = <&clk_xtal25>; 452 clocks = <&clk_xtal25>;
453 #clock-cells = <1>; 453 #clock-cells = <1>;
454 }; 454 };
455 }; 455 };
456 456
457 &i2c3 { /* Display connector I2C */ 457 &i2c3 { /* Display connector I2C */
458 /* IMX8MM ERRATA e7805 -- I2C is limit 458 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
459 clock-frequency = <320000>; 459 clock-frequency = <320000>;
460 pinctrl-names = "default", "gpio"; 460 pinctrl-names = "default", "gpio";
461 pinctrl-0 = <&pinctrl_i2c3>; 461 pinctrl-0 = <&pinctrl_i2c3>;
462 pinctrl-1 = <&pinctrl_i2c3_gpio>; 462 pinctrl-1 = <&pinctrl_i2c3_gpio>;
463 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 463 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
464 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 464 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
465 status = "okay"; 465 status = "okay";
466 }; 466 };
467 467
468 &i2c4 { /* Feature connector I2C */ 468 &i2c4 { /* Feature connector I2C */
469 /* IMX8MM ERRATA e7805 -- I2C is limit 469 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
470 clock-frequency = <320000>; 470 clock-frequency = <320000>;
471 pinctrl-names = "default", "gpio"; 471 pinctrl-names = "default", "gpio";
472 pinctrl-0 = <&pinctrl_i2c4>; 472 pinctrl-0 = <&pinctrl_i2c4>;
473 pinctrl-1 = <&pinctrl_i2c4_gpio>; 473 pinctrl-1 = <&pinctrl_i2c4_gpio>;
474 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 474 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
475 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 475 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
476 status = "okay"; 476 status = "okay";
477 }; 477 };
478 478
479 &iomuxc { 479 &iomuxc {
480 pinctrl-names = "default"; 480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_hog_feature>, <& 481 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
482 <&pinctrl_hog_panel>, <&pi 482 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
483 <&pinctrl_panel_expansion> 483 <&pinctrl_panel_expansion>;
484 484
485 pinctrl_ecspi1: ecspi1-grp { 485 pinctrl_ecspi1: ecspi1-grp {
486 fsl,pins = < 486 fsl,pins = <
487 MX8MM_IOMUXC_ECSPI1_SC 487 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
488 MX8MM_IOMUXC_ECSPI1_MO 488 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
489 MX8MM_IOMUXC_ECSPI1_MI 489 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
490 MX8MM_IOMUXC_ECSPI1_SS 490 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
491 >; 491 >;
492 }; 492 };
493 493
494 pinctrl_ecspi2: ecspi2-grp { 494 pinctrl_ecspi2: ecspi2-grp {
495 fsl,pins = < 495 fsl,pins = <
496 MX8MM_IOMUXC_ECSPI2_SC 496 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
497 MX8MM_IOMUXC_ECSPI2_MO 497 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
498 MX8MM_IOMUXC_ECSPI2_MI 498 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
499 MX8MM_IOMUXC_ECSPI2_SS 499 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
500 >; 500 >;
501 }; 501 };
502 502
503 pinctrl_ecspi3: ecspi3-grp { 503 pinctrl_ecspi3: ecspi3-grp {
504 fsl,pins = < 504 fsl,pins = <
505 MX8MM_IOMUXC_UART1_RXD 505 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
506 MX8MM_IOMUXC_UART1_TXD 506 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
507 MX8MM_IOMUXC_UART2_RXD 507 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
508 MX8MM_IOMUXC_UART2_TXD 508 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
509 >; 509 >;
510 }; 510 };
511 511
512 pinctrl_fec1: fec1-grp { 512 pinctrl_fec1: fec1-grp {
513 fsl,pins = < 513 fsl,pins = <
514 MX8MM_IOMUXC_ENET_MDC_ 514 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MM_IOMUXC_ENET_MDIO 515 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
516 MX8MM_IOMUXC_ENET_RD0_ 516 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
517 MX8MM_IOMUXC_ENET_RD1_ 517 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
518 MX8MM_IOMUXC_ENET_RD2_ 518 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
519 MX8MM_IOMUXC_ENET_RD3_ 519 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
520 MX8MM_IOMUXC_ENET_RXC_ 520 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
521 MX8MM_IOMUXC_ENET_RX_C 521 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
522 MX8MM_IOMUXC_ENET_TD0_ 522 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
523 MX8MM_IOMUXC_ENET_TD1_ 523 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
524 MX8MM_IOMUXC_ENET_TD2_ 524 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
525 MX8MM_IOMUXC_ENET_TD3_ 525 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
526 MX8MM_IOMUXC_ENET_TXC_ 526 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
527 MX8MM_IOMUXC_ENET_TX_C 527 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 /* ENET_RST# */ 528 /* ENET_RST# */
529 MX8MM_IOMUXC_GPIO1_IO0 529 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
530 /* ENET_WOL# */ 530 /* ENET_WOL# */
531 MX8MM_IOMUXC_GPIO1_IO1 531 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
532 /* ENET_INT# */ 532 /* ENET_INT# */
533 MX8MM_IOMUXC_GPIO1_IO1 533 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
534 >; 534 >;
535 }; 535 };
536 536
537 pinctrl_hog_feature: hog-feature-grp { 537 pinctrl_hog_feature: hog-feature-grp {
538 fsl,pins = < 538 fsl,pins = <
539 /* GPIO4_IO27 */ 539 /* GPIO4_IO27 */
540 MX8MM_IOMUXC_SAI2_MCLK 540 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
541 /* GPIO5_IO03 */ 541 /* GPIO5_IO03 */
542 MX8MM_IOMUXC_SPDIF_TX_ 542 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
543 /* GPIO5_IO04 */ 543 /* GPIO5_IO04 */
544 MX8MM_IOMUXC_SPDIF_RX_ 544 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
545 545
546 /* CAN_INT# */ 546 /* CAN_INT# */
547 MX8MM_IOMUXC_SAI2_TXC_ 547 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
548 /* CAN_RST# */ 548 /* CAN_RST# */
549 MX8MM_IOMUXC_SAI2_TXD0 549 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
550 >; 550 >;
551 }; 551 };
552 552
553 pinctrl_hog_panel: hog-panel-grp { 553 pinctrl_hog_panel: hog-panel-grp {
554 fsl,pins = < 554 fsl,pins = <
555 /* GRAPHICS_GPIO0_1V8 555 /* GRAPHICS_GPIO0_1V8 */
556 MX8MM_IOMUXC_NAND_DATA 556 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
557 >; 557 >;
558 }; 558 };
559 559
560 pinctrl_hog_misc: hog-misc-grp { 560 pinctrl_hog_misc: hog-misc-grp {
561 fsl,pins = < 561 fsl,pins = <
562 /* PG_V_IN_VAR# */ 562 /* PG_V_IN_VAR# */
563 MX8MM_IOMUXC_NAND_CE0_ 563 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
564 /* CSI_PD_1V8 */ 564 /* CSI_PD_1V8 */
565 MX8MM_IOMUXC_NAND_DATA 565 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
566 /* CSI_RESET_1V8# */ 566 /* CSI_RESET_1V8# */
567 MX8MM_IOMUXC_NAND_DATA 567 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
568 568
569 /* DIS_USB_DN1 */ 569 /* DIS_USB_DN1 */
570 MX8MM_IOMUXC_SAI3_TXD_ 570 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
571 /* DIS_USB_DN2 */ 571 /* DIS_USB_DN2 */
572 MX8MM_IOMUXC_SAI3_RXFS 572 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
573 573
574 /* EEPROM_WP_1V8# */ 574 /* EEPROM_WP_1V8# */
575 MX8MM_IOMUXC_SD1_DATA3 575 MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
576 /* PCIE_CLK_GEN_CLKPWR 576 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
577 MX8MM_IOMUXC_SD1_DATA4 577 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
578 /* GRAPHICS_PRSNT_1V8# 578 /* GRAPHICS_PRSNT_1V8# */
579 MX8MM_IOMUXC_SD1_DATA5 579 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
580 580
581 /* CLK_CCM_CLKO1_3V3 * 581 /* CLK_CCM_CLKO1_3V3 */
582 MX8MM_IOMUXC_GPIO1_IO1 582 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
583 >; 583 >;
584 }; 584 };
585 585
586 pinctrl_hog_sbc: hog-sbc-grp { 586 pinctrl_hog_sbc: hog-sbc-grp {
587 fsl,pins = < 587 fsl,pins = <
588 /* MEMCFG[0..2] straps 588 /* MEMCFG[0..2] straps */
589 MX8MM_IOMUXC_SD1_DATA6 589 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
590 MX8MM_IOMUXC_SD1_CMD_G 590 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
591 MX8MM_IOMUXC_SD1_CLK_G 591 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
592 592
593 /* BOOT_CFG[0..15] str 593 /* BOOT_CFG[0..15] straps */
594 MX8MM_IOMUXC_SAI1_RXD0 594 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
595 MX8MM_IOMUXC_SAI1_RXD1 595 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
596 MX8MM_IOMUXC_SAI1_RXD2 596 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
597 MX8MM_IOMUXC_SAI1_RXD3 597 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
598 MX8MM_IOMUXC_SAI1_RXD4 598 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
599 MX8MM_IOMUXC_SAI1_RXD5 599 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
600 MX8MM_IOMUXC_SAI1_RXD6 600 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
601 MX8MM_IOMUXC_SAI1_RXD7 601 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
602 MX8MM_IOMUXC_SAI1_TXD0 602 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
603 MX8MM_IOMUXC_SAI1_TXD1 603 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
604 MX8MM_IOMUXC_SAI1_TXD2 604 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
605 MX8MM_IOMUXC_SAI1_TXD3 605 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
606 MX8MM_IOMUXC_SAI1_TXD4 606 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
607 MX8MM_IOMUXC_SAI1_TXD5 607 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
608 MX8MM_IOMUXC_SAI1_TXD6 608 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
609 MX8MM_IOMUXC_SAI1_TXD7 609 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
610 610
611 /* Not connected pins 611 /* Not connected pins */
612 MX8MM_IOMUXC_SAI1_MCLK 612 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
613 MX8MM_IOMUXC_SAI1_TXFS 613 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
614 MX8MM_IOMUXC_SAI1_TXC_ 614 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
615 MX8MM_IOMUXC_SAI1_RXFS 615 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
616 MX8MM_IOMUXC_SAI1_RXC_ 616 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
617 >; 617 >;
618 }; 618 };
619 619
620 pinctrl_i2c1: i2c1-grp { 620 pinctrl_i2c1: i2c1-grp {
621 fsl,pins = < 621 fsl,pins = <
622 MX8MM_IOMUXC_I2C1_SCL_ 622 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
623 MX8MM_IOMUXC_I2C1_SDA_ 623 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
624 >; 624 >;
625 }; 625 };
626 626
627 pinctrl_i2c1_gpio: i2c1-gpio-grp { 627 pinctrl_i2c1_gpio: i2c1-gpio-grp {
628 fsl,pins = < 628 fsl,pins = <
629 MX8MM_IOMUXC_I2C1_SCL_ 629 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
630 MX8MM_IOMUXC_I2C1_SDA_ 630 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
631 >; 631 >;
632 }; 632 };
633 633
634 pinctrl_i2c2: i2c2-grp { 634 pinctrl_i2c2: i2c2-grp {
635 fsl,pins = < 635 fsl,pins = <
636 MX8MM_IOMUXC_I2C2_SCL_ 636 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
637 MX8MM_IOMUXC_I2C2_SDA_ 637 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
638 >; 638 >;
639 }; 639 };
640 640
641 pinctrl_i2c2_gpio: i2c2-gpio-grp { 641 pinctrl_i2c2_gpio: i2c2-gpio-grp {
642 fsl,pins = < 642 fsl,pins = <
643 MX8MM_IOMUXC_I2C2_SCL_ 643 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
644 MX8MM_IOMUXC_I2C2_SDA_ 644 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
645 >; 645 >;
646 }; 646 };
647 647
648 pinctrl_i2c3: i2c3-grp { 648 pinctrl_i2c3: i2c3-grp {
649 fsl,pins = < 649 fsl,pins = <
650 MX8MM_IOMUXC_I2C3_SCL_ 650 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
651 MX8MM_IOMUXC_I2C3_SDA_ 651 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
652 >; 652 >;
653 }; 653 };
654 654
655 pinctrl_i2c3_gpio: i2c3-gpio-grp { 655 pinctrl_i2c3_gpio: i2c3-gpio-grp {
656 fsl,pins = < 656 fsl,pins = <
657 MX8MM_IOMUXC_I2C3_SCL_ 657 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
658 MX8MM_IOMUXC_I2C3_SDA_ 658 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
659 >; 659 >;
660 }; 660 };
661 661
662 pinctrl_i2c4: i2c4-grp { 662 pinctrl_i2c4: i2c4-grp {
663 fsl,pins = < 663 fsl,pins = <
664 MX8MM_IOMUXC_I2C4_SCL_ 664 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
665 MX8MM_IOMUXC_I2C4_SDA_ 665 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
666 >; 666 >;
667 }; 667 };
668 668
669 pinctrl_i2c4_gpio: i2c4-gpio-grp { 669 pinctrl_i2c4_gpio: i2c4-gpio-grp {
670 fsl,pins = < 670 fsl,pins = <
671 MX8MM_IOMUXC_I2C4_SCL_ 671 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
672 MX8MM_IOMUXC_I2C4_SDA_ 672 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
673 >; 673 >;
674 }; 674 };
675 675
676 pinctrl_panel_backlight: panel-backlig 676 pinctrl_panel_backlight: panel-backlight-grp {
677 fsl,pins = < 677 fsl,pins = <
678 /* BL_ENABLE_1V8 */ 678 /* BL_ENABLE_1V8 */
679 MX8MM_IOMUXC_NAND_ALE_ 679 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
680 >; 680 >;
681 }; 681 };
682 682
683 pinctrl_panel_expansion: panel-expansi 683 pinctrl_panel_expansion: panel-expansion-grp {
684 fsl,pins = < 684 fsl,pins = <
685 /* DSI_RESET_1V8# */ 685 /* DSI_RESET_1V8# */
686 MX8MM_IOMUXC_SD1_DATA0 686 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
687 /* DSI_IRQ_1V8# */ 687 /* DSI_IRQ_1V8# */
688 MX8MM_IOMUXC_SD1_DATA1 688 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
689 >; 689 >;
690 }; 690 };
691 691
692 pinctrl_panel_vcc_reg: panel-vcc-grp { 692 pinctrl_panel_vcc_reg: panel-vcc-grp {
693 fsl,pins = < 693 fsl,pins = <
694 /* TFT_ENABLE_1V8 */ 694 /* TFT_ENABLE_1V8 */
695 MX8MM_IOMUXC_NAND_DATA 695 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
696 >; 696 >;
697 }; 697 };
698 698
699 pinctrl_panel_pwm: panel-pwm-grp { 699 pinctrl_panel_pwm: panel-pwm-grp {
700 fsl,pins = < 700 fsl,pins = <
701 /* BL_PWM_3V3 */ 701 /* BL_PWM_3V3 */
702 MX8MM_IOMUXC_SPDIF_EXT 702 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
703 >; 703 >;
704 }; 704 };
705 705
706 pinctrl_pcie0: pcie-grp { 706 pinctrl_pcie0: pcie-grp {
707 fsl,pins = < 707 fsl,pins = <
708 /* M2-B_RESET_1V8# */ 708 /* M2-B_RESET_1V8# */
709 MX8MM_IOMUXC_SAI5_RXC_ 709 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
710 /* M2-B_PCIE_RST# */ 710 /* M2-B_PCIE_RST# */
711 MX8MM_IOMUXC_GPIO1_IO0 711 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
712 /* M2-B_FULL_CARD_PWRO 712 /* M2-B_FULL_CARD_PWROFF_1V8# */
713 MX8MM_IOMUXC_SD1_DATA2 713 MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
714 /* M2-B_W_DISABLE1_WWA 714 /* M2-B_W_DISABLE1_WWAN_1V8# */
715 MX8MM_IOMUXC_SD1_RESET 715 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
716 /* M2-B_W_DISABLE2_GPS 716 /* M2-B_W_DISABLE2_GPS_1V8# */
717 MX8MM_IOMUXC_SD1_STROB 717 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
718 /* CLK_M2_32K768 */ 718 /* CLK_M2_32K768 */
719 MX8MM_IOMUXC_GPIO1_IO0 719 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
720 /* M2-B_WAKE_WWAN_1V8# 720 /* M2-B_WAKE_WWAN_1V8# */
721 MX8MM_IOMUXC_SAI5_RXFS 721 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
722 /* M2-B_PCIE_WAKE# */ 722 /* M2-B_PCIE_WAKE# */
723 MX8MM_IOMUXC_GPIO1_IO0 723 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
724 /* M2-B_PCIE_CLKREQ# * 724 /* M2-B_PCIE_CLKREQ# */
725 MX8MM_IOMUXC_GPIO1_IO0 725 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
726 >; 726 >;
727 }; 727 };
728 728
729 pinctrl_pmic: pmic-grp { 729 pinctrl_pmic: pmic-grp {
730 fsl,pins = < 730 fsl,pins = <
731 MX8MM_IOMUXC_GPIO1_IO0 731 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
732 >; 732 >;
733 }; 733 };
734 734
735 pinctrl_rtc: rtc-grp { 735 pinctrl_rtc: rtc-grp {
736 fsl,pins = < 736 fsl,pins = <
737 /* RTC_IRQ# */ 737 /* RTC_IRQ# */
738 MX8MM_IOMUXC_GPIO1_IO0 738 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
739 >; 739 >;
740 }; 740 };
741 741
742 pinctrl_sai5: sai5-grp { 742 pinctrl_sai5: sai5-grp {
743 fsl,pins = < 743 fsl,pins = <
744 MX8MM_IOMUXC_SAI5_MCLK 744 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
745 MX8MM_IOMUXC_SAI5_RXD0 745 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
746 MX8MM_IOMUXC_SAI5_RXD1 746 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
747 MX8MM_IOMUXC_SAI5_RXD2 747 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
748 MX8MM_IOMUXC_SAI5_RXD3 748 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
749 >; 749 >;
750 }; 750 };
751 751
752 pinctrl_uart1: uart1-grp { 752 pinctrl_uart1: uart1-grp {
753 fsl,pins = < 753 fsl,pins = <
754 MX8MM_IOMUXC_SAI2_RXC_ 754 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
755 MX8MM_IOMUXC_SAI2_RXD0 755 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
756 MX8MM_IOMUXC_SAI2_RXFS 756 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
757 MX8MM_IOMUXC_SAI2_TXFS 757 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
758 >; 758 >;
759 }; 759 };
760 760
761 pinctrl_uart2: uart2-grp { 761 pinctrl_uart2: uart2-grp {
762 fsl,pins = < 762 fsl,pins = <
763 MX8MM_IOMUXC_SAI3_RXC_ 763 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
764 MX8MM_IOMUXC_SAI3_RXD_ 764 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
765 MX8MM_IOMUXC_SAI3_TXC_ 765 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
766 MX8MM_IOMUXC_SAI3_TXFS 766 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
767 >; 767 >;
768 }; 768 };
769 769
770 pinctrl_uart3: uart3-grp { 770 pinctrl_uart3: uart3-grp {
771 fsl,pins = < 771 fsl,pins = <
772 MX8MM_IOMUXC_UART3_RXD 772 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
773 MX8MM_IOMUXC_UART3_TXD 773 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
774 >; 774 >;
775 }; 775 };
776 776
777 pinctrl_uart4: uart4-grp { 777 pinctrl_uart4: uart4-grp {
778 fsl,pins = < 778 fsl,pins = <
779 MX8MM_IOMUXC_UART4_RXD 779 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
780 MX8MM_IOMUXC_UART4_TXD 780 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
781 >; 781 >;
782 }; 782 };
783 783
784 pinctrl_usb_hub: usb-hub-grp { 784 pinctrl_usb_hub: usb-hub-grp {
785 fsl,pins = < 785 fsl,pins = <
786 /* USBHUB_RESET# */ 786 /* USBHUB_RESET# */
787 MX8MM_IOMUXC_SAI3_MCLK 787 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
788 >; 788 >;
789 }; 789 };
790 790
791 pinctrl_usb_otg1: usb-otg1-grp { 791 pinctrl_usb_otg1: usb-otg1-grp {
792 fsl,pins = < 792 fsl,pins = <
793 MX8MM_IOMUXC_GPIO1_IO1 793 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
794 MX8MM_IOMUXC_GPIO1_IO1 794 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
795 MX8MM_IOMUXC_GPIO1_IO1 795 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
796 >; 796 >;
797 }; 797 };
798 798
799 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg 799 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
800 fsl,pins = < 800 fsl,pins = <
801 MX8MM_IOMUXC_SD2_RESET 801 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
802 >; 802 >;
803 }; 803 };
804 804
805 pinctrl_usdhc2: usdhc2-grp { 805 pinctrl_usdhc2: usdhc2-grp {
806 fsl,pins = < 806 fsl,pins = <
807 MX8MM_IOMUXC_SD2_CLK_U 807 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
808 MX8MM_IOMUXC_SD2_CMD_U 808 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
809 MX8MM_IOMUXC_SD2_DATA0 809 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
810 MX8MM_IOMUXC_SD2_DATA1 810 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
811 MX8MM_IOMUXC_SD2_DATA2 811 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
812 MX8MM_IOMUXC_SD2_DATA3 812 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
813 MX8MM_IOMUXC_SD2_WP_US 813 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
814 MX8MM_IOMUXC_SD2_CD_B_ 814 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
815 MX8MM_IOMUXC_GPIO1_IO0 815 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 816 >;
817 }; 817 };
818 818
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g 819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
820 fsl,pins = < 820 fsl,pins = <
821 MX8MM_IOMUXC_SD2_CLK_U 821 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
822 MX8MM_IOMUXC_SD2_CMD_U 822 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
823 MX8MM_IOMUXC_SD2_DATA0 823 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
824 MX8MM_IOMUXC_SD2_DATA1 824 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
825 MX8MM_IOMUXC_SD2_DATA2 825 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
826 MX8MM_IOMUXC_SD2_DATA3 826 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
827 MX8MM_IOMUXC_SD2_WP_US 827 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
828 MX8MM_IOMUXC_SD2_CD_B_ 828 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
829 MX8MM_IOMUXC_GPIO1_IO0 829 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
830 >; 830 >;
831 }; 831 };
832 832
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g 833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
834 fsl,pins = < 834 fsl,pins = <
835 MX8MM_IOMUXC_SD2_CLK_U 835 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
836 MX8MM_IOMUXC_SD2_CMD_U 836 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
837 MX8MM_IOMUXC_SD2_DATA0 837 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
838 MX8MM_IOMUXC_SD2_DATA1 838 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
839 MX8MM_IOMUXC_SD2_DATA2 839 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
840 MX8MM_IOMUXC_SD2_DATA3 840 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
841 MX8MM_IOMUXC_SD2_WP_US 841 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
842 MX8MM_IOMUXC_SD2_CD_B_ 842 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
843 MX8MM_IOMUXC_GPIO1_IO0 843 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
844 >; 844 >;
845 }; 845 };
846 846
847 pinctrl_usdhc3: usdhc3-grp { 847 pinctrl_usdhc3: usdhc3-grp {
848 fsl,pins = < 848 fsl,pins = <
849 MX8MM_IOMUXC_NAND_WE_B 849 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
850 MX8MM_IOMUXC_NAND_WP_B 850 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
851 MX8MM_IOMUXC_NAND_DATA 851 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
852 MX8MM_IOMUXC_NAND_DATA 852 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
853 MX8MM_IOMUXC_NAND_DATA 853 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
854 MX8MM_IOMUXC_NAND_DATA 854 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
855 MX8MM_IOMUXC_NAND_RE_B 855 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
856 MX8MM_IOMUXC_NAND_CE2_ 856 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
857 MX8MM_IOMUXC_NAND_CE3_ 857 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
858 MX8MM_IOMUXC_NAND_CLE_ 858 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
859 MX8MM_IOMUXC_NAND_CE1_ 859 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
860 MX8MM_IOMUXC_NAND_READ 860 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
861 >; 861 >;
862 }; 862 };
863 863
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g 864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
865 fsl,pins = < 865 fsl,pins = <
866 MX8MM_IOMUXC_NAND_WE_B 866 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
867 MX8MM_IOMUXC_NAND_WP_B 867 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
868 MX8MM_IOMUXC_NAND_DATA 868 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
869 MX8MM_IOMUXC_NAND_DATA 869 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
870 MX8MM_IOMUXC_NAND_DATA 870 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
871 MX8MM_IOMUXC_NAND_DATA 871 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
872 MX8MM_IOMUXC_NAND_RE_B 872 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
873 MX8MM_IOMUXC_NAND_CE2_ 873 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
874 MX8MM_IOMUXC_NAND_CE3_ 874 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
875 MX8MM_IOMUXC_NAND_CLE_ 875 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
876 MX8MM_IOMUXC_NAND_CE1_ 876 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
877 MX8MM_IOMUXC_NAND_READ 877 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
878 >; 878 >;
879 }; 879 };
880 880
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g 881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
882 fsl,pins = < 882 fsl,pins = <
883 MX8MM_IOMUXC_NAND_WE_B 883 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
884 MX8MM_IOMUXC_NAND_WP_B 884 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
885 MX8MM_IOMUXC_NAND_DATA 885 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
886 MX8MM_IOMUXC_NAND_DATA 886 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
887 MX8MM_IOMUXC_NAND_DATA 887 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
888 MX8MM_IOMUXC_NAND_DATA 888 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
889 MX8MM_IOMUXC_NAND_RE_B 889 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
890 MX8MM_IOMUXC_NAND_CE2_ 890 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
891 MX8MM_IOMUXC_NAND_CE3_ 891 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
892 MX8MM_IOMUXC_NAND_CLE_ 892 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
893 MX8MM_IOMUXC_NAND_CE1_ 893 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
894 MX8MM_IOMUXC_NAND_READ 894 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
895 >; 895 >;
896 }; 896 };
897 897
898 pinctrl_watchdog_gpio: watchdog-gpio-g 898 pinctrl_watchdog_gpio: watchdog-gpio-grp {
899 fsl,pins = < 899 fsl,pins = <
900 /* WDOG_B# */ 900 /* WDOG_B# */
901 MX8MM_IOMUXC_GPIO1_IO0 901 MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
902 /* WDOG_EN -- ungate W 902 /* WDOG_EN -- ungate WDT RESET# signal propagation */
903 MX8MM_IOMUXC_SD1_DATA7 903 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
904 /* WDOG_KICK# / WDI */ 904 /* WDOG_KICK# / WDI */
905 MX8MM_IOMUXC_GPIO1_IO0 905 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
906 >; 906 >;
907 }; 907 };
908 }; 908 };
909 909
910 &pcie_phy { 910 &pcie_phy {
911 fsl,clkreq-unsupported; /* CLKREQ_B is 911 fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
912 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 912 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
913 fsl,tx-deemph-gen1 = <0x2d>; 913 fsl,tx-deemph-gen1 = <0x2d>;
914 fsl,tx-deemph-gen2 = <0xf>; 914 fsl,tx-deemph-gen2 = <0xf>;
915 clocks = <&pcieclk 0>; 915 clocks = <&pcieclk 0>;
916 status = "okay"; 916 status = "okay";
917 }; 917 };
918 918
919 &pcie0 { 919 &pcie0 {
920 pinctrl-names = "default"; 920 pinctrl-names = "default";
921 pinctrl-0 = <&pinctrl_pcie0>; 921 pinctrl-0 = <&pinctrl_pcie0>;
922 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW 922 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
923 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 923 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
924 <&clk IMX8MM_CLK_PCIE1_AUX>; 924 <&clk IMX8MM_CLK_PCIE1_AUX>;
925 assigned-clocks = <&clk IMX8MM_CLK_PCI 925 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
926 <&clk IMX8MM_CLK_PCI 926 <&clk IMX8MM_CLK_PCIE1_CTRL>;
927 assigned-clock-rates = <10000000>, <25 927 assigned-clock-rates = <10000000>, <250000000>;
928 assigned-clock-parents = <&clk IMX8MM_ 928 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
929 <&clk IMX8MM_ 929 <&clk IMX8MM_SYS_PLL2_250M>;
930 status = "okay"; 930 status = "okay";
931 }; 931 };
932 932
933 &pwm1 { 933 &pwm1 {
934 pinctrl-names = "default"; 934 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_panel_pwm>; 935 pinctrl-0 = <&pinctrl_panel_pwm>;
936 /* Disabled by default, unless display 936 /* Disabled by default, unless display board plugged in. */
937 status = "disabled"; 937 status = "disabled";
938 }; 938 };
939 939
940 &sai5 { 940 &sai5 {
941 pinctrl-names = "default"; 941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_sai5>; 942 pinctrl-0 = <&pinctrl_sai5>;
943 fsl,sai-mclk-direction-output; 943 fsl,sai-mclk-direction-output;
944 /* Input into codec PLL */ 944 /* Input into codec PLL */
945 assigned-clocks = <&clk IMX8MM_CLK_SAI 945 assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
946 assigned-clock-parents = <&clk IMX8MM_ 946 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
947 assigned-clock-rates = <22579200>; 947 assigned-clock-rates = <22579200>;
948 /* Disabled by default, unless display 948 /* Disabled by default, unless display board plugged in. */
949 status = "disabled"; 949 status = "disabled";
950 }; 950 };
951 951
952 &snvs_rtc { 952 &snvs_rtc {
953 clocks = <&pmic>; 953 clocks = <&pmic>;
954 }; 954 };
955 955
956 &uart1 { 956 &uart1 {
957 pinctrl-names = "default"; 957 pinctrl-names = "default";
958 pinctrl-0 = <&pinctrl_uart1>; 958 pinctrl-0 = <&pinctrl_uart1>;
959 uart-has-rtscts; 959 uart-has-rtscts;
960 status = "disabled"; 960 status = "disabled";
961 }; 961 };
962 962
963 &uart2 { 963 &uart2 {
964 pinctrl-names = "default"; 964 pinctrl-names = "default";
965 pinctrl-0 = <&pinctrl_uart2>; 965 pinctrl-0 = <&pinctrl_uart2>;
966 status = "disabled"; 966 status = "disabled";
967 }; 967 };
968 968
969 &uart3 { /* A53 Debug */ 969 &uart3 { /* A53 Debug */
970 pinctrl-names = "default"; 970 pinctrl-names = "default";
971 pinctrl-0 = <&pinctrl_uart3>; 971 pinctrl-0 = <&pinctrl_uart3>;
972 status = "okay"; 972 status = "okay";
973 }; 973 };
974 974
975 &uart4 { /* M4 Debug */ 975 &uart4 { /* M4 Debug */
976 pinctrl-names = "default"; 976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_uart4>; 977 pinctrl-0 = <&pinctrl_uart4>;
978 /* UART4 is reserved for CM and RDC bl 978 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
979 status = "disabled"; 979 status = "disabled";
980 }; 980 };
981 981
982 &usbotg1 { 982 &usbotg1 {
983 pinctrl-names = "default"; 983 pinctrl-names = "default";
984 pinctrl-0 = <&pinctrl_usb_otg1>; 984 pinctrl-0 = <&pinctrl_usb_otg1>;
985 dr_mode = "otg"; 985 dr_mode = "otg";
986 status = "okay"; 986 status = "okay";
987 }; 987 };
988 988
989 &usbotg2 { 989 &usbotg2 {
990 disable-over-current; 990 disable-over-current;
991 dr_mode = "host"; 991 dr_mode = "host";
992 status = "okay"; 992 status = "okay";
993 }; 993 };
994 994
995 &usdhc2 { /* MicroSD */ 995 &usdhc2 { /* MicroSD */
996 assigned-clocks = <&clk IMX8MM_CLK_USD 996 assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
997 pinctrl-names = "default", "state_100m 997 pinctrl-names = "default", "state_100mhz", "state_200mhz";
998 pinctrl-0 = <&pinctrl_usdhc2>; 998 pinctrl-0 = <&pinctrl_usdhc2>;
999 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 999 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
1000 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1000 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
1001 bus-width = <4>; 1001 bus-width = <4>;
1002 vmmc-supply = <®_usdhc2_vcc>; 1002 vmmc-supply = <®_usdhc2_vcc>;
1003 status = "okay"; 1003 status = "okay";
1004 }; 1004 };
1005 1005
1006 &usdhc3 { /* eMMC */ 1006 &usdhc3 { /* eMMC */
1007 assigned-clocks = <&clk IMX8MM_CLK_US 1007 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
1008 assigned-clock-rates = <400000000>; 1008 assigned-clock-rates = <400000000>;
1009 pinctrl-names = "default", "state_100 1009 pinctrl-names = "default", "state_100mhz", "state_200mhz";
1010 pinctrl-0 = <&pinctrl_usdhc3>; 1010 pinctrl-0 = <&pinctrl_usdhc3>;
1011 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 1011 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
1012 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 1012 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
1013 bus-width = <8>; 1013 bus-width = <8>;
1014 non-removable; 1014 non-removable;
1015 vmmc-supply = <&buck4_reg>; 1015 vmmc-supply = <&buck4_reg>;
1016 vqmmc-supply = <&buck5_reg>; 1016 vqmmc-supply = <&buck5_reg>;
1017 status = "okay"; 1017 status = "okay";
1018 }; 1018 };
1019 1019
1020 &wdog1 { 1020 &wdog1 {
1021 status = "okay"; 1021 status = "okay";
1022 }; 1022 };
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