1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 NXP
4 */
5
6 /dts-v1/;
7
8 #include "imx8mm-evk.dtsi"
9
10 / {
11 model = "FSL i.MX8MM DDR4 EVK with CYW
12 compatible = "fsl,imx8mm-ddr4-evk", "f
13
14 leds {
15 pinctrl-0 = <&pinctrl_gpio_led
16
17 status {
18 gpios = <&gpio3 4 GPIO
19 };
20 };
21 };
22
23 &gpmi {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpmi_nand>;
26 status = "okay";
27 };
28
29 &iomuxc {
30 pinctrl_gpmi_nand: gpminandgrp {
31 fsl,pins = <
32 MX8MM_IOMUXC_NAND_ALE_
33 MX8MM_IOMUXC_NAND_CE0_
34 MX8MM_IOMUXC_NAND_CE1_
35 MX8MM_IOMUXC_NAND_CLE_
36 MX8MM_IOMUXC_NAND_DATA
37 MX8MM_IOMUXC_NAND_DATA
38 MX8MM_IOMUXC_NAND_DATA
39 MX8MM_IOMUXC_NAND_DATA
40 MX8MM_IOMUXC_NAND_DATA
41 MX8MM_IOMUXC_NAND_DATA
42 MX8MM_IOMUXC_NAND_DATA
43 MX8MM_IOMUXC_NAND_DATA
44 MX8MM_IOMUXC_NAND_RE_B
45 MX8MM_IOMUXC_NAND_READ
46 MX8MM_IOMUXC_NAND_WE_B
47 MX8MM_IOMUXC_NAND_WP_B
48 >;
49 };
50
51 pinctrl_gpio_led_2: gpioled2grp {
52 fsl,pins = <
53 MX8MM_IOMUXC_NAND_CE3_
54 >;
55 };
56 };
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