1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Copyright 2018 NXP
4 // Copyright (C) 2021 emtrion GmbH
5 //
6
7 /dts-v1/;
8
9 #include "imx8mm.dtsi"
10
11 / {
12 chosen {
13 stdout-path = &uart1;
14 };
15
16 som_leds: leds {
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_led
20
21 led-green {
22 label = "som:green";
23 gpios = <&gpio3 4 GPIO
24 default-state = "on";
25 linux,default-trigger
26 };
27
28 led-red {
29 label = "som:red";
30 gpios = <&gpio5 10 GPI
31 default-state = "off";
32 };
33 };
34
35 lvds_backlight: lvds-backlight {
36 compatible = "pwm-backlight";
37 enable-gpios = <&gpio3 23 GPIO
38 pwms = <&pwm1 0 50000 0>;
39 brightness-levels = <
40 0 4 8 16 32 64 80 96 1
41 128 144 160 176 250
42 >;
43 default-brightness-level = <9>
44 status = "disabled";
45 };
46
47 reg_usdhc1_vmmc: regulator-emmc {
48 compatible = "regulator-fixed"
49 regulator-name = "eMMC";
50 regulator-min-microvolt = <330
51 regulator-max-microvolt = <330
52 };
53
54 reg_usdhc2_vmmc: regulator-usdhc2 {
55 compatible = "regulator-fixed"
56 regulator-name = "sdcard_3V3";
57 regulator-min-microvolt = <330
58 regulator-max-microvolt = <330
59 };
60 };
61
62 &A53_0 {
63 cpu-supply = <&buck2_reg>;
64 };
65
66 &ecspi1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_
69 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
70 <&gpio5 13 GPI
71 status = "okay";
72 };
73
74 &fec1 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>;
79 fsl,magic-packet;
80 status = "okay";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet
88 reg = <0>;
89 reset-gpios = <&gpio1
90 reset-assert-us = <100
91 };
92 };
93 };
94
95 &flexspi {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_flexspi0>;
98 pinctrl-1 = <&pinctrl_flexspi1>;
99 status = "okay";
100
101 flash0: flash@0 {
102 reg = <0>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "jedec,spi-nor";
106 spi-max-frequency = <40000000>
107 };
108 };
109
110 &iomuxc {
111 pinctrl_csi_pwn: csi-pwn-grp {
112 fsl,pins = <
113 MX8MM_IOMUXC_GPIO1_IO0
114 >;
115 };
116
117 pinctrl_ecspi1: ecspi1-grp {
118 fsl,pins = <
119 MX8MM_IOMUXC_ECSPI1_SC
120 MX8MM_IOMUXC_ECSPI1_MO
121 MX8MM_IOMUXC_ECSPI1_MI
122 >;
123 };
124
125 pinctrl_ecspi1_cs: ecspi1cs-grp {
126 fsl,pins = <
127 MX8MM_IOMUXC_ECSPI1_SS
128 MX8MM_IOMUXC_ECSPI2_SS
129 >;
130 };
131
132 pinctrl_fec1: fec1-grp {
133 fsl,pins = <
134 MX8MM_IOMUXC_ENET_MDC_
135 MX8MM_IOMUXC_ENET_MDIO
136 MX8MM_IOMUXC_ENET_TD3_
137 MX8MM_IOMUXC_ENET_TD2_
138 MX8MM_IOMUXC_ENET_TD1_
139 MX8MM_IOMUXC_ENET_TD0_
140 MX8MM_IOMUXC_ENET_RD3_
141 MX8MM_IOMUXC_ENET_RD2_
142 MX8MM_IOMUXC_ENET_RD1_
143 MX8MM_IOMUXC_ENET_RD0_
144 MX8MM_IOMUXC_ENET_TXC_
145 MX8MM_IOMUXC_ENET_RXC_
146 MX8MM_IOMUXC_ENET_RX_C
147 MX8MM_IOMUXC_ENET_TX_C
148 MX8MM_IOMUXC_GPIO1_IO0
149 >;
150 };
151
152 pinctrl_flexspi0: flexspi0-grp {
153 fsl,pins = <
154 MX8MM_IOMUXC_NAND_ALE_
155 MX8MM_IOMUXC_NAND_CE0_
156 MX8MM_IOMUXC_NAND_DATA
157 MX8MM_IOMUXC_NAND_DATA
158 MX8MM_IOMUXC_NAND_DATA
159 MX8MM_IOMUXC_NAND_DATA
160 MX8MM_IOMUXC_NAND_DQS_
161 >;
162 };
163
164 pinctrl_flexspi1: flexspi1-grp {
165 fsl,pins = <
166 MX8MM_IOMUXC_NAND_CLE_
167 MX8MM_IOMUXC_NAND_CE2_
168 MX8MM_IOMUXC_NAND_DATA
169 MX8MM_IOMUXC_NAND_DATA
170 MX8MM_IOMUXC_NAND_DATA
171 MX8MM_IOMUXC_NAND_DATA
172 >;
173 };
174
175 pinctrl_gpio_led: gpio-led-grp {
176 fsl,pins = <
177 MX8MM_IOMUXC_ECSPI2_SC
178 MX8MM_IOMUXC_NAND_CE3_
179 >;
180 };
181
182 pinctrl_i2c1: i2c1-grp {
183 fsl,pins = <
184 MX8MM_IOMUXC_I2C1_SCL_
185 MX8MM_IOMUXC_I2C1_SDA_
186 >;
187 };
188
189 pinctrl_i2c2: i2c2grp {
190 fsl,pins = <
191 MX8MM_IOMUXC_I2C2_SCL_
192 MX8MM_IOMUXC_I2C2_SDA_
193 >;
194 };
195
196 pinctrl_i2c3: i2c3-grp {
197 fsl,pins = <
198 MX8MM_IOMUXC_I2C3_SCL_
199 MX8MM_IOMUXC_I2C3_SDA_
200 >;
201 };
202
203 pinctrl_lvds: lvds-grp {
204 fsl,pins = <
205 MX8MM_IOMUXC_SAI5_MCLK
206 >;
207 };
208
209 pinctrl_pcie0: pcie0-grp {
210 fsl,pins = <
211 MX8MM_IOMUXC_SAI5_RXC_
212 MX8MM_IOMUXC_SAI5_RXFS
213 >;
214 };
215
216 pinctrl_pmic: pmicirq-grp {
217 fsl,pins = <
218 MX8MM_IOMUXC_NAND_CE1_
219 >;
220 };
221
222 pinctrl_pwm1: pwm1-grp {
223 fsl,pins = <
224 MX8MM_IOMUXC_GPIO1_IO0
225 >;
226 };
227
228 pinctrl_sai2: sai2-grp {
229 fsl,pins = <
230 MX8MM_IOMUXC_SAI2_MCLK
231 MX8MM_IOMUXC_SAI2_RXC_
232 MX8MM_IOMUXC_SAI2_RXD0
233 MX8MM_IOMUXC_SAI2_RXFS
234 MX8MM_IOMUXC_SAI2_TXC_
235 MX8MM_IOMUXC_SAI2_TXD0
236 MX8MM_IOMUXC_SAI2_TXFS
237 >;
238 };
239
240 pinctrl_spdif1: spdif1-grp {
241 fsl,pins = <
242 MX8MM_IOMUXC_SPDIF_TX_
243 MX8MM_IOMUXC_SPDIF_RX_
244 >;
245 };
246
247 pinctrl_uart1: uart1-grp {
248 fsl,pins = <
249 MX8MM_IOMUXC_UART1_RXD
250 MX8MM_IOMUXC_UART1_TXD
251 >;
252 };
253
254 pinctrl_uart2: uart2-grp {
255 fsl,pins = <
256 MX8MM_IOMUXC_UART2_RXD
257 MX8MM_IOMUXC_UART2_TXD
258
259 /* rts and cts */
260 MX8MM_IOMUXC_SAI3_RXC_
261 MX8MM_IOMUXC_SAI3_RXD_
262 >;
263 };
264
265 pinctrl_uart3: uart3-grp {
266 fsl,pins = <
267 MX8MM_IOMUXC_UART3_RXD
268 MX8MM_IOMUXC_UART3_TXD
269 >;
270 };
271
272 pinctrl_uart4: uart4-grp {
273 fsl,pins = <
274 MX8MM_IOMUXC_UART4_RXD
275 MX8MM_IOMUXC_UART4_TXD
276 >;
277 };
278
279 pinctrl_usdhc1: usdhc1-grp {
280 fsl,pins = <
281 MX8MM_IOMUXC_SD1_CLK_U
282 MX8MM_IOMUXC_SD1_CMD_U
283 MX8MM_IOMUXC_SD1_DATA0
284 MX8MM_IOMUXC_SD1_DATA1
285 MX8MM_IOMUXC_SD1_DATA2
286 MX8MM_IOMUXC_SD1_DATA3
287 MX8MM_IOMUXC_SD1_DATA4
288 MX8MM_IOMUXC_SD1_DATA5
289 MX8MM_IOMUXC_SD1_DATA6
290 MX8MM_IOMUXC_SD1_DATA7
291 >;
292 };
293
294 pinctrl_usdhc1_100mhz: usdhc1-100mhz-g
295 fsl,pins = <
296 MX8MM_IOMUXC_SD1_CLK_U
297 MX8MM_IOMUXC_SD1_CMD_U
298 MX8MM_IOMUXC_SD1_DATA0
299 MX8MM_IOMUXC_SD1_DATA1
300 MX8MM_IOMUXC_SD1_DATA2
301 MX8MM_IOMUXC_SD1_DATA3
302 MX8MM_IOMUXC_SD1_DATA4
303 MX8MM_IOMUXC_SD1_DATA5
304 MX8MM_IOMUXC_SD1_DATA6
305 MX8MM_IOMUXC_SD1_DATA7
306 >;
307 };
308
309 pinctrl_usdhc1_200mhz: usdhc1-200mhz-g
310 fsl,pins = <
311 MX8MM_IOMUXC_SD1_CLK_U
312 MX8MM_IOMUXC_SD1_CMD_U
313 MX8MM_IOMUXC_SD1_DATA0
314 MX8MM_IOMUXC_SD1_DATA1
315 MX8MM_IOMUXC_SD1_DATA2
316 MX8MM_IOMUXC_SD1_DATA3
317 MX8MM_IOMUXC_SD1_DATA4
318 MX8MM_IOMUXC_SD1_DATA5
319 MX8MM_IOMUXC_SD1_DATA6
320 MX8MM_IOMUXC_SD1_DATA7
321 >;
322 };
323
324 pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
325 fsl,pins = <
326 MX8MM_IOMUXC_SD1_RESET
327 MX8MM_IOMUXC_GPIO1_IO0
328 >;
329 };
330
331 pinctrl_usdhc2: usdhc2-grp {
332 fsl,pins = <
333 MX8MM_IOMUXC_SD2_CLK_U
334 MX8MM_IOMUXC_SD2_CMD_U
335 MX8MM_IOMUXC_SD2_DATA0
336 MX8MM_IOMUXC_SD2_DATA1
337 MX8MM_IOMUXC_SD2_DATA2
338 MX8MM_IOMUXC_SD2_DATA3
339 MX8MM_IOMUXC_GPIO1_IO0
340 >;
341 };
342
343 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g
344 fsl,pins = <
345 MX8MM_IOMUXC_SD2_CLK_U
346 MX8MM_IOMUXC_SD2_CMD_U
347 MX8MM_IOMUXC_SD2_DATA0
348 MX8MM_IOMUXC_SD2_DATA1
349 MX8MM_IOMUXC_SD2_DATA2
350 MX8MM_IOMUXC_SD2_DATA3
351 MX8MM_IOMUXC_GPIO1_IO0
352 >;
353 };
354
355 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g
356 fsl,pins = <
357 MX8MM_IOMUXC_SD2_CLK_U
358 MX8MM_IOMUXC_SD2_CMD_U
359 MX8MM_IOMUXC_SD2_DATA0
360 MX8MM_IOMUXC_SD2_DATA1
361 MX8MM_IOMUXC_SD2_DATA2
362 MX8MM_IOMUXC_SD2_DATA3
363 MX8MM_IOMUXC_GPIO1_IO0
364 >;
365 };
366
367 /* no reset for sdhc2 interface */
368 pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
369 fsl,pins = <
370 MX8MM_IOMUXC_SD2_CD_B_
371 MX8MM_IOMUXC_SD2_WP_US
372 >;
373 };
374
375 pinctrl_wdog: wdog-grp {
376 fsl,pins = <
377 MX8MM_IOMUXC_GPIO1_IO0
378 >;
379 };
380 };
381
382 &i2c1 {
383 clock-frequency = <400000>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_i2c1>;
386 status = "okay";
387 };
388
389 &i2c2 {
390 clock-frequency = <400000>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c2>;
393 status = "okay";
394 };
395
396 &i2c3 {
397 clock-frequency = <400000>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_i2c3>;
400 status = "okay";
401
402 bd71847: pmic@4b {
403 compatible = "rohm,bd71847";
404 reg = <0x4b>;
405 pinctrl-0 = <&pinctrl_pmic>;
406 interrupt-parent = <&gpio3>;
407 interrupts = <2 IRQ_TYPE_LEVEL
408 rohm,reset-snvs-powered;
409
410 regulators {
411 buck1_reg: BUCK1 {
412 regulator-name
413 regulator-min-
414 regulator-max-
415 regulator-boot
416 regulator-alwa
417 regulator-ramp
418 };
419
420 buck2_reg: BUCK2 {
421 regulator-name
422 regulator-min-
423 regulator-max-
424 regulator-boot
425 regulator-alwa
426 regulator-ramp
427 rohm,dvs-run-v
428 rohm,dvs-idle-
429 };
430
431 buck3_reg: BUCK3 {
432 // BUCK5 in da
433 regulator-name
434 regulator-min-
435 regulator-max-
436 regulator-boot
437 regulator-alwa
438 };
439
440 buck4_reg: BUCK4 {
441 // BUCK6 in da
442 regulator-name
443 regulator-min-
444 regulator-max-
445 regulator-boot
446 regulator-alwa
447 };
448
449 buck5_reg: BUCK5 {
450 // BUCK7 in da
451 regulator-name
452 regulator-min-
453 regulator-max-
454 regulator-boot
455 regulator-alwa
456 };
457
458 buck6_reg: BUCK6 {
459 // BUCK8 in da
460 regulator-name
461 regulator-min-
462 regulator-max-
463 regulator-boot
464 regulator-alwa
465 };
466
467 ldo1_reg: LDO1 {
468 regulator-name
469 regulator-min-
470 regulator-max-
471 regulator-boot
472 regulator-alwa
473 };
474
475 ldo2_reg: LDO2 {
476 regulator-name
477 regulator-min-
478 regulator-max-
479 regulator-boot
480 regulator-alwa
481 };
482
483 ldo3_reg: LDO3 {
484 regulator-name
485 regulator-min-
486 regulator-max-
487 regulator-boot
488 regulator-alwa
489 };
490
491 ldo4_reg: LDO4 {
492 regulator-name
493 regulator-min-
494 regulator-max-
495 regulator-boot
496 regulator-alwa
497 };
498
499 ldo6_reg: LDO6 {
500 regulator-name
501 regulator-min-
502 regulator-max-
503 regulator-boot
504 regulator-alwa
505 };
506 };
507 };
508
509 rv1805: rtc@69 {
510 compatible = "abracon,ab1805";
511 reg = <0x69>;
512 };
513 };
514
515 &mu {
516 status = "okay";
517 };
518
519 &pwm1 {
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_pwm1>;
522 };
523
524 &sai2 {
525 #sound-dai-cells = <0>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_sai2>;
528 assigned-clocks = <&clk IMX8MM_CLK_SAI
529 assigned-clock-parents = <&clk IMX8MM_
530 assigned-clock-rates = <12000000>;
531 status = "disabled";
532 };
533
534 &spdif1 {
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_spdif1>;
537 assigned-clocks = <&clk IMX8MM_CLK_SPD
538 assigned-clock-parents = <&clk IMX8MM_
539 assigned-clock-rates = <24576000>;
540 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>,
541 <&clk IMX8MM_CLK_SPDIF1>, <&cl
542 <&clk IMX8MM_CLK_DUMMY>, <&clk
543 <&clk IMX8MM_CLK_AUDIO_AHB>, <
544 <&clk IMX8MM_CLK_DUMMY>, <&clk
545 <&clk IMX8MM_AUDIO_PLL1_OUT>,
546 clock-names = "core", "rxtx0", "rxtx1"
547 "rxtx4", "rxtx5", "rxtx6", "rx
548 status = "disabled";
549 };
550
551 &uart1 { /* console */
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_uart1>;
554 assigned-clocks = <&clk IMX8MM_CLK_UAR
555 assigned-clock-parents = <&clk IMX8MM_
556 status = "okay";
557 };
558
559 &uart2 {
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_uart2>;
562 assigned-clocks = <&clk IMX8MM_CLK_UAR
563 assigned-clock-parents = <&clk IMX8MM_
564 status = "okay";
565 };
566
567 &uart3 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_uart3>;
570 assigned-clocks = <&clk IMX8MM_CLK_UAR
571 assigned-clock-parents = <&clk IMX8MM_
572 status = "okay";
573 };
574
575 &uart4 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_uart4>;
578 assigned-clocks = <&clk IMX8MM_CLK_UAR
579 assigned-clock-parents = <&clk IMX8MM_
580 status = "okay";
581 };
582
583 &usbotg1 {
584 dr_mode = "otg";
585 over-current-active-low;
586 status = "okay";
587 };
588
589 &usbotg2 {
590 dr_mode = "host";
591 disable-over-current;
592 status = "disabled";
593 };
594
595 &usdhc1 {
596 pinctrl-names = "default", "state_100m
597 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct
598 pinctrl-1 = <&pinctrl_usdhc1_100mhz>,
599 pinctrl-2 = <&pinctrl_usdhc1_200mhz>,
600 bus-width = <8>;
601 vmmc-supply = <®_usdhc1_vmmc>;
602 keep-power-in-suspend;
603 non-removable;
604 status = "okay";
605 };
606
607 &usdhc2 {
608 pinctrl-names = "default", "state_100m
609 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
610 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
611 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
612 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
613 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH
614 bus-width = <4>;
615 vmmc-supply = <®_usdhc2_vmmc>;
616 no-1-8-v;
617 status = "okay";
618 };
619
620 &wdog1 {
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_wdog>;
623 fsl,ext-reset-output;
624 status = "okay";
625 };
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