1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2023 Emtop Embedded Solutions 3 * Copyright 2023 Emtop Embedded Solutions
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h> 9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/usb/pd.h> 10 #include <dt-bindings/usb/pd.h>
11 11
12 #include "imx8mm.dtsi" 12 #include "imx8mm.dtsi"
13 13
14 / { 14 / {
15 model = "Emtop Embedded Solutions i.MX 15 model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
16 compatible = "ees,imx8mm-emtop-som", " 16 compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart2; 19 stdout-path = &uart2;
20 }; 20 };
21 21
22 leds { 22 leds {
23 compatible = "gpio-leds"; 23 compatible = "gpio-leds";
24 pinctrl-names = "default"; 24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_led 25 pinctrl-0 = <&pinctrl_gpio_led>;
26 26
27 led-0 { 27 led-0 {
28 function = LED_FUNCTIO 28 function = LED_FUNCTION_POWER;
29 gpios = <&gpio3 16 GPI 29 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
30 linux,default-trigger 30 linux,default-trigger = "heartbeat";
31 }; 31 };
32 }; 32 };
33 }; 33 };
34 34
35 &A53_0 { 35 &A53_0 {
36 cpu-supply = <&buck2>; 36 cpu-supply = <&buck2>;
37 }; 37 };
38 38
39 &A53_1 { 39 &A53_1 {
40 cpu-supply = <&buck2>; 40 cpu-supply = <&buck2>;
41 }; 41 };
42 42
43 &A53_2 { 43 &A53_2 {
44 cpu-supply = <&buck2>; 44 cpu-supply = <&buck2>;
45 }; 45 };
46 46
47 &A53_3 { 47 &A53_3 {
48 cpu-supply = <&buck2>; 48 cpu-supply = <&buck2>;
49 }; 49 };
50 50
51 &i2c1 { 51 &i2c1 {
52 clock-frequency = <400000>; 52 clock-frequency = <400000>;
53 pinctrl-names = "default"; 53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c1>; 54 pinctrl-0 = <&pinctrl_i2c1>;
55 status = "okay"; 55 status = "okay";
56 56
57 pmic@25 { 57 pmic@25 {
58 compatible = "nxp,pca9450c"; 58 compatible = "nxp,pca9450c";
59 reg = <0x25>; 59 reg = <0x25>;
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pmic>; 61 pinctrl-0 = <&pinctrl_pmic>;
62 interrupt-parent = <&gpio1>; 62 interrupt-parent = <&gpio1>;
63 interrupts = <3 IRQ_TYPE_EDGE_ 63 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
64 64
65 regulators { 65 regulators {
66 buck1: BUCK1 { 66 buck1: BUCK1 {
67 regulator-name 67 regulator-name = "BUCK1";
68 regulator-min- 68 regulator-min-microvolt = <800000>;
69 regulator-max- 69 regulator-max-microvolt = <1000000>;
70 regulator-boot 70 regulator-boot-on;
71 regulator-alwa 71 regulator-always-on;
72 regulator-ramp 72 regulator-ramp-delay = <3125>;
73 }; 73 };
74 74
75 buck2: BUCK2 { 75 buck2: BUCK2 {
76 regulator-name 76 regulator-name = "BUCK2";
77 regulator-min- 77 regulator-min-microvolt = <800000>;
78 regulator-max- 78 regulator-max-microvolt = <900000>;
79 regulator-boot 79 regulator-boot-on;
80 regulator-alwa 80 regulator-always-on;
81 regulator-ramp 81 regulator-ramp-delay = <3125>;
82 }; 82 };
83 83
84 buck3: BUCK3 { 84 buck3: BUCK3 {
85 regulator-name 85 regulator-name = "BUCK3";
86 regulator-min- 86 regulator-min-microvolt = <800000>;
87 regulator-max- 87 regulator-max-microvolt = <1000000>;
88 regulator-boot 88 regulator-boot-on;
89 regulator-alwa 89 regulator-always-on;
90 }; 90 };
91 91
92 buck4: BUCK4 { 92 buck4: BUCK4 {
93 regulator-name 93 regulator-name = "BUCK4";
94 regulator-min- 94 regulator-min-microvolt = <3000000>;
95 regulator-max- 95 regulator-max-microvolt = <3600000>;
96 regulator-boot 96 regulator-boot-on;
97 regulator-alwa 97 regulator-always-on;
98 }; 98 };
99 99
100 buck5: BUCK5 { 100 buck5: BUCK5 {
101 regulator-name 101 regulator-name = "BUCK5";
102 regulator-min- 102 regulator-min-microvolt = <1650000>;
103 regulator-max- 103 regulator-max-microvolt = <1950000>;
104 regulator-boot 104 regulator-boot-on;
105 regulator-alwa 105 regulator-always-on;
106 }; 106 };
107 107
108 buck6: BUCK6 { 108 buck6: BUCK6 {
109 regulator-name 109 regulator-name = "BUCK6";
110 regulator-min- 110 regulator-min-microvolt = <1100000>;
111 regulator-max- 111 regulator-max-microvolt = <1200000>;
112 regulator-boot 112 regulator-boot-on;
113 regulator-alwa 113 regulator-always-on;
114 }; 114 };
115 115
116 ldo1: LDO1 { 116 ldo1: LDO1 {
117 regulator-name 117 regulator-name = "LDO1";
118 regulator-min- 118 regulator-min-microvolt = <1650000>;
119 regulator-max- 119 regulator-max-microvolt = <1950000>;
120 regulator-boot 120 regulator-boot-on;
121 regulator-alwa 121 regulator-always-on;
122 }; 122 };
123 123
124 ldo2: LDO2 { 124 ldo2: LDO2 {
125 regulator-name 125 regulator-name = "LDO2";
126 regulator-min- 126 regulator-min-microvolt = <800000>;
127 regulator-max- 127 regulator-max-microvolt = <945000>;
128 regulator-boot 128 regulator-boot-on;
129 regulator-alwa 129 regulator-always-on;
130 }; 130 };
131 131
132 ldo3: LDO3 { 132 ldo3: LDO3 {
133 regulator-name 133 regulator-name = "LDO3";
134 regulator-min- 134 regulator-min-microvolt = <1710000>;
135 regulator-max- 135 regulator-max-microvolt = <1890000>;
136 regulator-boot 136 regulator-boot-on;
137 regulator-alwa 137 regulator-always-on;
138 }; 138 };
139 139
140 ldo4: LDO4 { 140 ldo4: LDO4 {
141 regulator-name 141 regulator-name = "LDO4";
142 regulator-min- 142 regulator-min-microvolt = <810000>;
143 regulator-max- 143 regulator-max-microvolt = <945000>;
144 regulator-boot 144 regulator-boot-on;
145 regulator-alwa 145 regulator-always-on;
146 }; 146 };
147 147
148 ldo5: LDO5 { 148 ldo5: LDO5 {
149 regulator-name 149 regulator-name = "LDO5";
150 regulator-min- 150 regulator-min-microvolt = <1650000>;
151 regulator-max- 151 regulator-max-microvolt = <3600000>;
152 }; 152 };
153 }; 153 };
154 }; 154 };
155 }; 155 };
156 156
157 &uart2 { 157 &uart2 {
158 pinctrl-names = "default"; 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_uart2>; 159 pinctrl-0 = <&pinctrl_uart2>;
160 status = "okay"; 160 status = "okay";
161 }; 161 };
162 162
163 &usdhc3 { 163 &usdhc3 {
164 pinctrl-names = "default", "state_100m 164 pinctrl-names = "default", "state_100mhz", "state_200mhz";
165 pinctrl-0 = <&pinctrl_usdhc3>; 165 pinctrl-0 = <&pinctrl_usdhc3>;
166 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 166 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
167 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 167 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
168 bus-width = <8>; 168 bus-width = <8>;
169 non-removable; 169 non-removable;
170 status = "okay"; 170 status = "okay";
171 }; 171 };
172 172
173 &wdog1 { 173 &wdog1 {
174 pinctrl-names = "default"; 174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_wdog>; 175 pinctrl-0 = <&pinctrl_wdog>;
176 fsl,ext-reset-output; 176 fsl,ext-reset-output;
177 status = "okay"; 177 status = "okay";
178 }; 178 };
179 179
180 &iomuxc { 180 &iomuxc {
181 pinctrl_gpio_led: emtop-gpio-led-grp { 181 pinctrl_gpio_led: emtop-gpio-led-grp {
182 fsl,pins = < 182 fsl,pins = <
183 MX8MM_IOMUXC_NAND_READ 183 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
184 MX8MM_IOMUXC_SAI3_RXC_ 184 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
185 >; 185 >;
186 }; 186 };
187 187
188 pinctrl_i2c1: emtop-i2c1-grp { 188 pinctrl_i2c1: emtop-i2c1-grp {
189 fsl,pins = < 189 fsl,pins = <
190 MX8MM_IOMUXC_I2C1_SCL_ 190 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
191 MX8MM_IOMUXC_I2C1_SDA_ 191 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
192 >; 192 >;
193 }; 193 };
194 194
195 pinctrl_pmic: emtop-pmic-grp { 195 pinctrl_pmic: emtop-pmic-grp {
196 fsl,pins = < 196 fsl,pins = <
197 MX8MM_IOMUXC_GPIO1_IO0 197 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
198 >; 198 >;
199 }; 199 };
200 200
201 pinctrl_uart2: emtop-uart2-grp { 201 pinctrl_uart2: emtop-uart2-grp {
202 fsl,pins = < 202 fsl,pins = <
203 MX8MM_IOMUXC_UART2_RXD 203 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
204 MX8MM_IOMUXC_UART2_TXD 204 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
205 >; 205 >;
206 }; 206 };
207 207
208 pinctrl_usdhc3: emtop-usdhc3-grp { 208 pinctrl_usdhc3: emtop-usdhc3-grp {
209 fsl,pins = < 209 fsl,pins = <
210 MX8MM_IOMUXC_NAND_WE_B 210 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
211 MX8MM_IOMUXC_NAND_WP_B 211 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
212 MX8MM_IOMUXC_NAND_DATA 212 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
213 MX8MM_IOMUXC_NAND_DATA 213 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
214 MX8MM_IOMUXC_NAND_DATA 214 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
215 MX8MM_IOMUXC_NAND_DATA 215 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
216 MX8MM_IOMUXC_NAND_RE_B 216 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
217 MX8MM_IOMUXC_NAND_CE2_ 217 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
218 MX8MM_IOMUXC_NAND_CE3_ 218 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
219 MX8MM_IOMUXC_NAND_CLE_ 219 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
220 MX8MM_IOMUXC_NAND_CE1_ 220 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
221 >; 221 >;
222 }; 222 };
223 223
224 pinctrl_usdhc3_100mhz: emtop-usdhc3-10 224 pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp {
225 fsl,pins = < 225 fsl,pins = <
226 MX8MM_IOMUXC_NAND_WE_B 226 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
227 MX8MM_IOMUXC_NAND_WP_B 227 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
228 MX8MM_IOMUXC_NAND_DATA 228 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
229 MX8MM_IOMUXC_NAND_DATA 229 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
230 MX8MM_IOMUXC_NAND_DATA 230 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
231 MX8MM_IOMUXC_NAND_DATA 231 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
232 MX8MM_IOMUXC_NAND_RE_B 232 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
233 MX8MM_IOMUXC_NAND_CE2_ 233 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
234 MX8MM_IOMUXC_NAND_CE3_ 234 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
235 MX8MM_IOMUXC_NAND_CLE_ 235 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
236 MX8MM_IOMUXC_NAND_CE1_ 236 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
237 >; 237 >;
238 }; 238 };
239 239
240 pinctrl_usdhc3_200mhz: emtop-usdhc3-20 240 pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp {
241 fsl,pins = < 241 fsl,pins = <
242 MX8MM_IOMUXC_NAND_WE_B 242 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
243 MX8MM_IOMUXC_NAND_WP_B 243 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
244 MX8MM_IOMUXC_NAND_DATA 244 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
245 MX8MM_IOMUXC_NAND_DATA 245 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
246 MX8MM_IOMUXC_NAND_DATA 246 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
247 MX8MM_IOMUXC_NAND_DATA 247 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
248 MX8MM_IOMUXC_NAND_RE_B 248 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
249 MX8MM_IOMUXC_NAND_CE2_ 249 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
250 MX8MM_IOMUXC_NAND_CE3_ 250 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
251 MX8MM_IOMUXC_NAND_CLE_ 251 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
252 MX8MM_IOMUXC_NAND_CE1_ 252 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
253 >; 253 >;
254 }; 254 };
255 255
256 pinctrl_wdog: emtop-wdog-grp { 256 pinctrl_wdog: emtop-wdog-grp {
257 fsl,pins = < 257 fsl,pins = <
258 MX8MM_IOMUXC_GPIO1_IO0 258 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
259 >; 259 >;
260 }; 260 };
261 }; 261 };
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