1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019-2020 NXP !! 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/usb/pd.h> !! 8 #include "imx8mm.dtsi"
9 #include "imx8mm-evk.dtsi" <<
10 9
11 / { 10 / {
12 model = "FSL i.MX8MM EVK board"; 11 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,im 12 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14 13
15 aliases { !! 14 chosen {
16 spi0 = &flexspi; !! 15 stdout-path = &uart2;
17 }; 16 };
18 }; <<
19 17
20 &ddrc { !! 18 leds {
21 operating-points-v2 = <&ddrc_opp_table !! 19 compatible = "gpio-leds";
>> 20 pinctrl-names = "default";
>> 21 pinctrl-0 = <&pinctrl_gpio_led>;
>> 22
>> 23 status {
>> 24 label = "status";
>> 25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
>> 26 default-state = "on";
>> 27 };
>> 28 };
22 29
23 ddrc_opp_table: opp-table { !! 30 reg_usdhc2_vmmc: regulator-usdhc2 {
24 compatible = "operating-points !! 31 compatible = "regulator-fixed";
>> 32 pinctrl-names = "default";
>> 33 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
>> 34 regulator-name = "VSD_3V3";
>> 35 regulator-min-microvolt = <3300000>;
>> 36 regulator-max-microvolt = <3300000>;
>> 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> 38 enable-active-high;
>> 39 };
25 40
26 opp-25000000 { !! 41 wm8524: audio-codec {
27 opp-hz = /bits/ 64 <25 !! 42 #sound-dai-cells = <0>;
28 }; !! 43 compatible = "wlf,wm8524";
>> 44 pinctrl-names = "default";
>> 45 pinctrl-0 = <&pinctrl_gpio_wlf>;
>> 46 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
>> 47 };
29 48
30 opp-100000000 { !! 49 sound-wm8524 {
31 opp-hz = /bits/ 64 <10 !! 50 compatible = "simple-audio-card";
>> 51 simple-audio-card,name = "wm8524-audio";
>> 52 simple-audio-card,format = "i2s";
>> 53 simple-audio-card,frame-master = <&cpudai>;
>> 54 simple-audio-card,bitclock-master = <&cpudai>;
>> 55 simple-audio-card,widgets =
>> 56 "Line", "Left Line Out Jack",
>> 57 "Line", "Right Line Out Jack";
>> 58 simple-audio-card,routing =
>> 59 "Left Line Out Jack", "LINEVOUTL",
>> 60 "Right Line Out Jack", "LINEVOUTR";
>> 61
>> 62 cpudai: simple-audio-card,cpu {
>> 63 sound-dai = <&sai3>;
32 }; 64 };
33 65
34 opp-750000000 { !! 66 simple-audio-card,codec {
35 opp-hz = /bits/ 64 <75 !! 67 sound-dai = <&wm8524>;
>> 68 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
36 }; 69 };
37 }; 70 };
38 }; 71 };
39 72
40 &flexspi { !! 73 &A53_0 {
>> 74 cpu-supply = <&buck2_reg>;
>> 75 };
>> 76
>> 77 &fec1 {
41 pinctrl-names = "default"; 78 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_flexspi>; !! 79 pinctrl-0 = <&pinctrl_fec1>;
>> 80 phy-mode = "rgmii-id";
>> 81 phy-handle = <ðphy0>;
>> 82 fsl,magic-packet;
43 status = "okay"; 83 status = "okay";
44 84
45 flash@0 { !! 85 mdio {
46 reg = <0>; <<
47 #address-cells = <1>; 86 #address-cells = <1>;
48 #size-cells = <1>; !! 87 #size-cells = <0>;
49 compatible = "jedec,spi-nor"; !! 88
50 spi-max-frequency = <80000000> !! 89 ethphy0: ethernet-phy@0 {
51 spi-tx-bus-width = <1>; !! 90 compatible = "ethernet-phy-ieee802.3-c22";
52 spi-rx-bus-width = <4>; !! 91 reg = <0>;
>> 92 at803x,led-act-blind-workaround;
>> 93 at803x,eee-okay;
>> 94 at803x,vddio-1p8v;
>> 95 };
53 }; 96 };
54 }; 97 };
55 98
>> 99 &sai3 {
>> 100 pinctrl-names = "default";
>> 101 pinctrl-0 = <&pinctrl_sai3>;
>> 102 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
>> 103 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
>> 104 assigned-clock-rates = <24576000>;
>> 105 status = "okay";
>> 106 };
>> 107
>> 108 &snvs_pwrkey {
>> 109 status = "okay";
>> 110 };
>> 111
>> 112 &uart2 { /* console */
>> 113 pinctrl-names = "default";
>> 114 pinctrl-0 = <&pinctrl_uart2>;
>> 115 status = "okay";
>> 116 };
>> 117
>> 118 &usdhc2 {
>> 119 pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> 120 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>> 121 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>> 122 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>> 123 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
>> 124 bus-width = <4>;
>> 125 vmmc-supply = <®_usdhc2_vmmc>;
>> 126 status = "okay";
>> 127 };
>> 128
56 &usdhc3 { 129 &usdhc3 {
57 assigned-clocks = <&clk IMX8MM_CLK_USD <<
58 assigned-clock-rates = <400000000>; <<
59 pinctrl-names = "default", "state_100m 130 pinctrl-names = "default", "state_100mhz", "state_200mhz";
60 pinctrl-0 = <&pinctrl_usdhc3>; 131 pinctrl-0 = <&pinctrl_usdhc3>;
61 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 132 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
62 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 133 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
63 bus-width = <8>; 134 bus-width = <8>;
64 non-removable; 135 non-removable;
65 status = "okay"; 136 status = "okay";
66 }; 137 };
67 138
>> 139 &wdog1 {
>> 140 pinctrl-names = "default";
>> 141 pinctrl-0 = <&pinctrl_wdog>;
>> 142 fsl,ext-reset-output;
>> 143 status = "okay";
>> 144 };
>> 145
>> 146 &i2c1 {
>> 147 clock-frequency = <400000>;
>> 148 pinctrl-names = "default";
>> 149 pinctrl-0 = <&pinctrl_i2c1>;
>> 150 status = "okay";
>> 151
>> 152 pmic@4b {
>> 153 compatible = "rohm,bd71847";
>> 154 reg = <0x4b>;
>> 155 pinctrl-0 = <&pinctrl_pmic>;
>> 156 interrupt-parent = <&gpio1>;
>> 157 interrupts = <3 GPIO_ACTIVE_LOW>;
>> 158 rohm,reset-snvs-powered;
>> 159
>> 160 regulators {
>> 161 buck1_reg: BUCK1 {
>> 162 regulator-name = "BUCK1";
>> 163 regulator-min-microvolt = <700000>;
>> 164 regulator-max-microvolt = <1300000>;
>> 165 regulator-boot-on;
>> 166 regulator-always-on;
>> 167 regulator-ramp-delay = <1250>;
>> 168 };
>> 169
>> 170 buck2_reg: BUCK2 {
>> 171 regulator-name = "BUCK2";
>> 172 regulator-min-microvolt = <700000>;
>> 173 regulator-max-microvolt = <1300000>;
>> 174 regulator-boot-on;
>> 175 regulator-always-on;
>> 176 regulator-ramp-delay = <1250>;
>> 177 rohm,dvs-run-voltage = <1000000>;
>> 178 rohm,dvs-idle-voltage = <900000>;
>> 179 };
>> 180
>> 181 buck3_reg: BUCK3 {
>> 182 // BUCK5 in datasheet
>> 183 regulator-name = "BUCK3";
>> 184 regulator-min-microvolt = <700000>;
>> 185 regulator-max-microvolt = <1350000>;
>> 186 regulator-boot-on;
>> 187 regulator-always-on;
>> 188 };
>> 189
>> 190 buck4_reg: BUCK4 {
>> 191 // BUCK6 in datasheet
>> 192 regulator-name = "BUCK4";
>> 193 regulator-min-microvolt = <3000000>;
>> 194 regulator-max-microvolt = <3300000>;
>> 195 regulator-boot-on;
>> 196 regulator-always-on;
>> 197 };
>> 198
>> 199 buck5_reg: BUCK5 {
>> 200 // BUCK7 in datasheet
>> 201 regulator-name = "BUCK5";
>> 202 regulator-min-microvolt = <1605000>;
>> 203 regulator-max-microvolt = <1995000>;
>> 204 regulator-boot-on;
>> 205 regulator-always-on;
>> 206 };
>> 207
>> 208 buck6_reg: BUCK6 {
>> 209 // BUCK8 in datasheet
>> 210 regulator-name = "BUCK6";
>> 211 regulator-min-microvolt = <800000>;
>> 212 regulator-max-microvolt = <1400000>;
>> 213 regulator-boot-on;
>> 214 regulator-always-on;
>> 215 };
>> 216
>> 217 ldo1_reg: LDO1 {
>> 218 regulator-name = "LDO1";
>> 219 regulator-min-microvolt = <3000000>;
>> 220 regulator-max-microvolt = <3300000>;
>> 221 regulator-boot-on;
>> 222 regulator-always-on;
>> 223 };
>> 224
>> 225 ldo2_reg: LDO2 {
>> 226 regulator-name = "LDO2";
>> 227 regulator-min-microvolt = <900000>;
>> 228 regulator-max-microvolt = <900000>;
>> 229 regulator-boot-on;
>> 230 regulator-always-on;
>> 231 };
>> 232
>> 233 ldo3_reg: LDO3 {
>> 234 regulator-name = "LDO3";
>> 235 regulator-min-microvolt = <1800000>;
>> 236 regulator-max-microvolt = <3300000>;
>> 237 regulator-boot-on;
>> 238 regulator-always-on;
>> 239 };
>> 240
>> 241 ldo4_reg: LDO4 {
>> 242 regulator-name = "LDO4";
>> 243 regulator-min-microvolt = <900000>;
>> 244 regulator-max-microvolt = <1800000>;
>> 245 regulator-boot-on;
>> 246 regulator-always-on;
>> 247 };
>> 248
>> 249 ldo6_reg: LDO6 {
>> 250 regulator-name = "LDO6";
>> 251 regulator-min-microvolt = <900000>;
>> 252 regulator-max-microvolt = <1800000>;
>> 253 regulator-boot-on;
>> 254 regulator-always-on;
>> 255 };
>> 256 };
>> 257 };
>> 258 };
>> 259
68 &iomuxc { 260 &iomuxc {
69 pinctrl_flexspi: flexspigrp { !! 261 pinctrl-names = "default";
>> 262
>> 263 pinctrl_fec1: fec1grp {
70 fsl,pins = < 264 fsl,pins = <
71 MX8MM_IOMUXC_NAND_ALE_ !! 265 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
72 MX8MM_IOMUXC_NAND_CE0_ !! 266 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
73 MX8MM_IOMUXC_NAND_DATA !! 267 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
74 MX8MM_IOMUXC_NAND_DATA !! 268 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
75 MX8MM_IOMUXC_NAND_DATA !! 269 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
76 MX8MM_IOMUXC_NAND_DATA !! 270 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> 271 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> 272 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> 273 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> 274 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> 275 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> 276 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> 277 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> 278 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> 279 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>> 280 >;
>> 281 };
>> 282
>> 283 pinctrl_gpio_led: gpioledgrp {
>> 284 fsl,pins = <
>> 285 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>> 286 >;
>> 287 };
>> 288
>> 289 pinctrl_gpio_wlf: gpiowlfgrp {
>> 290 fsl,pins = <
>> 291 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>> 292 >;
>> 293 };
>> 294
>> 295 pinctrl_i2c1: i2c1grp {
>> 296 fsl,pins = <
>> 297 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
>> 298 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>> 299 >;
>> 300 };
>> 301
>> 302 pinctrl_pmic: pmicirq {
>> 303 fsl,pins = <
>> 304 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>> 305 >;
>> 306 };
>> 307
>> 308 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
>> 309 fsl,pins = <
>> 310 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> 311 >;
>> 312 };
>> 313
>> 314 pinctrl_sai3: sai3grp {
>> 315 fsl,pins = <
>> 316 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
>> 317 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
>> 318 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
>> 319 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>> 320 >;
>> 321 };
>> 322
>> 323 pinctrl_uart2: uart2grp {
>> 324 fsl,pins = <
>> 325 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
>> 326 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>> 327 >;
>> 328 };
>> 329
>> 330 pinctrl_usdhc2_gpio: usdhc2grpgpio {
>> 331 fsl,pins = <
>> 332 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>> 333 >;
>> 334 };
>> 335
>> 336 pinctrl_usdhc2: usdhc2grp {
>> 337 fsl,pins = <
>> 338 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
>> 339 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
>> 340 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
>> 341 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
>> 342 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
>> 343 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>> 344 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 345 >;
>> 346 };
>> 347
>> 348 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> 349 fsl,pins = <
>> 350 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
>> 351 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
>> 352 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
>> 353 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
>> 354 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
>> 355 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>> 356 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 357 >;
>> 358 };
>> 359
>> 360 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> 361 fsl,pins = <
>> 362 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
>> 363 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
>> 364 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
>> 365 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
>> 366 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
>> 367 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>> 368 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
77 >; 369 >;
78 }; 370 };
79 371
80 pinctrl_usdhc3: usdhc3grp { 372 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = < 373 fsl,pins = <
82 MX8MM_IOMUXC_NAND_WE_B !! 374 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
83 MX8MM_IOMUXC_NAND_WP_B !! 375 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
84 MX8MM_IOMUXC_NAND_DATA !! 376 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
85 MX8MM_IOMUXC_NAND_DATA !! 377 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
86 MX8MM_IOMUXC_NAND_DATA !! 378 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
87 MX8MM_IOMUXC_NAND_DATA !! 379 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
88 MX8MM_IOMUXC_NAND_DATA !! 380 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
89 MX8MM_IOMUXC_NAND_RE_B !! 381 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
90 MX8MM_IOMUXC_NAND_CE2_ !! 382 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
91 MX8MM_IOMUXC_NAND_CE3_ !! 383 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
92 MX8MM_IOMUXC_NAND_CLE_ !! 384 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
93 MX8MM_IOMUXC_NAND_CE1_ <<
94 >; 385 >;
95 }; 386 };
96 387
97 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr !! 388 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
98 fsl,pins = < !! 389 fsl,pins = <
99 MX8MM_IOMUXC_NAND_WE_B !! 390 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
100 MX8MM_IOMUXC_NAND_WP_B !! 391 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
101 MX8MM_IOMUXC_NAND_DATA !! 392 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
102 MX8MM_IOMUXC_NAND_DATA !! 393 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
103 MX8MM_IOMUXC_NAND_DATA !! 394 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
104 MX8MM_IOMUXC_NAND_DATA !! 395 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
105 MX8MM_IOMUXC_NAND_RE_B !! 396 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
106 MX8MM_IOMUXC_NAND_CE2_ !! 397 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
107 MX8MM_IOMUXC_NAND_CE3_ !! 398 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
108 MX8MM_IOMUXC_NAND_CLE_ !! 399 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
109 MX8MM_IOMUXC_NAND_CE1_ !! 400 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
110 >; 401 >;
111 }; 402 };
112 403
113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr !! 404 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
114 fsl,pins = < !! 405 fsl,pins = <
115 MX8MM_IOMUXC_NAND_WE_B !! 406 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
116 MX8MM_IOMUXC_NAND_WP_B !! 407 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
117 MX8MM_IOMUXC_NAND_DATA !! 408 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
118 MX8MM_IOMUXC_NAND_DATA !! 409 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
119 MX8MM_IOMUXC_NAND_DATA !! 410 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
120 MX8MM_IOMUXC_NAND_DATA !! 411 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
121 MX8MM_IOMUXC_NAND_RE_B !! 412 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
122 MX8MM_IOMUXC_NAND_CE2_ !! 413 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
123 MX8MM_IOMUXC_NAND_CE3_ !! 414 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
124 MX8MM_IOMUXC_NAND_CLE_ !! 415 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
125 MX8MM_IOMUXC_NAND_CE1_ !! 416 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>> 417 >;
>> 418 };
>> 419
>> 420 pinctrl_wdog: wdoggrp {
>> 421 fsl,pins = <
>> 422 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
126 >; 423 >;
127 }; 424 };
128 }; 425 };
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