1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019-2020 NXP !! 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/usb/pd.h> 8 #include <dt-bindings/usb/pd.h>
9 #include "imx8mm-evk.dtsi" !! 9 #include "imx8mm.dtsi"
10 10
11 / { 11 / {
12 model = "FSL i.MX8MM EVK board"; 12 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,im 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14 14
15 aliases { !! 15 chosen {
16 spi0 = &flexspi; !! 16 stdout-path = &uart2;
17 }; 17 };
18 }; <<
19 18
20 &ddrc { !! 19 leds {
21 operating-points-v2 = <&ddrc_opp_table !! 20 compatible = "gpio-leds";
>> 21 pinctrl-names = "default";
>> 22 pinctrl-0 = <&pinctrl_gpio_led>;
>> 23
>> 24 status {
>> 25 label = "status";
>> 26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
>> 27 default-state = "on";
>> 28 };
>> 29 };
22 30
23 ddrc_opp_table: opp-table { !! 31 reg_usdhc2_vmmc: regulator-usdhc2 {
24 compatible = "operating-points !! 32 compatible = "regulator-fixed";
>> 33 pinctrl-names = "default";
>> 34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
>> 35 regulator-name = "VSD_3V3";
>> 36 regulator-min-microvolt = <3300000>;
>> 37 regulator-max-microvolt = <3300000>;
>> 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> 39 enable-active-high;
>> 40 };
25 41
26 opp-25000000 { !! 42 wm8524: audio-codec {
27 opp-hz = /bits/ 64 <25 !! 43 #sound-dai-cells = <0>;
28 }; !! 44 compatible = "wlf,wm8524";
>> 45 pinctrl-names = "default";
>> 46 pinctrl-0 = <&pinctrl_gpio_wlf>;
>> 47 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
>> 48 };
29 49
30 opp-100000000 { !! 50 sound-wm8524 {
31 opp-hz = /bits/ 64 <10 !! 51 compatible = "simple-audio-card";
>> 52 simple-audio-card,name = "wm8524-audio";
>> 53 simple-audio-card,format = "i2s";
>> 54 simple-audio-card,frame-master = <&cpudai>;
>> 55 simple-audio-card,bitclock-master = <&cpudai>;
>> 56 simple-audio-card,widgets =
>> 57 "Line", "Left Line Out Jack",
>> 58 "Line", "Right Line Out Jack";
>> 59 simple-audio-card,routing =
>> 60 "Left Line Out Jack", "LINEVOUTL",
>> 61 "Right Line Out Jack", "LINEVOUTR";
>> 62
>> 63 cpudai: simple-audio-card,cpu {
>> 64 sound-dai = <&sai3>;
>> 65 dai-tdm-slot-num = <2>;
>> 66 dai-tdm-slot-width = <32>;
32 }; 67 };
33 68
34 opp-750000000 { !! 69 simple-audio-card,codec {
35 opp-hz = /bits/ 64 <75 !! 70 sound-dai = <&wm8524>;
>> 71 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
36 }; 72 };
37 }; 73 };
38 }; 74 };
39 75
40 &flexspi { !! 76 &A53_0 {
>> 77 cpu-supply = <&buck2_reg>;
>> 78 };
>> 79
>> 80 &fec1 {
41 pinctrl-names = "default"; 81 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_flexspi>; !! 82 pinctrl-0 = <&pinctrl_fec1>;
>> 83 phy-mode = "rgmii-id";
>> 84 phy-handle = <ðphy0>;
>> 85 fsl,magic-packet;
43 status = "okay"; 86 status = "okay";
44 87
45 flash@0 { !! 88 mdio {
46 reg = <0>; <<
47 #address-cells = <1>; 89 #address-cells = <1>;
48 #size-cells = <1>; !! 90 #size-cells = <0>;
49 compatible = "jedec,spi-nor"; !! 91
50 spi-max-frequency = <80000000> !! 92 ethphy0: ethernet-phy@0 {
51 spi-tx-bus-width = <1>; !! 93 compatible = "ethernet-phy-ieee802.3-c22";
52 spi-rx-bus-width = <4>; !! 94 reg = <0>;
>> 95 };
>> 96 };
>> 97 };
>> 98
>> 99 &sai3 {
>> 100 pinctrl-names = "default";
>> 101 pinctrl-0 = <&pinctrl_sai3>;
>> 102 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
>> 103 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
>> 104 assigned-clock-rates = <24576000>;
>> 105 status = "okay";
>> 106 };
>> 107
>> 108 &snvs_pwrkey {
>> 109 status = "okay";
>> 110 };
>> 111
>> 112 &uart2 { /* console */
>> 113 pinctrl-names = "default";
>> 114 pinctrl-0 = <&pinctrl_uart2>;
>> 115 status = "okay";
>> 116 };
>> 117
>> 118 &usbotg1 {
>> 119 dr_mode = "otg";
>> 120 hnp-disable;
>> 121 srp-disable;
>> 122 adp-disable;
>> 123 usb-role-switch;
>> 124 status = "okay";
>> 125
>> 126 port {
>> 127 usb1_drd_sw: endpoint {
>> 128 remote-endpoint = <&typec1_dr_sw>;
>> 129 };
53 }; 130 };
54 }; 131 };
55 132
>> 133 &usdhc2 {
>> 134 pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> 135 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>> 136 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>> 137 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>> 138 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
>> 139 bus-width = <4>;
>> 140 vmmc-supply = <®_usdhc2_vmmc>;
>> 141 status = "okay";
>> 142 };
>> 143
56 &usdhc3 { 144 &usdhc3 {
57 assigned-clocks = <&clk IMX8MM_CLK_USD <<
58 assigned-clock-rates = <400000000>; <<
59 pinctrl-names = "default", "state_100m 145 pinctrl-names = "default", "state_100mhz", "state_200mhz";
60 pinctrl-0 = <&pinctrl_usdhc3>; 146 pinctrl-0 = <&pinctrl_usdhc3>;
61 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 147 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
62 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 148 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
63 bus-width = <8>; 149 bus-width = <8>;
64 non-removable; 150 non-removable;
65 status = "okay"; 151 status = "okay";
66 }; 152 };
67 153
>> 154 &wdog1 {
>> 155 pinctrl-names = "default";
>> 156 pinctrl-0 = <&pinctrl_wdog>;
>> 157 fsl,ext-reset-output;
>> 158 status = "okay";
>> 159 };
>> 160
>> 161 &i2c1 {
>> 162 clock-frequency = <400000>;
>> 163 pinctrl-names = "default";
>> 164 pinctrl-0 = <&pinctrl_i2c1>;
>> 165 status = "okay";
>> 166
>> 167 pmic@4b {
>> 168 compatible = "rohm,bd71847";
>> 169 reg = <0x4b>;
>> 170 pinctrl-0 = <&pinctrl_pmic>;
>> 171 interrupt-parent = <&gpio1>;
>> 172 interrupts = <3 GPIO_ACTIVE_LOW>;
>> 173 rohm,reset-snvs-powered;
>> 174
>> 175 regulators {
>> 176 buck1_reg: BUCK1 {
>> 177 regulator-name = "BUCK1";
>> 178 regulator-min-microvolt = <700000>;
>> 179 regulator-max-microvolt = <1300000>;
>> 180 regulator-boot-on;
>> 181 regulator-always-on;
>> 182 regulator-ramp-delay = <1250>;
>> 183 };
>> 184
>> 185 buck2_reg: BUCK2 {
>> 186 regulator-name = "BUCK2";
>> 187 regulator-min-microvolt = <700000>;
>> 188 regulator-max-microvolt = <1300000>;
>> 189 regulator-boot-on;
>> 190 regulator-always-on;
>> 191 regulator-ramp-delay = <1250>;
>> 192 rohm,dvs-run-voltage = <1000000>;
>> 193 rohm,dvs-idle-voltage = <900000>;
>> 194 };
>> 195
>> 196 buck3_reg: BUCK3 {
>> 197 // BUCK5 in datasheet
>> 198 regulator-name = "BUCK3";
>> 199 regulator-min-microvolt = <700000>;
>> 200 regulator-max-microvolt = <1350000>;
>> 201 regulator-boot-on;
>> 202 regulator-always-on;
>> 203 };
>> 204
>> 205 buck4_reg: BUCK4 {
>> 206 // BUCK6 in datasheet
>> 207 regulator-name = "BUCK4";
>> 208 regulator-min-microvolt = <3000000>;
>> 209 regulator-max-microvolt = <3300000>;
>> 210 regulator-boot-on;
>> 211 regulator-always-on;
>> 212 };
>> 213
>> 214 buck5_reg: BUCK5 {
>> 215 // BUCK7 in datasheet
>> 216 regulator-name = "BUCK5";
>> 217 regulator-min-microvolt = <1605000>;
>> 218 regulator-max-microvolt = <1995000>;
>> 219 regulator-boot-on;
>> 220 regulator-always-on;
>> 221 };
>> 222
>> 223 buck6_reg: BUCK6 {
>> 224 // BUCK8 in datasheet
>> 225 regulator-name = "BUCK6";
>> 226 regulator-min-microvolt = <800000>;
>> 227 regulator-max-microvolt = <1400000>;
>> 228 regulator-boot-on;
>> 229 regulator-always-on;
>> 230 };
>> 231
>> 232 ldo1_reg: LDO1 {
>> 233 regulator-name = "LDO1";
>> 234 regulator-min-microvolt = <1600000>;
>> 235 regulator-max-microvolt = <3300000>;
>> 236 regulator-boot-on;
>> 237 regulator-always-on;
>> 238 };
>> 239
>> 240 ldo2_reg: LDO2 {
>> 241 regulator-name = "LDO2";
>> 242 regulator-min-microvolt = <800000>;
>> 243 regulator-max-microvolt = <900000>;
>> 244 regulator-boot-on;
>> 245 regulator-always-on;
>> 246 };
>> 247
>> 248 ldo3_reg: LDO3 {
>> 249 regulator-name = "LDO3";
>> 250 regulator-min-microvolt = <1800000>;
>> 251 regulator-max-microvolt = <3300000>;
>> 252 regulator-boot-on;
>> 253 regulator-always-on;
>> 254 };
>> 255
>> 256 ldo4_reg: LDO4 {
>> 257 regulator-name = "LDO4";
>> 258 regulator-min-microvolt = <900000>;
>> 259 regulator-max-microvolt = <1800000>;
>> 260 regulator-boot-on;
>> 261 regulator-always-on;
>> 262 };
>> 263
>> 264 ldo6_reg: LDO6 {
>> 265 regulator-name = "LDO6";
>> 266 regulator-min-microvolt = <900000>;
>> 267 regulator-max-microvolt = <1800000>;
>> 268 regulator-boot-on;
>> 269 regulator-always-on;
>> 270 };
>> 271 };
>> 272 };
>> 273 };
>> 274
>> 275 &i2c2 {
>> 276 clock-frequency = <400000>;
>> 277 pinctrl-names = "default";
>> 278 pinctrl-0 = <&pinctrl_i2c2>;
>> 279 status = "okay";
>> 280
>> 281 ptn5110: tcpc@50 {
>> 282 compatible = "nxp,ptn5110";
>> 283 pinctrl-names = "default";
>> 284 pinctrl-0 = <&pinctrl_typec1>;
>> 285 reg = <0x50>;
>> 286 interrupt-parent = <&gpio2>;
>> 287 interrupts = <11 8>;
>> 288 status = "okay";
>> 289
>> 290 port {
>> 291 typec1_dr_sw: endpoint {
>> 292 remote-endpoint = <&usb1_drd_sw>;
>> 293 };
>> 294 };
>> 295
>> 296 typec1_con: connector {
>> 297 compatible = "usb-c-connector";
>> 298 label = "USB-C";
>> 299 power-role = "dual";
>> 300 data-role = "dual";
>> 301 try-power-role = "sink";
>> 302 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
>> 303 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
>> 304 PDO_VAR(5000, 20000, 3000)>;
>> 305 op-sink-microwatt = <15000000>;
>> 306 self-powered;
>> 307 };
>> 308 };
>> 309 };
>> 310
68 &iomuxc { 311 &iomuxc {
69 pinctrl_flexspi: flexspigrp { !! 312 pinctrl-names = "default";
>> 313
>> 314 pinctrl_fec1: fec1grp {
70 fsl,pins = < 315 fsl,pins = <
71 MX8MM_IOMUXC_NAND_ALE_ !! 316 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
72 MX8MM_IOMUXC_NAND_CE0_ !! 317 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
73 MX8MM_IOMUXC_NAND_DATA !! 318 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
74 MX8MM_IOMUXC_NAND_DATA !! 319 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
75 MX8MM_IOMUXC_NAND_DATA !! 320 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
76 MX8MM_IOMUXC_NAND_DATA !! 321 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> 322 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> 323 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> 324 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> 325 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> 326 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> 327 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> 328 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> 329 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> 330 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>> 331 >;
>> 332 };
>> 333
>> 334 pinctrl_gpio_led: gpioledgrp {
>> 335 fsl,pins = <
>> 336 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>> 337 >;
>> 338 };
>> 339
>> 340 pinctrl_gpio_wlf: gpiowlfgrp {
>> 341 fsl,pins = <
>> 342 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>> 343 >;
>> 344 };
>> 345
>> 346 pinctrl_i2c1: i2c1grp {
>> 347 fsl,pins = <
>> 348 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
>> 349 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>> 350 >;
>> 351 };
>> 352
>> 353 pinctrl_i2c2: i2c2grp {
>> 354 fsl,pins = <
>> 355 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
>> 356 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>> 357 >;
>> 358 };
>> 359
>> 360 pinctrl_pmic: pmicirq {
>> 361 fsl,pins = <
>> 362 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>> 363 >;
>> 364 };
>> 365
>> 366 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
>> 367 fsl,pins = <
>> 368 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> 369 >;
>> 370 };
>> 371
>> 372 pinctrl_sai3: sai3grp {
>> 373 fsl,pins = <
>> 374 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
>> 375 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
>> 376 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
>> 377 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>> 378 >;
>> 379 };
>> 380
>> 381 pinctrl_typec1: typec1grp {
>> 382 fsl,pins = <
>> 383 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>> 384 >;
>> 385 };
>> 386
>> 387 pinctrl_uart2: uart2grp {
>> 388 fsl,pins = <
>> 389 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
>> 390 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>> 391 >;
>> 392 };
>> 393
>> 394 pinctrl_usdhc2_gpio: usdhc2grpgpio {
>> 395 fsl,pins = <
>> 396 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>> 397 >;
>> 398 };
>> 399
>> 400 pinctrl_usdhc2: usdhc2grp {
>> 401 fsl,pins = <
>> 402 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
>> 403 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
>> 404 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
>> 405 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
>> 406 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
>> 407 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>> 408 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 409 >;
>> 410 };
>> 411
>> 412 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> 413 fsl,pins = <
>> 414 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
>> 415 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
>> 416 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
>> 417 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
>> 418 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
>> 419 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>> 420 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 421 >;
>> 422 };
>> 423
>> 424 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> 425 fsl,pins = <
>> 426 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
>> 427 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
>> 428 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
>> 429 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
>> 430 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
>> 431 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>> 432 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
77 >; 433 >;
78 }; 434 };
79 435
80 pinctrl_usdhc3: usdhc3grp { 436 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = < 437 fsl,pins = <
82 MX8MM_IOMUXC_NAND_WE_B !! 438 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
83 MX8MM_IOMUXC_NAND_WP_B !! 439 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
84 MX8MM_IOMUXC_NAND_DATA !! 440 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
85 MX8MM_IOMUXC_NAND_DATA !! 441 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
86 MX8MM_IOMUXC_NAND_DATA !! 442 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
87 MX8MM_IOMUXC_NAND_DATA !! 443 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
88 MX8MM_IOMUXC_NAND_DATA !! 444 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
89 MX8MM_IOMUXC_NAND_RE_B !! 445 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
90 MX8MM_IOMUXC_NAND_CE2_ !! 446 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
91 MX8MM_IOMUXC_NAND_CE3_ !! 447 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
92 MX8MM_IOMUXC_NAND_CLE_ !! 448 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
93 MX8MM_IOMUXC_NAND_CE1_ <<
94 >; 449 >;
95 }; 450 };
96 451
97 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr !! 452 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
98 fsl,pins = < !! 453 fsl,pins = <
99 MX8MM_IOMUXC_NAND_WE_B !! 454 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
100 MX8MM_IOMUXC_NAND_WP_B !! 455 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
101 MX8MM_IOMUXC_NAND_DATA !! 456 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
102 MX8MM_IOMUXC_NAND_DATA !! 457 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
103 MX8MM_IOMUXC_NAND_DATA !! 458 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
104 MX8MM_IOMUXC_NAND_DATA !! 459 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
105 MX8MM_IOMUXC_NAND_RE_B !! 460 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
106 MX8MM_IOMUXC_NAND_CE2_ !! 461 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
107 MX8MM_IOMUXC_NAND_CE3_ !! 462 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
108 MX8MM_IOMUXC_NAND_CLE_ !! 463 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
109 MX8MM_IOMUXC_NAND_CE1_ !! 464 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>> 465 >;
>> 466 };
>> 467
>> 468 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
>> 469 fsl,pins = <
>> 470 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
>> 471 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>> 472 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
>> 473 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
>> 474 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
>> 475 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
>> 476 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
>> 477 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
>> 478 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
>> 479 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
>> 480 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
110 >; 481 >;
111 }; 482 };
112 483
113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr !! 484 pinctrl_wdog: wdoggrp {
114 fsl,pins = < !! 485 fsl,pins = <
115 MX8MM_IOMUXC_NAND_WE_B !! 486 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
116 MX8MM_IOMUXC_NAND_WP_B <<
117 MX8MM_IOMUXC_NAND_DATA <<
118 MX8MM_IOMUXC_NAND_DATA <<
119 MX8MM_IOMUXC_NAND_DATA <<
120 MX8MM_IOMUXC_NAND_DATA <<
121 MX8MM_IOMUXC_NAND_RE_B <<
122 MX8MM_IOMUXC_NAND_CE2_ <<
123 MX8MM_IOMUXC_NAND_CE3_ <<
124 MX8MM_IOMUXC_NAND_CLE_ <<
125 MX8MM_IOMUXC_NAND_CE1_ <<
126 >; 487 >;
127 }; 488 };
128 }; 489 };
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