1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019-2020 NXP !! 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/usb/pd.h> 8 #include <dt-bindings/usb/pd.h>
9 #include "imx8mm-evk.dtsi" !! 9 #include "imx8mm.dtsi"
10 10
11 / { 11 / {
12 model = "FSL i.MX8MM EVK board"; 12 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,im 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14 14
15 aliases { !! 15 chosen {
16 spi0 = &flexspi; !! 16 stdout-path = &uart2;
17 }; 17 };
>> 18
>> 19 memory@40000000 {
>> 20 device_type = "memory";
>> 21 reg = <0x0 0x40000000 0 0x80000000>;
>> 22 };
>> 23
>> 24 leds {
>> 25 compatible = "gpio-leds";
>> 26 pinctrl-names = "default";
>> 27 pinctrl-0 = <&pinctrl_gpio_led>;
>> 28
>> 29 status {
>> 30 label = "status";
>> 31 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
>> 32 default-state = "on";
>> 33 };
>> 34 };
>> 35
>> 36 reg_usdhc2_vmmc: regulator-usdhc2 {
>> 37 compatible = "regulator-fixed";
>> 38 pinctrl-names = "default";
>> 39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
>> 40 regulator-name = "VSD_3V3";
>> 41 regulator-min-microvolt = <3300000>;
>> 42 regulator-max-microvolt = <3300000>;
>> 43 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> 44 enable-active-high;
>> 45 };
>> 46
>> 47 wm8524: audio-codec {
>> 48 #sound-dai-cells = <0>;
>> 49 compatible = "wlf,wm8524";
>> 50 pinctrl-names = "default";
>> 51 pinctrl-0 = <&pinctrl_gpio_wlf>;
>> 52 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
>> 53 };
>> 54
>> 55 sound-wm8524 {
>> 56 compatible = "simple-audio-card";
>> 57 simple-audio-card,name = "wm8524-audio";
>> 58 simple-audio-card,format = "i2s";
>> 59 simple-audio-card,frame-master = <&cpudai>;
>> 60 simple-audio-card,bitclock-master = <&cpudai>;
>> 61 simple-audio-card,widgets =
>> 62 "Line", "Left Line Out Jack",
>> 63 "Line", "Right Line Out Jack";
>> 64 simple-audio-card,routing =
>> 65 "Left Line Out Jack", "LINEVOUTL",
>> 66 "Right Line Out Jack", "LINEVOUTR";
>> 67
>> 68 cpudai: simple-audio-card,cpu {
>> 69 sound-dai = <&sai3>;
>> 70 dai-tdm-slot-num = <2>;
>> 71 dai-tdm-slot-width = <32>;
>> 72 };
>> 73
>> 74 simple-audio-card,codec {
>> 75 sound-dai = <&wm8524>;
>> 76 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
>> 77 };
>> 78 };
>> 79 };
>> 80
>> 81 &A53_0 {
>> 82 cpu-supply = <&buck2_reg>;
>> 83 };
>> 84
>> 85 &A53_1 {
>> 86 cpu-supply = <&buck2_reg>;
>> 87 };
>> 88
>> 89 &A53_2 {
>> 90 cpu-supply = <&buck2_reg>;
>> 91 };
>> 92
>> 93 &A53_3 {
>> 94 cpu-supply = <&buck2_reg>;
18 }; 95 };
19 96
20 &ddrc { 97 &ddrc {
21 operating-points-v2 = <&ddrc_opp_table 98 operating-points-v2 = <&ddrc_opp_table>;
22 99
23 ddrc_opp_table: opp-table { 100 ddrc_opp_table: opp-table {
24 compatible = "operating-points 101 compatible = "operating-points-v2";
25 102
26 opp-25000000 { !! 103 opp-25M {
27 opp-hz = /bits/ 64 <25 104 opp-hz = /bits/ 64 <25000000>;
28 }; 105 };
29 106
30 opp-100000000 { !! 107 opp-100M {
31 opp-hz = /bits/ 64 <10 108 opp-hz = /bits/ 64 <100000000>;
32 }; 109 };
33 110
34 opp-750000000 { !! 111 opp-750M {
35 opp-hz = /bits/ 64 <75 112 opp-hz = /bits/ 64 <750000000>;
36 }; 113 };
37 }; 114 };
38 }; 115 };
39 116
40 &flexspi { !! 117 &fec1 {
41 pinctrl-names = "default"; 118 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_flexspi>; !! 119 pinctrl-0 = <&pinctrl_fec1>;
>> 120 phy-mode = "rgmii-id";
>> 121 phy-handle = <ðphy0>;
>> 122 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
>> 123 phy-reset-duration = <10>;
>> 124 fsl,magic-packet;
43 status = "okay"; 125 status = "okay";
44 126
45 flash@0 { !! 127 mdio {
46 reg = <0>; <<
47 #address-cells = <1>; 128 #address-cells = <1>;
48 #size-cells = <1>; !! 129 #size-cells = <0>;
49 compatible = "jedec,spi-nor"; !! 130
50 spi-max-frequency = <80000000> !! 131 ethphy0: ethernet-phy@0 {
51 spi-tx-bus-width = <1>; !! 132 compatible = "ethernet-phy-ieee802.3-c22";
52 spi-rx-bus-width = <4>; !! 133 reg = <0>;
>> 134 };
>> 135 };
>> 136 };
>> 137
>> 138 &i2c1 {
>> 139 clock-frequency = <400000>;
>> 140 pinctrl-names = "default";
>> 141 pinctrl-0 = <&pinctrl_i2c1>;
>> 142 status = "okay";
>> 143
>> 144 pmic@4b {
>> 145 compatible = "rohm,bd71847";
>> 146 reg = <0x4b>;
>> 147 pinctrl-0 = <&pinctrl_pmic>;
>> 148 interrupt-parent = <&gpio1>;
>> 149 interrupts = <3 GPIO_ACTIVE_LOW>;
>> 150 rohm,reset-snvs-powered;
>> 151
>> 152 regulators {
>> 153 buck1_reg: BUCK1 {
>> 154 regulator-name = "BUCK1";
>> 155 regulator-min-microvolt = <700000>;
>> 156 regulator-max-microvolt = <1300000>;
>> 157 regulator-boot-on;
>> 158 regulator-always-on;
>> 159 regulator-ramp-delay = <1250>;
>> 160 };
>> 161
>> 162 buck2_reg: BUCK2 {
>> 163 regulator-name = "BUCK2";
>> 164 regulator-min-microvolt = <700000>;
>> 165 regulator-max-microvolt = <1300000>;
>> 166 regulator-boot-on;
>> 167 regulator-always-on;
>> 168 regulator-ramp-delay = <1250>;
>> 169 rohm,dvs-run-voltage = <1000000>;
>> 170 rohm,dvs-idle-voltage = <900000>;
>> 171 };
>> 172
>> 173 buck3_reg: BUCK3 {
>> 174 // BUCK5 in datasheet
>> 175 regulator-name = "BUCK3";
>> 176 regulator-min-microvolt = <700000>;
>> 177 regulator-max-microvolt = <1350000>;
>> 178 regulator-boot-on;
>> 179 regulator-always-on;
>> 180 };
>> 181
>> 182 buck4_reg: BUCK4 {
>> 183 // BUCK6 in datasheet
>> 184 regulator-name = "BUCK4";
>> 185 regulator-min-microvolt = <3000000>;
>> 186 regulator-max-microvolt = <3300000>;
>> 187 regulator-boot-on;
>> 188 regulator-always-on;
>> 189 };
>> 190
>> 191 buck5_reg: BUCK5 {
>> 192 // BUCK7 in datasheet
>> 193 regulator-name = "BUCK5";
>> 194 regulator-min-microvolt = <1605000>;
>> 195 regulator-max-microvolt = <1995000>;
>> 196 regulator-boot-on;
>> 197 regulator-always-on;
>> 198 };
>> 199
>> 200 buck6_reg: BUCK6 {
>> 201 // BUCK8 in datasheet
>> 202 regulator-name = "BUCK6";
>> 203 regulator-min-microvolt = <800000>;
>> 204 regulator-max-microvolt = <1400000>;
>> 205 regulator-boot-on;
>> 206 regulator-always-on;
>> 207 };
>> 208
>> 209 ldo1_reg: LDO1 {
>> 210 regulator-name = "LDO1";
>> 211 regulator-min-microvolt = <1600000>;
>> 212 regulator-max-microvolt = <3300000>;
>> 213 regulator-boot-on;
>> 214 regulator-always-on;
>> 215 };
>> 216
>> 217 ldo2_reg: LDO2 {
>> 218 regulator-name = "LDO2";
>> 219 regulator-min-microvolt = <800000>;
>> 220 regulator-max-microvolt = <900000>;
>> 221 regulator-boot-on;
>> 222 regulator-always-on;
>> 223 };
>> 224
>> 225 ldo3_reg: LDO3 {
>> 226 regulator-name = "LDO3";
>> 227 regulator-min-microvolt = <1800000>;
>> 228 regulator-max-microvolt = <3300000>;
>> 229 regulator-boot-on;
>> 230 regulator-always-on;
>> 231 };
>> 232
>> 233 ldo4_reg: LDO4 {
>> 234 regulator-name = "LDO4";
>> 235 regulator-min-microvolt = <900000>;
>> 236 regulator-max-microvolt = <1800000>;
>> 237 regulator-boot-on;
>> 238 regulator-always-on;
>> 239 };
>> 240
>> 241 ldo6_reg: LDO6 {
>> 242 regulator-name = "LDO6";
>> 243 regulator-min-microvolt = <900000>;
>> 244 regulator-max-microvolt = <1800000>;
>> 245 regulator-boot-on;
>> 246 regulator-always-on;
>> 247 };
>> 248 };
>> 249 };
>> 250 };
>> 251
>> 252 &i2c2 {
>> 253 clock-frequency = <400000>;
>> 254 pinctrl-names = "default";
>> 255 pinctrl-0 = <&pinctrl_i2c2>;
>> 256 status = "okay";
>> 257
>> 258 ptn5110: tcpc@50 {
>> 259 compatible = "nxp,ptn5110";
>> 260 pinctrl-names = "default";
>> 261 pinctrl-0 = <&pinctrl_typec1>;
>> 262 reg = <0x50>;
>> 263 interrupt-parent = <&gpio2>;
>> 264 interrupts = <11 8>;
>> 265 status = "okay";
>> 266
>> 267 port {
>> 268 typec1_dr_sw: endpoint {
>> 269 remote-endpoint = <&usb1_drd_sw>;
>> 270 };
>> 271 };
>> 272
>> 273 typec1_con: connector {
>> 274 compatible = "usb-c-connector";
>> 275 label = "USB-C";
>> 276 power-role = "dual";
>> 277 data-role = "dual";
>> 278 try-power-role = "sink";
>> 279 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
>> 280 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
>> 281 PDO_VAR(5000, 20000, 3000)>;
>> 282 op-sink-microwatt = <15000000>;
>> 283 self-powered;
>> 284 };
>> 285 };
>> 286 };
>> 287
>> 288 &i2c3 {
>> 289 clock-frequency = <400000>;
>> 290 pinctrl-names = "default";
>> 291 pinctrl-0 = <&pinctrl_i2c3>;
>> 292 status = "okay";
>> 293
>> 294 pca6416: gpio@20 {
>> 295 compatible = "ti,tca6416";
>> 296 reg = <0x20>;
>> 297 gpio-controller;
>> 298 #gpio-cells = <2>;
>> 299 };
>> 300 };
>> 301
>> 302 &sai3 {
>> 303 pinctrl-names = "default";
>> 304 pinctrl-0 = <&pinctrl_sai3>;
>> 305 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
>> 306 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
>> 307 assigned-clock-rates = <24576000>;
>> 308 status = "okay";
>> 309 };
>> 310
>> 311 &snvs_pwrkey {
>> 312 status = "okay";
>> 313 };
>> 314
>> 315 &uart2 { /* console */
>> 316 pinctrl-names = "default";
>> 317 pinctrl-0 = <&pinctrl_uart2>;
>> 318 status = "okay";
>> 319 };
>> 320
>> 321 &usbotg1 {
>> 322 dr_mode = "otg";
>> 323 hnp-disable;
>> 324 srp-disable;
>> 325 adp-disable;
>> 326 usb-role-switch;
>> 327 status = "okay";
>> 328
>> 329 port {
>> 330 usb1_drd_sw: endpoint {
>> 331 remote-endpoint = <&typec1_dr_sw>;
>> 332 };
53 }; 333 };
54 }; 334 };
55 335
>> 336 &usdhc2 {
>> 337 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
>> 338 assigned-clock-rates = <200000000>;
>> 339 pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> 340 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>> 341 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>> 342 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>> 343 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
>> 344 bus-width = <4>;
>> 345 vmmc-supply = <®_usdhc2_vmmc>;
>> 346 status = "okay";
>> 347 };
>> 348
56 &usdhc3 { 349 &usdhc3 {
57 assigned-clocks = <&clk IMX8MM_CLK_USD 350 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
58 assigned-clock-rates = <400000000>; 351 assigned-clock-rates = <400000000>;
59 pinctrl-names = "default", "state_100m 352 pinctrl-names = "default", "state_100mhz", "state_200mhz";
60 pinctrl-0 = <&pinctrl_usdhc3>; 353 pinctrl-0 = <&pinctrl_usdhc3>;
61 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 354 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
62 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 355 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
63 bus-width = <8>; 356 bus-width = <8>;
64 non-removable; 357 non-removable;
65 status = "okay"; 358 status = "okay";
66 }; 359 };
67 360
>> 361 &wdog1 {
>> 362 pinctrl-names = "default";
>> 363 pinctrl-0 = <&pinctrl_wdog>;
>> 364 fsl,ext-reset-output;
>> 365 status = "okay";
>> 366 };
>> 367
68 &iomuxc { 368 &iomuxc {
69 pinctrl_flexspi: flexspigrp { !! 369 pinctrl-names = "default";
>> 370
>> 371 pinctrl_fec1: fec1grp {
>> 372 fsl,pins = <
>> 373 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>> 374 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
>> 375 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>> 376 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>> 377 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>> 378 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> 379 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> 380 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> 381 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> 382 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> 383 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> 384 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> 385 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> 386 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> 387 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>> 388 >;
>> 389 };
>> 390
>> 391 pinctrl_gpio_led: gpioledgrp {
>> 392 fsl,pins = <
>> 393 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>> 394 >;
>> 395 };
>> 396
>> 397 pinctrl_gpio_wlf: gpiowlfgrp {
>> 398 fsl,pins = <
>> 399 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>> 400 >;
>> 401 };
>> 402
>> 403 pinctrl_i2c1: i2c1grp {
70 fsl,pins = < 404 fsl,pins = <
71 MX8MM_IOMUXC_NAND_ALE_ !! 405 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
72 MX8MM_IOMUXC_NAND_CE0_ !! 406 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
73 MX8MM_IOMUXC_NAND_DATA !! 407 >;
74 MX8MM_IOMUXC_NAND_DATA !! 408 };
75 MX8MM_IOMUXC_NAND_DATA !! 409
76 MX8MM_IOMUXC_NAND_DATA !! 410 pinctrl_i2c2: i2c2grp {
>> 411 fsl,pins = <
>> 412 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
>> 413 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>> 414 >;
>> 415 };
>> 416
>> 417 pinctrl_i2c3: i2c3grp {
>> 418 fsl,pins = <
>> 419 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
>> 420 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>> 421 >;
>> 422 };
>> 423
>> 424 pinctrl_pmic: pmicirq {
>> 425 fsl,pins = <
>> 426 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>> 427 >;
>> 428 };
>> 429
>> 430 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
>> 431 fsl,pins = <
>> 432 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> 433 >;
>> 434 };
>> 435
>> 436 pinctrl_sai3: sai3grp {
>> 437 fsl,pins = <
>> 438 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
>> 439 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
>> 440 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
>> 441 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>> 442 >;
>> 443 };
>> 444
>> 445 pinctrl_typec1: typec1grp {
>> 446 fsl,pins = <
>> 447 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>> 448 >;
>> 449 };
>> 450
>> 451 pinctrl_uart2: uart2grp {
>> 452 fsl,pins = <
>> 453 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
>> 454 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>> 455 >;
>> 456 };
>> 457
>> 458 pinctrl_usdhc2_gpio: usdhc2grpgpio {
>> 459 fsl,pins = <
>> 460 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>> 461 >;
>> 462 };
>> 463
>> 464 pinctrl_usdhc2: usdhc2grp {
>> 465 fsl,pins = <
>> 466 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
>> 467 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
>> 468 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
>> 469 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
>> 470 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
>> 471 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>> 472 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 473 >;
>> 474 };
>> 475
>> 476 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> 477 fsl,pins = <
>> 478 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
>> 479 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
>> 480 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
>> 481 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
>> 482 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
>> 483 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>> 484 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 485 >;
>> 486 };
>> 487
>> 488 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> 489 fsl,pins = <
>> 490 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
>> 491 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
>> 492 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
>> 493 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
>> 494 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
>> 495 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>> 496 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
77 >; 497 >;
78 }; 498 };
79 499
80 pinctrl_usdhc3: usdhc3grp { 500 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = < 501 fsl,pins = <
82 MX8MM_IOMUXC_NAND_WE_B !! 502 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
83 MX8MM_IOMUXC_NAND_WP_B !! 503 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
84 MX8MM_IOMUXC_NAND_DATA !! 504 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
85 MX8MM_IOMUXC_NAND_DATA !! 505 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
86 MX8MM_IOMUXC_NAND_DATA !! 506 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
87 MX8MM_IOMUXC_NAND_DATA !! 507 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
88 MX8MM_IOMUXC_NAND_DATA !! 508 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
89 MX8MM_IOMUXC_NAND_RE_B !! 509 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
90 MX8MM_IOMUXC_NAND_CE2_ !! 510 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
91 MX8MM_IOMUXC_NAND_CE3_ !! 511 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
92 MX8MM_IOMUXC_NAND_CLE_ !! 512 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
93 MX8MM_IOMUXC_NAND_CE1_ !! 513 >;
>> 514 };
>> 515
>> 516 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
>> 517 fsl,pins = <
>> 518 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
>> 519 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>> 520 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
>> 521 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
>> 522 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
>> 523 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
>> 524 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
>> 525 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
>> 526 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
>> 527 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
>> 528 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
94 >; 529 >;
95 }; 530 };
96 531
97 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr !! 532 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
98 fsl,pins = < !! 533 fsl,pins = <
99 MX8MM_IOMUXC_NAND_WE_B !! 534 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
100 MX8MM_IOMUXC_NAND_WP_B !! 535 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
101 MX8MM_IOMUXC_NAND_DATA !! 536 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
102 MX8MM_IOMUXC_NAND_DATA !! 537 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
103 MX8MM_IOMUXC_NAND_DATA !! 538 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
104 MX8MM_IOMUXC_NAND_DATA !! 539 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
105 MX8MM_IOMUXC_NAND_RE_B !! 540 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
106 MX8MM_IOMUXC_NAND_CE2_ !! 541 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
107 MX8MM_IOMUXC_NAND_CE3_ !! 542 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
108 MX8MM_IOMUXC_NAND_CLE_ !! 543 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
109 MX8MM_IOMUXC_NAND_CE1_ !! 544 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
110 >; 545 >;
111 }; 546 };
112 547
113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr !! 548 pinctrl_wdog: wdoggrp {
114 fsl,pins = < !! 549 fsl,pins = <
115 MX8MM_IOMUXC_NAND_WE_B !! 550 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
116 MX8MM_IOMUXC_NAND_WP_B <<
117 MX8MM_IOMUXC_NAND_DATA <<
118 MX8MM_IOMUXC_NAND_DATA <<
119 MX8MM_IOMUXC_NAND_DATA <<
120 MX8MM_IOMUXC_NAND_DATA <<
121 MX8MM_IOMUXC_NAND_RE_B <<
122 MX8MM_IOMUXC_NAND_CE2_ <<
123 MX8MM_IOMUXC_NAND_CE3_ <<
124 MX8MM_IOMUXC_NAND_CLE_ <<
125 MX8MM_IOMUXC_NAND_CE1_ <<
126 >; 551 >;
127 }; 552 };
128 }; 553 };
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