1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2020 NXP
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi"
11
12 / {
13 chosen {
14 stdout-path = &uart2;
15 };
16
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x8000
20 };
21
22 hdmi-connector {
23 compatible = "hdmi-connector";
24 label = "hdmi";
25 type = "a";
26
27 port {
28 hdmi_connector_in: end
29 remote-endpoin
30 };
31 };
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led
38
39 status {
40 label = "status";
41 gpios = <&gpio3 16 GPI
42 default-state = "on";
43 };
44 };
45
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <100000000>;
50 };
51
52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed"
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_re
56 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <330
58 regulator-max-microvolt = <330
59 gpio = <&gpio1 5 GPIO_ACTIVE_H
60 enable-active-high;
61 };
62
63 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed"
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdh
67 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <330
69 regulator-max-microvolt = <330
70 gpio = <&gpio2 19 GPIO_ACTIVE_
71 off-on-delay-us = <20000>;
72 enable-active-high;
73 };
74
75 reg_1v5: regulator-1v5 {
76 compatible = "regulator-fixed"
77 regulator-name = "VDD_1V5";
78 regulator-min-microvolt = <150
79 regulator-max-microvolt = <150
80 };
81
82 reg_1v8: regulator-1v8 {
83 compatible = "regulator-fixed"
84 regulator-name = "VDD_1V8";
85 regulator-min-microvolt = <180
86 regulator-max-microvolt = <180
87 };
88
89 reg_vddext_3v3: regulator-vddext-3v3 {
90 compatible = "regulator-fixed"
91 regulator-name = "VDDEXT_3V3";
92 regulator-min-microvolt = <330
93 regulator-max-microvolt = <330
94 };
95
96 backlight: backlight {
97 compatible = "pwm-backlight";
98 pwms = <&pwm1 0 5000000 0>;
99 brightness-levels = <0 255>;
100 num-interpolated-steps = <255>
101 default-brightness-level = <25
102 };
103
104 ir-receiver {
105 compatible = "gpio-ir-receiver
106 gpios = <&gpio1 13 GPIO_ACTIVE
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_ir>;
109 linux,autosuspend-period = <12
110 };
111
112 audio_codec_bt_sco: audio-codec-bt-sco
113 compatible = "linux,bt-sco";
114 #sound-dai-cells = <1>;
115 };
116
117 wm8524: audio-codec {
118 #sound-dai-cells = <0>;
119 compatible = "wlf,wm8524";
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_gpio_wlf
122 wlf,mute-gpios = <&gpio5 21 GP
123 };
124
125 sound-bt-sco {
126 compatible = "simple-audio-car
127 simple-audio-card,name = "bt-s
128 simple-audio-card,format = "ds
129 simple-audio-card,bitclock-inv
130 simple-audio-card,frame-master
131 simple-audio-card,bitclock-mas
132
133 btcpu: simple-audio-card,cpu {
134 sound-dai = <&sai2>;
135 dai-tdm-slot-num = <2>
136 dai-tdm-slot-width = <
137 };
138
139 simple-audio-card,codec {
140 sound-dai = <&audio_co
141 };
142 };
143
144 sound-wm8524 {
145 compatible = "simple-audio-car
146 simple-audio-card,name = "wm85
147 simple-audio-card,format = "i2
148 simple-audio-card,frame-master
149 simple-audio-card,bitclock-mas
150 simple-audio-card,widgets =
151 "Line", "Left Line Out
152 "Line", "Right Line Ou
153 simple-audio-card,routing =
154 "Left Line Out Jack",
155 "Right Line Out Jack",
156
157 cpudai: simple-audio-card,cpu
158 sound-dai = <&sai3>;
159 dai-tdm-slot-num = <2>
160 dai-tdm-slot-width = <
161 };
162
163 simple-audio-card,codec {
164 sound-dai = <&wm8524>;
165 clocks = <&clk IMX8MM_
166 };
167 };
168
169 sound-micfil {
170 compatible = "fsl,imx-audio-ca
171 model = "micfil-audio";
172
173 pri-dai-link {
174 link-name = "micfil hi
175 format = "i2s";
176
177 cpu {
178 sound-dai = <&
179 };
180 };
181 };
182
183 spdif_out: spdif-out {
184 compatible = "linux,spdif-dit"
185 #sound-dai-cells = <0>;
186 };
187
188 spdif_in: spdif-in {
189 compatible = "linux,spdif-dir"
190 #sound-dai-cells = <0>;
191 };
192
193 sound-spdif {
194 compatible = "fsl,imx-audio-sp
195 model = "imx-spdif";
196 audio-cpu = <&spdif1>;
197 audio-codec = <&spdif_out>, <&
198 };
199 };
200
201 &A53_0 {
202 cpu-supply = <&buck2_reg>;
203 };
204
205 &A53_1 {
206 cpu-supply = <&buck2_reg>;
207 };
208
209 &A53_2 {
210 cpu-supply = <&buck2_reg>;
211 };
212
213 &A53_3 {
214 cpu-supply = <&buck2_reg>;
215 };
216
217 &fec1 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec1>;
220 phy-mode = "rgmii-id";
221 phy-handle = <ðphy0>;
222 fsl,magic-packet;
223 status = "okay";
224
225 mdio {
226 #address-cells = <1>;
227 #size-cells = <0>;
228
229 ethphy0: ethernet-phy@0 {
230 compatible = "ethernet
231 reg = <0>;
232 reset-gpios = <&gpio4
233 reset-assert-us = <100
234 qca,disable-smarteee;
235 vddio-supply = <&vddio
236
237 vddio: vddio-regulator
238 regulator-min-
239 regulator-max-
240 };
241 };
242 };
243 };
244
245 &i2c1 {
246 clock-frequency = <400000>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay";
250
251 pmic@4b {
252 compatible = "rohm,bd71847";
253 reg = <0x4b>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_pmic>;
256 interrupt-parent = <&gpio1>;
257 interrupts = <3 IRQ_TYPE_LEVEL
258 rohm,reset-snvs-powered;
259
260 #clock-cells = <0>;
261 clocks = <&osc_32k>;
262 clock-output-names = "clk-32k-
263
264 regulators {
265 buck1_reg: BUCK1 {
266 regulator-name
267 regulator-min-
268 regulator-max-
269 regulator-boot
270 regulator-alwa
271 regulator-ramp
272 };
273
274 buck2_reg: BUCK2 {
275 regulator-name
276 regulator-min-
277 regulator-max-
278 regulator-boot
279 regulator-alwa
280 regulator-ramp
281 rohm,dvs-run-v
282 rohm,dvs-idle-
283 };
284
285 buck3_reg: BUCK3 {
286 // BUCK5 in da
287 regulator-name
288 regulator-min-
289 regulator-max-
290 regulator-boot
291 regulator-alwa
292 };
293
294 buck4_reg: BUCK4 {
295 // BUCK6 in da
296 regulator-name
297 regulator-min-
298 regulator-max-
299 regulator-boot
300 regulator-alwa
301 };
302
303 buck5_reg: BUCK5 {
304 // BUCK7 in da
305 regulator-name
306 regulator-min-
307 regulator-max-
308 regulator-boot
309 regulator-alwa
310 };
311
312 buck6_reg: BUCK6 {
313 // BUCK8 in da
314 regulator-name
315 regulator-min-
316 regulator-max-
317 regulator-boot
318 regulator-alwa
319 };
320
321 ldo1_reg: LDO1 {
322 regulator-name
323 regulator-min-
324 regulator-max-
325 regulator-boot
326 regulator-alwa
327 };
328
329 ldo2_reg: LDO2 {
330 regulator-name
331 regulator-min-
332 regulator-max-
333 regulator-boot
334 regulator-alwa
335 };
336
337 ldo3_reg: LDO3 {
338 regulator-name
339 regulator-min-
340 regulator-max-
341 regulator-boot
342 regulator-alwa
343 };
344
345 ldo4_reg: LDO4 {
346 regulator-name
347 regulator-min-
348 regulator-max-
349 regulator-boot
350 regulator-alwa
351 };
352
353 ldo6_reg: LDO6 {
354 regulator-name
355 regulator-min-
356 regulator-max-
357 regulator-boot
358 regulator-alwa
359 };
360 };
361 };
362 };
363
364 &i2c2 {
365 clock-frequency = <400000>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c2>;
368 status = "okay";
369
370 hdmi@3d {
371 compatible = "adi,adv7535";
372 reg = <0x3d>;
373 interrupt-parent = <&gpio1>;
374 interrupts = <9 IRQ_TYPE_EDGE_
375 adi,dsi-lanes = <4>;
376 avdd-supply = <&buck5_reg>;
377 dvdd-supply = <&buck5_reg>;
378 pvdd-supply = <&buck5_reg>;
379 a2vdd-supply = <&buck5_reg>;
380 v3p3-supply = <®_vddext_3v3
381 v1p2-supply = <&buck5_reg>;
382
383 ports {
384 #address-cells = <1>;
385 #size-cells = <0>;
386
387 port@0 {
388 reg = <0>;
389
390 adv7535_in: en
391 remote
392 };
393 };
394
395 port@1 {
396 reg = <1>;
397
398 adv7535_out: e
399 remote
400 };
401 };
402
403 };
404 };
405
406 ptn5110: tcpc@50 {
407 compatible = "nxp,ptn5110", "t
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_typec1>;
410 reg = <0x50>;
411 interrupt-parent = <&gpio2>;
412 interrupts = <11 IRQ_TYPE_LEVE
413 status = "okay";
414
415 typec1_con: connector {
416 compatible = "usb-c-co
417 label = "USB-C";
418 power-role = "dual";
419 data-role = "dual";
420 try-power-role = "sink
421 source-pdos = <PDO_FIX
422 sink-pdos = <PDO_FIXED
423 PDO_VAR(5
424 op-sink-microwatt = <1
425 self-powered;
426
427 port {
428 typec1_dr_sw:
429 remote
430 };
431 };
432 };
433 };
434 };
435
436
437 &csi {
438 status = "okay";
439 };
440
441 &i2c3 {
442 clock-frequency = <400000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay";
446
447 pca6416: gpio@20 {
448 compatible = "nxp,pca6416";
449 reg = <0x20>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 vcc-supply = <&buck4_reg>;
453 };
454
455 camera@3c {
456 compatible = "ovti,ov5640";
457 reg = <0x3c>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_camera>;
460 clocks = <&clk IMX8MM_CLK_CLKO
461 clock-names = "xclk";
462 assigned-clocks = <&clk IMX8MM
463 assigned-clock-parents = <&clk
464 assigned-clock-rates = <240000
465 powerdown-gpios = <&gpio1 7 GP
466 reset-gpios = <&gpio1 6 GPIO_A
467 DOVDD-supply = <&buck5_reg>;
468 AVDD-supply = <®_1v8>;
469 DVDD-supply = <®_1v5>;
470
471 port {
472 ov5640_to_mipi_csi2: e
473 remote-endpoin
474 clock-lanes =
475 data-lanes = <
476 };
477 };
478 };
479 };
480
481 &lcdif {
482 status = "okay";
483 };
484
485 &micfil {
486 #sound-dai-cells = <0>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_pdm>;
489 assigned-clocks = <&clk IMX8MM_CLK_PDM
490 assigned-clock-parents = <&clk IMX8MM_
491 assigned-clock-rates = <196608000>;
492 status = "okay";
493 };
494
495 &mipi_csi {
496 status = "okay";
497
498 ports {
499 port@0 {
500 imx8mm_mipi_csi_in: en
501 remote-endpoin
502 data-lanes = <
503 };
504 };
505 };
506 };
507
508 &mipi_dsi {
509 samsung,esc-clock-frequency = <1000000
510 status = "okay";
511
512 ports {
513 port@1 {
514 reg = <1>;
515
516 dsi_out: endpoint {
517 remote-endpoin
518 data-lanes = <
519 };
520 };
521 };
522 };
523
524 &pcie_phy {
525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
526 fsl,tx-deemph-gen1 = <0x2d>;
527 fsl,tx-deemph-gen2 = <0xf>;
528 clocks = <&pcie0_refclk>;
529 status = "okay";
530 };
531
532 &pcie0 {
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_pcie0>;
535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LO
536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
537 <&clk IMX8MM_CLK_PCIE1_AUX>;
538 assigned-clocks = <&clk IMX8MM_CLK_PCI
539 <&clk IMX8MM_CLK_PCI
540 assigned-clock-rates = <10000000>, <25
541 assigned-clock-parents = <&clk IMX8MM_
542 <&clk IMX8MM_
543 vpcie-supply = <®_pcie0>;
544 status = "okay";
545 };
546
547 &sai2 {
548 #sound-dai-cells = <0>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_sai2>;
551 assigned-clocks = <&clk IMX8MM_CLK_SAI
552 assigned-clock-parents = <&clk IMX8MM_
553 assigned-clock-rates = <24576000>;
554 status = "okay";
555 };
556
557 &sai3 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_sai3>;
560 assigned-clocks = <&clk IMX8MM_CLK_SAI
561 assigned-clock-parents = <&clk IMX8MM_
562 assigned-clock-rates = <24576000>;
563 status = "okay";
564 };
565
566 &snvs_pwrkey {
567 status = "okay";
568 };
569
570 &spdif1 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_spdif1>;
573 assigned-clocks = <&clk IMX8MM_CLK_SPD
574 assigned-clock-parents = <&clk IMX8MM_
575 assigned-clock-rates = <24576000>;
576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>,
577 <&clk IMX8MM_CLK_SPDIF1>, <&c
578 <&clk IMX8MM_CLK_DUMMY>, <&cl
579 <&clk IMX8MM_CLK_AUDIO_AHB>,
580 <&clk IMX8MM_CLK_DUMMY>, <&cl
581 <&clk IMX8MM_AUDIO_PLL1_OUT>,
582 clock-names = "core", "rxtx0", "rxtx1"
583 "rxtx4", "rxtx5", "rxtx6
584 "pll8k", "pll11k";
585 status = "okay";
586 };
587
588 &uart2 { /* console */
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart2>;
591 status = "okay";
592 };
593
594 &usbphynop1 {
595 wakeup-source;
596 };
597
598 &usbotg1 {
599 dr_mode = "otg";
600 hnp-disable;
601 srp-disable;
602 adp-disable;
603 usb-role-switch;
604 disable-over-current;
605 samsung,picophy-pre-emp-curr-control =
606 samsung,picophy-dc-vol-level-adjust =
607 status = "okay";
608
609 port {
610 usb1_drd_sw: endpoint {
611 remote-endpoint = <&ty
612 };
613 };
614 };
615
616 &usdhc2 {
617 assigned-clocks = <&clk IMX8MM_CLK_USD
618 assigned-clock-rates = <200000000>;
619 pinctrl-names = "default", "state_100m
620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>
624 bus-width = <4>;
625 vmmc-supply = <®_usdhc2_vmmc>;
626 status = "okay";
627 };
628
629 &wdog1 {
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_wdog>;
632 fsl,ext-reset-output;
633 status = "okay";
634 };
635
636 &pwm1 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_backlight>;
639 status = "okay";
640 };
641
642 &iomuxc {
643 pinctrl_fec1: fec1grp {
644 fsl,pins = <
645 MX8MM_IOMUXC_ENET_MDC_
646 MX8MM_IOMUXC_ENET_MDIO
647 MX8MM_IOMUXC_ENET_TD3_
648 MX8MM_IOMUXC_ENET_TD2_
649 MX8MM_IOMUXC_ENET_TD1_
650 MX8MM_IOMUXC_ENET_TD0_
651 MX8MM_IOMUXC_ENET_RD3_
652 MX8MM_IOMUXC_ENET_RD2_
653 MX8MM_IOMUXC_ENET_RD1_
654 MX8MM_IOMUXC_ENET_RD0_
655 MX8MM_IOMUXC_ENET_TXC_
656 MX8MM_IOMUXC_ENET_RXC_
657 MX8MM_IOMUXC_ENET_RX_C
658 MX8MM_IOMUXC_ENET_TX_C
659 MX8MM_IOMUXC_SAI2_RXC_
660 >;
661 };
662
663 pinctrl_gpio_led: gpioledgrp {
664 fsl,pins = <
665 MX8MM_IOMUXC_NAND_READ
666 >;
667 };
668
669 pinctrl_ir: irgrp {
670 fsl,pins = <
671 MX8MM_IOMUXC_GPIO1_IO1
672 >;
673 };
674
675 pinctrl_gpio_wlf: gpiowlfgrp {
676 fsl,pins = <
677 MX8MM_IOMUXC_I2C4_SDA_
678 >;
679 };
680
681 pinctrl_i2c1: i2c1grp {
682 fsl,pins = <
683 MX8MM_IOMUXC_I2C1_SCL_
684 MX8MM_IOMUXC_I2C1_SDA_
685 >;
686 };
687
688 pinctrl_i2c2: i2c2grp {
689 fsl,pins = <
690 MX8MM_IOMUXC_I2C2_SCL_
691 MX8MM_IOMUXC_I2C2_SDA_
692 >;
693 };
694
695 pinctrl_i2c3: i2c3grp {
696 fsl,pins = <
697 MX8MM_IOMUXC_I2C3_SCL_
698 MX8MM_IOMUXC_I2C3_SDA_
699 >;
700 };
701
702 pinctrl_pcie0: pcie0grp {
703 fsl,pins = <
704 MX8MM_IOMUXC_I2C4_SCL_
705 MX8MM_IOMUXC_SAI2_RXFS
706 >;
707 };
708
709 pinctrl_pcie0_reg: pcie0reggrp {
710 fsl,pins = <
711 MX8MM_IOMUXC_GPIO1_IO0
712 >;
713 };
714
715 pinctrl_pdm: pdmgrp {
716 fsl,pins = <
717 MX8MM_IOMUXC_SAI5_MCLK
718 MX8MM_IOMUXC_SAI5_RXC_
719 MX8MM_IOMUXC_SAI5_RXFS
720 MX8MM_IOMUXC_SAI5_RXD0
721 MX8MM_IOMUXC_SAI5_RXD1
722 MX8MM_IOMUXC_SAI5_RXD2
723 MX8MM_IOMUXC_SAI5_RXD3
724 >;
725 };
726
727 pinctrl_pmic: pmicirqgrp {
728 fsl,pins = <
729 MX8MM_IOMUXC_GPIO1_IO0
730 >;
731 };
732
733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc
734 fsl,pins = <
735 MX8MM_IOMUXC_SD2_RESET
736 >;
737 };
738
739 pinctrl_sai2: sai2grp {
740 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXC_
742 MX8MM_IOMUXC_SAI2_TXFS
743 MX8MM_IOMUXC_SAI2_TXD0
744 MX8MM_IOMUXC_SAI2_RXD0
745 >;
746 };
747
748 pinctrl_sai3: sai3grp {
749 fsl,pins = <
750 MX8MM_IOMUXC_SAI3_TXFS
751 MX8MM_IOMUXC_SAI3_TXC_
752 MX8MM_IOMUXC_SAI3_MCLK
753 MX8MM_IOMUXC_SAI3_TXD_
754 >;
755 };
756
757 pinctrl_spdif1: spdif1grp {
758 fsl,pins = <
759 MX8MM_IOMUXC_SPDIF_TX_
760 MX8MM_IOMUXC_SPDIF_RX_
761 >;
762 };
763
764 pinctrl_typec1: typec1grp {
765 fsl,pins = <
766 MX8MM_IOMUXC_SD1_STROB
767 >;
768 };
769
770 pinctrl_uart2: uart2grp {
771 fsl,pins = <
772 MX8MM_IOMUXC_UART2_RXD
773 MX8MM_IOMUXC_UART2_TXD
774 >;
775 };
776
777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp
778 fsl,pins = <
779 MX8MM_IOMUXC_GPIO1_IO1
780 >;
781 };
782
783 pinctrl_usdhc2: usdhc2grp {
784 fsl,pins = <
785 MX8MM_IOMUXC_SD2_CLK_U
786 MX8MM_IOMUXC_SD2_CMD_U
787 MX8MM_IOMUXC_SD2_DATA0
788 MX8MM_IOMUXC_SD2_DATA1
789 MX8MM_IOMUXC_SD2_DATA2
790 MX8MM_IOMUXC_SD2_DATA3
791 MX8MM_IOMUXC_GPIO1_IO0
792 >;
793 };
794
795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
796 fsl,pins = <
797 MX8MM_IOMUXC_SD2_CLK_U
798 MX8MM_IOMUXC_SD2_CMD_U
799 MX8MM_IOMUXC_SD2_DATA0
800 MX8MM_IOMUXC_SD2_DATA1
801 MX8MM_IOMUXC_SD2_DATA2
802 MX8MM_IOMUXC_SD2_DATA3
803 MX8MM_IOMUXC_GPIO1_IO0
804 >;
805 };
806
807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
808 fsl,pins = <
809 MX8MM_IOMUXC_SD2_CLK_U
810 MX8MM_IOMUXC_SD2_CMD_U
811 MX8MM_IOMUXC_SD2_DATA0
812 MX8MM_IOMUXC_SD2_DATA1
813 MX8MM_IOMUXC_SD2_DATA2
814 MX8MM_IOMUXC_SD2_DATA3
815 MX8MM_IOMUXC_GPIO1_IO0
816 >;
817 };
818
819 pinctrl_wdog: wdoggrp {
820 fsl,pins = <
821 MX8MM_IOMUXC_GPIO1_IO0
822 >;
823 };
824
825 pinctrl_backlight: backlightgrp {
826 fsl,pins = <
827 MX8MM_IOMUXC_GPIO1_IO0
828 >;
829 };
830
831 pinctrl_camera: cameragrp {
832 fsl,pins = <
833 MX8MM_IOMUXC_GPIO1_IO0
834 MX8MM_IOMUXC_GPIO1_IO0
835 MX8MM_IOMUXC_GPIO1_IO1
836 >;
837 };
838 };
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