1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
9 #include <dt-bindings/usb/pd.h> 8 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi" 9 #include "imx8mm.dtsi"
11 10
12 / { 11 / {
13 chosen { 12 chosen {
14 stdout-path = &uart2; 13 stdout-path = &uart2;
15 }; 14 };
16 15
17 memory@40000000 { 16 memory@40000000 {
18 device_type = "memory"; 17 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x8000 18 reg = <0x0 0x40000000 0 0x80000000>;
20 }; 19 };
21 20
22 hdmi-connector { <<
23 compatible = "hdmi-connector"; <<
24 label = "hdmi"; <<
25 type = "a"; <<
26 <<
27 port { <<
28 hdmi_connector_in: end <<
29 remote-endpoin <<
30 }; <<
31 }; <<
32 }; <<
33 <<
34 leds { 21 leds {
35 compatible = "gpio-leds"; 22 compatible = "gpio-leds";
36 pinctrl-names = "default"; 23 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led 24 pinctrl-0 = <&pinctrl_gpio_led>;
38 25
39 status { 26 status {
40 label = "status"; 27 label = "status";
41 gpios = <&gpio3 16 GPI 28 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on"; 29 default-state = "on";
43 }; 30 };
44 }; 31 };
45 32
46 pcie0_refclk: pcie0-refclk { <<
47 compatible = "fixed-clock"; <<
48 #clock-cells = <0>; <<
49 clock-frequency = <100000000>; <<
50 }; <<
51 <<
52 reg_pcie0: regulator-pcie { <<
53 compatible = "regulator-fixed" <<
54 pinctrl-names = "default"; <<
55 pinctrl-0 = <&pinctrl_pcie0_re <<
56 regulator-name = "MPCIE_3V3"; <<
57 regulator-min-microvolt = <330 <<
58 regulator-max-microvolt = <330 <<
59 gpio = <&gpio1 5 GPIO_ACTIVE_H <<
60 enable-active-high; <<
61 }; <<
62 <<
63 reg_usdhc2_vmmc: regulator-usdhc2 { 33 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed" 34 compatible = "regulator-fixed";
65 pinctrl-names = "default"; 35 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdh 36 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3"; 37 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <330 38 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <330 39 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_ 40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>; <<
72 enable-active-high; 41 enable-active-high;
73 }; 42 };
74 43
75 reg_1v5: regulator-1v5 { <<
76 compatible = "regulator-fixed" <<
77 regulator-name = "VDD_1V5"; <<
78 regulator-min-microvolt = <150 <<
79 regulator-max-microvolt = <150 <<
80 }; <<
81 <<
82 reg_1v8: regulator-1v8 { <<
83 compatible = "regulator-fixed" <<
84 regulator-name = "VDD_1V8"; <<
85 regulator-min-microvolt = <180 <<
86 regulator-max-microvolt = <180 <<
87 }; <<
88 <<
89 reg_vddext_3v3: regulator-vddext-3v3 { <<
90 compatible = "regulator-fixed" <<
91 regulator-name = "VDDEXT_3V3"; <<
92 regulator-min-microvolt = <330 <<
93 regulator-max-microvolt = <330 <<
94 }; <<
95 <<
96 backlight: backlight { <<
97 compatible = "pwm-backlight"; <<
98 pwms = <&pwm1 0 5000000 0>; <<
99 brightness-levels = <0 255>; <<
100 num-interpolated-steps = <255> <<
101 default-brightness-level = <25 <<
102 }; <<
103 <<
104 ir-receiver { 44 ir-receiver {
105 compatible = "gpio-ir-receiver 45 compatible = "gpio-ir-receiver";
106 gpios = <&gpio1 13 GPIO_ACTIVE 46 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
107 pinctrl-names = "default"; 47 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_ir>; 48 pinctrl-0 = <&pinctrl_ir>;
109 linux,autosuspend-period = <12 49 linux,autosuspend-period = <125>;
110 }; 50 };
111 51
112 audio_codec_bt_sco: audio-codec-bt-sco <<
113 compatible = "linux,bt-sco"; <<
114 #sound-dai-cells = <1>; <<
115 }; <<
116 <<
117 wm8524: audio-codec { 52 wm8524: audio-codec {
118 #sound-dai-cells = <0>; 53 #sound-dai-cells = <0>;
119 compatible = "wlf,wm8524"; 54 compatible = "wlf,wm8524";
120 pinctrl-names = "default"; 55 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_gpio_wlf 56 pinctrl-0 = <&pinctrl_gpio_wlf>;
122 wlf,mute-gpios = <&gpio5 21 GP 57 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
123 }; 58 };
124 59
125 sound-bt-sco { <<
126 compatible = "simple-audio-car <<
127 simple-audio-card,name = "bt-s <<
128 simple-audio-card,format = "ds <<
129 simple-audio-card,bitclock-inv <<
130 simple-audio-card,frame-master <<
131 simple-audio-card,bitclock-mas <<
132 <<
133 btcpu: simple-audio-card,cpu { <<
134 sound-dai = <&sai2>; <<
135 dai-tdm-slot-num = <2> <<
136 dai-tdm-slot-width = < <<
137 }; <<
138 <<
139 simple-audio-card,codec { <<
140 sound-dai = <&audio_co <<
141 }; <<
142 }; <<
143 <<
144 sound-wm8524 { 60 sound-wm8524 {
145 compatible = "simple-audio-car 61 compatible = "simple-audio-card";
146 simple-audio-card,name = "wm85 62 simple-audio-card,name = "wm8524-audio";
147 simple-audio-card,format = "i2 63 simple-audio-card,format = "i2s";
148 simple-audio-card,frame-master 64 simple-audio-card,frame-master = <&cpudai>;
149 simple-audio-card,bitclock-mas 65 simple-audio-card,bitclock-master = <&cpudai>;
150 simple-audio-card,widgets = 66 simple-audio-card,widgets =
151 "Line", "Left Line Out 67 "Line", "Left Line Out Jack",
152 "Line", "Right Line Ou 68 "Line", "Right Line Out Jack";
153 simple-audio-card,routing = 69 simple-audio-card,routing =
154 "Left Line Out Jack", 70 "Left Line Out Jack", "LINEVOUTL",
155 "Right Line Out Jack", 71 "Right Line Out Jack", "LINEVOUTR";
156 72
157 cpudai: simple-audio-card,cpu 73 cpudai: simple-audio-card,cpu {
158 sound-dai = <&sai3>; 74 sound-dai = <&sai3>;
159 dai-tdm-slot-num = <2> 75 dai-tdm-slot-num = <2>;
160 dai-tdm-slot-width = < 76 dai-tdm-slot-width = <32>;
161 }; 77 };
162 78
163 simple-audio-card,codec { 79 simple-audio-card,codec {
164 sound-dai = <&wm8524>; 80 sound-dai = <&wm8524>;
165 clocks = <&clk IMX8MM_ 81 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
166 }; 82 };
167 }; 83 };
168 <<
169 sound-micfil { <<
170 compatible = "fsl,imx-audio-ca <<
171 model = "micfil-audio"; <<
172 <<
173 pri-dai-link { <<
174 link-name = "micfil hi <<
175 format = "i2s"; <<
176 <<
177 cpu { <<
178 sound-dai = <& <<
179 }; <<
180 }; <<
181 }; <<
182 <<
183 spdif_out: spdif-out { <<
184 compatible = "linux,spdif-dit" <<
185 #sound-dai-cells = <0>; <<
186 }; <<
187 <<
188 spdif_in: spdif-in { <<
189 compatible = "linux,spdif-dir" <<
190 #sound-dai-cells = <0>; <<
191 }; <<
192 <<
193 sound-spdif { <<
194 compatible = "fsl,imx-audio-sp <<
195 model = "imx-spdif"; <<
196 audio-cpu = <&spdif1>; <<
197 audio-codec = <&spdif_out>, <& <<
198 }; <<
199 }; 84 };
200 85
201 &A53_0 { 86 &A53_0 {
202 cpu-supply = <&buck2_reg>; 87 cpu-supply = <&buck2_reg>;
203 }; 88 };
204 89
205 &A53_1 { 90 &A53_1 {
206 cpu-supply = <&buck2_reg>; 91 cpu-supply = <&buck2_reg>;
207 }; 92 };
208 93
209 &A53_2 { 94 &A53_2 {
210 cpu-supply = <&buck2_reg>; 95 cpu-supply = <&buck2_reg>;
211 }; 96 };
212 97
213 &A53_3 { 98 &A53_3 {
214 cpu-supply = <&buck2_reg>; 99 cpu-supply = <&buck2_reg>;
215 }; 100 };
216 101
217 &fec1 { 102 &fec1 {
218 pinctrl-names = "default"; 103 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec1>; 104 pinctrl-0 = <&pinctrl_fec1>;
220 phy-mode = "rgmii-id"; 105 phy-mode = "rgmii-id";
221 phy-handle = <ðphy0>; 106 phy-handle = <ðphy0>;
222 fsl,magic-packet; 107 fsl,magic-packet;
223 status = "okay"; 108 status = "okay";
224 109
225 mdio { 110 mdio {
226 #address-cells = <1>; 111 #address-cells = <1>;
227 #size-cells = <0>; 112 #size-cells = <0>;
228 113
229 ethphy0: ethernet-phy@0 { 114 ethphy0: ethernet-phy@0 {
230 compatible = "ethernet 115 compatible = "ethernet-phy-ieee802.3-c22";
231 reg = <0>; 116 reg = <0>;
232 reset-gpios = <&gpio4 117 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
233 reset-assert-us = <100 118 reset-assert-us = <10000>;
234 qca,disable-smarteee; 119 qca,disable-smarteee;
235 vddio-supply = <&vddio 120 vddio-supply = <&vddio>;
236 121
237 vddio: vddio-regulator 122 vddio: vddio-regulator {
238 regulator-min- 123 regulator-min-microvolt = <1800000>;
239 regulator-max- 124 regulator-max-microvolt = <1800000>;
240 }; 125 };
241 }; 126 };
242 }; 127 };
243 }; 128 };
244 129
245 &i2c1 { 130 &i2c1 {
246 clock-frequency = <400000>; 131 clock-frequency = <400000>;
247 pinctrl-names = "default"; 132 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>; 133 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay"; 134 status = "okay";
250 135
251 pmic@4b { 136 pmic@4b {
252 compatible = "rohm,bd71847"; 137 compatible = "rohm,bd71847";
253 reg = <0x4b>; 138 reg = <0x4b>;
254 pinctrl-names = "default"; 139 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_pmic>; 140 pinctrl-0 = <&pinctrl_pmic>;
256 interrupt-parent = <&gpio1>; 141 interrupt-parent = <&gpio1>;
257 interrupts = <3 IRQ_TYPE_LEVEL 142 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
258 rohm,reset-snvs-powered; 143 rohm,reset-snvs-powered;
259 144
260 #clock-cells = <0>; 145 #clock-cells = <0>;
261 clocks = <&osc_32k>; !! 146 clocks = <&osc_32k 0>;
262 clock-output-names = "clk-32k- 147 clock-output-names = "clk-32k-out";
263 148
264 regulators { 149 regulators {
265 buck1_reg: BUCK1 { 150 buck1_reg: BUCK1 {
266 regulator-name 151 regulator-name = "buck1";
267 regulator-min- 152 regulator-min-microvolt = <700000>;
268 regulator-max- 153 regulator-max-microvolt = <1300000>;
269 regulator-boot 154 regulator-boot-on;
270 regulator-alwa 155 regulator-always-on;
271 regulator-ramp 156 regulator-ramp-delay = <1250>;
272 }; 157 };
273 158
274 buck2_reg: BUCK2 { 159 buck2_reg: BUCK2 {
275 regulator-name 160 regulator-name = "buck2";
276 regulator-min- 161 regulator-min-microvolt = <700000>;
277 regulator-max- 162 regulator-max-microvolt = <1300000>;
278 regulator-boot 163 regulator-boot-on;
279 regulator-alwa 164 regulator-always-on;
280 regulator-ramp 165 regulator-ramp-delay = <1250>;
281 rohm,dvs-run-v 166 rohm,dvs-run-voltage = <1000000>;
282 rohm,dvs-idle- 167 rohm,dvs-idle-voltage = <900000>;
283 }; 168 };
284 169
285 buck3_reg: BUCK3 { 170 buck3_reg: BUCK3 {
286 // BUCK5 in da 171 // BUCK5 in datasheet
287 regulator-name 172 regulator-name = "buck3";
288 regulator-min- 173 regulator-min-microvolt = <700000>;
289 regulator-max- 174 regulator-max-microvolt = <1350000>;
290 regulator-boot 175 regulator-boot-on;
291 regulator-alwa 176 regulator-always-on;
292 }; 177 };
293 178
294 buck4_reg: BUCK4 { 179 buck4_reg: BUCK4 {
295 // BUCK6 in da 180 // BUCK6 in datasheet
296 regulator-name 181 regulator-name = "buck4";
297 regulator-min- 182 regulator-min-microvolt = <3000000>;
298 regulator-max- 183 regulator-max-microvolt = <3300000>;
299 regulator-boot 184 regulator-boot-on;
300 regulator-alwa 185 regulator-always-on;
301 }; 186 };
302 187
303 buck5_reg: BUCK5 { 188 buck5_reg: BUCK5 {
304 // BUCK7 in da 189 // BUCK7 in datasheet
305 regulator-name 190 regulator-name = "buck5";
306 regulator-min- 191 regulator-min-microvolt = <1605000>;
307 regulator-max- 192 regulator-max-microvolt = <1995000>;
308 regulator-boot 193 regulator-boot-on;
309 regulator-alwa 194 regulator-always-on;
310 }; 195 };
311 196
312 buck6_reg: BUCK6 { 197 buck6_reg: BUCK6 {
313 // BUCK8 in da 198 // BUCK8 in datasheet
314 regulator-name 199 regulator-name = "buck6";
315 regulator-min- 200 regulator-min-microvolt = <800000>;
316 regulator-max- 201 regulator-max-microvolt = <1400000>;
317 regulator-boot 202 regulator-boot-on;
318 regulator-alwa 203 regulator-always-on;
319 }; 204 };
320 205
321 ldo1_reg: LDO1 { 206 ldo1_reg: LDO1 {
322 regulator-name 207 regulator-name = "ldo1";
323 regulator-min- 208 regulator-min-microvolt = <1600000>;
324 regulator-max- 209 regulator-max-microvolt = <3300000>;
325 regulator-boot 210 regulator-boot-on;
326 regulator-alwa 211 regulator-always-on;
327 }; 212 };
328 213
329 ldo2_reg: LDO2 { 214 ldo2_reg: LDO2 {
330 regulator-name 215 regulator-name = "ldo2";
331 regulator-min- 216 regulator-min-microvolt = <800000>;
332 regulator-max- 217 regulator-max-microvolt = <900000>;
333 regulator-boot 218 regulator-boot-on;
334 regulator-alwa 219 regulator-always-on;
335 }; 220 };
336 221
337 ldo3_reg: LDO3 { 222 ldo3_reg: LDO3 {
338 regulator-name 223 regulator-name = "ldo3";
339 regulator-min- 224 regulator-min-microvolt = <1800000>;
340 regulator-max- 225 regulator-max-microvolt = <3300000>;
341 regulator-boot 226 regulator-boot-on;
342 regulator-alwa 227 regulator-always-on;
343 }; 228 };
344 229
345 ldo4_reg: LDO4 { 230 ldo4_reg: LDO4 {
346 regulator-name 231 regulator-name = "ldo4";
347 regulator-min- 232 regulator-min-microvolt = <900000>;
348 regulator-max- 233 regulator-max-microvolt = <1800000>;
349 regulator-boot 234 regulator-boot-on;
350 regulator-alwa 235 regulator-always-on;
351 }; 236 };
352 237
353 ldo6_reg: LDO6 { 238 ldo6_reg: LDO6 {
354 regulator-name 239 regulator-name = "ldo6";
355 regulator-min- 240 regulator-min-microvolt = <900000>;
356 regulator-max- 241 regulator-max-microvolt = <1800000>;
357 regulator-boot 242 regulator-boot-on;
358 regulator-alwa 243 regulator-always-on;
359 }; 244 };
360 }; 245 };
361 }; 246 };
362 }; 247 };
363 248
364 &i2c2 { 249 &i2c2 {
365 clock-frequency = <400000>; 250 clock-frequency = <400000>;
366 pinctrl-names = "default"; 251 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c2>; 252 pinctrl-0 = <&pinctrl_i2c2>;
368 status = "okay"; 253 status = "okay";
369 254
370 hdmi@3d { <<
371 compatible = "adi,adv7535"; <<
372 reg = <0x3d>; <<
373 interrupt-parent = <&gpio1>; <<
374 interrupts = <9 IRQ_TYPE_EDGE_ <<
375 adi,dsi-lanes = <4>; <<
376 avdd-supply = <&buck5_reg>; <<
377 dvdd-supply = <&buck5_reg>; <<
378 pvdd-supply = <&buck5_reg>; <<
379 a2vdd-supply = <&buck5_reg>; <<
380 v3p3-supply = <®_vddext_3v3 <<
381 v1p2-supply = <&buck5_reg>; <<
382 <<
383 ports { <<
384 #address-cells = <1>; <<
385 #size-cells = <0>; <<
386 <<
387 port@0 { <<
388 reg = <0>; <<
389 <<
390 adv7535_in: en <<
391 remote <<
392 }; <<
393 }; <<
394 <<
395 port@1 { <<
396 reg = <1>; <<
397 <<
398 adv7535_out: e <<
399 remote <<
400 }; <<
401 }; <<
402 <<
403 }; <<
404 }; <<
405 <<
406 ptn5110: tcpc@50 { 255 ptn5110: tcpc@50 {
407 compatible = "nxp,ptn5110", "t !! 256 compatible = "nxp,ptn5110";
408 pinctrl-names = "default"; 257 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_typec1>; 258 pinctrl-0 = <&pinctrl_typec1>;
410 reg = <0x50>; 259 reg = <0x50>;
411 interrupt-parent = <&gpio2>; 260 interrupt-parent = <&gpio2>;
412 interrupts = <11 IRQ_TYPE_LEVE !! 261 interrupts = <11 8>;
413 status = "okay"; 262 status = "okay";
414 263
>> 264 port {
>> 265 typec1_dr_sw: endpoint {
>> 266 remote-endpoint = <&usb1_drd_sw>;
>> 267 };
>> 268 };
>> 269
415 typec1_con: connector { 270 typec1_con: connector {
416 compatible = "usb-c-co 271 compatible = "usb-c-connector";
417 label = "USB-C"; 272 label = "USB-C";
418 power-role = "dual"; 273 power-role = "dual";
419 data-role = "dual"; 274 data-role = "dual";
420 try-power-role = "sink 275 try-power-role = "sink";
421 source-pdos = <PDO_FIX 276 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
422 sink-pdos = <PDO_FIXED 277 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
423 PDO_VAR(5 278 PDO_VAR(5000, 20000, 3000)>;
424 op-sink-microwatt = <1 279 op-sink-microwatt = <15000000>;
425 self-powered; 280 self-powered;
426 <<
427 port { <<
428 typec1_dr_sw: <<
429 remote <<
430 }; <<
431 }; <<
432 }; 281 };
433 }; 282 };
434 }; 283 };
435 284
436 <<
437 &csi { <<
438 status = "okay"; <<
439 }; <<
440 <<
441 &i2c3 { 285 &i2c3 {
442 clock-frequency = <400000>; 286 clock-frequency = <400000>;
443 pinctrl-names = "default"; 287 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>; 288 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay"; 289 status = "okay";
446 290
447 pca6416: gpio@20 { 291 pca6416: gpio@20 {
448 compatible = "nxp,pca6416"; !! 292 compatible = "ti,tca6416";
449 reg = <0x20>; 293 reg = <0x20>;
450 gpio-controller; 294 gpio-controller;
451 #gpio-cells = <2>; 295 #gpio-cells = <2>;
452 vcc-supply = <&buck4_reg>; <<
453 }; <<
454 <<
455 camera@3c { <<
456 compatible = "ovti,ov5640"; <<
457 reg = <0x3c>; <<
458 pinctrl-names = "default"; <<
459 pinctrl-0 = <&pinctrl_camera>; <<
460 clocks = <&clk IMX8MM_CLK_CLKO <<
461 clock-names = "xclk"; <<
462 assigned-clocks = <&clk IMX8MM <<
463 assigned-clock-parents = <&clk <<
464 assigned-clock-rates = <240000 <<
465 powerdown-gpios = <&gpio1 7 GP <<
466 reset-gpios = <&gpio1 6 GPIO_A <<
467 DOVDD-supply = <&buck5_reg>; <<
468 AVDD-supply = <®_1v8>; <<
469 DVDD-supply = <®_1v5>; <<
470 <<
471 port { <<
472 ov5640_to_mipi_csi2: e <<
473 remote-endpoin <<
474 clock-lanes = <<
475 data-lanes = < <<
476 }; <<
477 }; <<
478 }; 296 };
479 }; 297 };
480 298
481 &lcdif { <<
482 status = "okay"; <<
483 }; <<
484 <<
485 &micfil { <<
486 #sound-dai-cells = <0>; <<
487 pinctrl-names = "default"; <<
488 pinctrl-0 = <&pinctrl_pdm>; <<
489 assigned-clocks = <&clk IMX8MM_CLK_PDM <<
490 assigned-clock-parents = <&clk IMX8MM_ <<
491 assigned-clock-rates = <196608000>; <<
492 status = "okay"; <<
493 }; <<
494 <<
495 &mipi_csi { <<
496 status = "okay"; <<
497 <<
498 ports { <<
499 port@0 { <<
500 imx8mm_mipi_csi_in: en <<
501 remote-endpoin <<
502 data-lanes = < <<
503 }; <<
504 }; <<
505 }; <<
506 }; <<
507 <<
508 &mipi_dsi { <<
509 samsung,esc-clock-frequency = <1000000 <<
510 status = "okay"; <<
511 <<
512 ports { <<
513 port@1 { <<
514 reg = <1>; <<
515 <<
516 dsi_out: endpoint { <<
517 remote-endpoin <<
518 data-lanes = < <<
519 }; <<
520 }; <<
521 }; <<
522 }; <<
523 <<
524 &pcie_phy { <<
525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
526 fsl,tx-deemph-gen1 = <0x2d>; <<
527 fsl,tx-deemph-gen2 = <0xf>; <<
528 clocks = <&pcie0_refclk>; <<
529 status = "okay"; <<
530 }; <<
531 <<
532 &pcie0 { <<
533 pinctrl-names = "default"; <<
534 pinctrl-0 = <&pinctrl_pcie0>; <<
535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LO <<
536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <<
537 <&clk IMX8MM_CLK_PCIE1_AUX>; <<
538 assigned-clocks = <&clk IMX8MM_CLK_PCI <<
539 <&clk IMX8MM_CLK_PCI <<
540 assigned-clock-rates = <10000000>, <25 <<
541 assigned-clock-parents = <&clk IMX8MM_ <<
542 <&clk IMX8MM_ <<
543 vpcie-supply = <®_pcie0>; <<
544 status = "okay"; <<
545 }; <<
546 <<
547 &sai2 { <<
548 #sound-dai-cells = <0>; <<
549 pinctrl-names = "default"; <<
550 pinctrl-0 = <&pinctrl_sai2>; <<
551 assigned-clocks = <&clk IMX8MM_CLK_SAI <<
552 assigned-clock-parents = <&clk IMX8MM_ <<
553 assigned-clock-rates = <24576000>; <<
554 status = "okay"; <<
555 }; <<
556 <<
557 &sai3 { 299 &sai3 {
558 pinctrl-names = "default"; 300 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_sai3>; 301 pinctrl-0 = <&pinctrl_sai3>;
560 assigned-clocks = <&clk IMX8MM_CLK_SAI 302 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
561 assigned-clock-parents = <&clk IMX8MM_ 303 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
562 assigned-clock-rates = <24576000>; 304 assigned-clock-rates = <24576000>;
563 status = "okay"; 305 status = "okay";
564 }; 306 };
565 307
566 &snvs_pwrkey { 308 &snvs_pwrkey {
567 status = "okay"; 309 status = "okay";
568 }; 310 };
569 311
570 &spdif1 { <<
571 pinctrl-names = "default"; <<
572 pinctrl-0 = <&pinctrl_spdif1>; <<
573 assigned-clocks = <&clk IMX8MM_CLK_SPD <<
574 assigned-clock-parents = <&clk IMX8MM_ <<
575 assigned-clock-rates = <24576000>; <<
576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <<
577 <&clk IMX8MM_CLK_SPDIF1>, <&c <<
578 <&clk IMX8MM_CLK_DUMMY>, <&cl <<
579 <&clk IMX8MM_CLK_AUDIO_AHB>, <<
580 <&clk IMX8MM_CLK_DUMMY>, <&cl <<
581 <&clk IMX8MM_AUDIO_PLL1_OUT>, <<
582 clock-names = "core", "rxtx0", "rxtx1" <<
583 "rxtx4", "rxtx5", "rxtx6 <<
584 "pll8k", "pll11k"; <<
585 status = "okay"; <<
586 }; <<
587 <<
588 &uart2 { /* console */ 312 &uart2 { /* console */
589 pinctrl-names = "default"; 313 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart2>; 314 pinctrl-0 = <&pinctrl_uart2>;
591 status = "okay"; 315 status = "okay";
592 }; 316 };
593 317
594 &usbphynop1 { <<
595 wakeup-source; <<
596 }; <<
597 <<
598 &usbotg1 { 318 &usbotg1 {
599 dr_mode = "otg"; 319 dr_mode = "otg";
600 hnp-disable; 320 hnp-disable;
601 srp-disable; 321 srp-disable;
602 adp-disable; 322 adp-disable;
603 usb-role-switch; 323 usb-role-switch;
604 disable-over-current; 324 disable-over-current;
605 samsung,picophy-pre-emp-curr-control = 325 samsung,picophy-pre-emp-curr-control = <3>;
606 samsung,picophy-dc-vol-level-adjust = 326 samsung,picophy-dc-vol-level-adjust = <7>;
607 status = "okay"; 327 status = "okay";
608 328
609 port { 329 port {
610 usb1_drd_sw: endpoint { 330 usb1_drd_sw: endpoint {
611 remote-endpoint = <&ty 331 remote-endpoint = <&typec1_dr_sw>;
612 }; 332 };
613 }; 333 };
614 }; 334 };
615 335
616 &usdhc2 { 336 &usdhc2 {
617 assigned-clocks = <&clk IMX8MM_CLK_USD 337 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
618 assigned-clock-rates = <200000000>; 338 assigned-clock-rates = <200000000>;
619 pinctrl-names = "default", "state_100m 339 pinctrl-names = "default", "state_100mhz", "state_200mhz";
620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 340 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 341 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 342 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 343 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
624 bus-width = <4>; 344 bus-width = <4>;
625 vmmc-supply = <®_usdhc2_vmmc>; 345 vmmc-supply = <®_usdhc2_vmmc>;
626 status = "okay"; 346 status = "okay";
627 }; 347 };
628 348
629 &wdog1 { 349 &wdog1 {
630 pinctrl-names = "default"; 350 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_wdog>; 351 pinctrl-0 = <&pinctrl_wdog>;
632 fsl,ext-reset-output; 352 fsl,ext-reset-output;
633 status = "okay"; 353 status = "okay";
634 }; 354 };
635 355
636 &pwm1 { <<
637 pinctrl-names = "default"; <<
638 pinctrl-0 = <&pinctrl_backlight>; <<
639 status = "okay"; <<
640 }; <<
641 <<
642 &iomuxc { 356 &iomuxc {
643 pinctrl_fec1: fec1grp { 357 pinctrl_fec1: fec1grp {
644 fsl,pins = < 358 fsl,pins = <
645 MX8MM_IOMUXC_ENET_MDC_ 359 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
646 MX8MM_IOMUXC_ENET_MDIO 360 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
647 MX8MM_IOMUXC_ENET_TD3_ 361 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
648 MX8MM_IOMUXC_ENET_TD2_ 362 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
649 MX8MM_IOMUXC_ENET_TD1_ 363 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
650 MX8MM_IOMUXC_ENET_TD0_ 364 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
651 MX8MM_IOMUXC_ENET_RD3_ 365 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
652 MX8MM_IOMUXC_ENET_RD2_ 366 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
653 MX8MM_IOMUXC_ENET_RD1_ 367 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
654 MX8MM_IOMUXC_ENET_RD0_ 368 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
655 MX8MM_IOMUXC_ENET_TXC_ 369 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
656 MX8MM_IOMUXC_ENET_RXC_ 370 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
657 MX8MM_IOMUXC_ENET_RX_C 371 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
658 MX8MM_IOMUXC_ENET_TX_C 372 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
659 MX8MM_IOMUXC_SAI2_RXC_ 373 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
660 >; 374 >;
661 }; 375 };
662 376
663 pinctrl_gpio_led: gpioledgrp { 377 pinctrl_gpio_led: gpioledgrp {
664 fsl,pins = < 378 fsl,pins = <
665 MX8MM_IOMUXC_NAND_READ 379 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
666 >; 380 >;
667 }; 381 };
668 382
669 pinctrl_ir: irgrp { 383 pinctrl_ir: irgrp {
670 fsl,pins = < 384 fsl,pins = <
671 MX8MM_IOMUXC_GPIO1_IO1 385 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
672 >; 386 >;
673 }; 387 };
674 388
675 pinctrl_gpio_wlf: gpiowlfgrp { 389 pinctrl_gpio_wlf: gpiowlfgrp {
676 fsl,pins = < 390 fsl,pins = <
677 MX8MM_IOMUXC_I2C4_SDA_ 391 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
678 >; 392 >;
679 }; 393 };
680 394
681 pinctrl_i2c1: i2c1grp { 395 pinctrl_i2c1: i2c1grp {
682 fsl,pins = < 396 fsl,pins = <
683 MX8MM_IOMUXC_I2C1_SCL_ 397 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
684 MX8MM_IOMUXC_I2C1_SDA_ 398 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
685 >; 399 >;
686 }; 400 };
687 401
688 pinctrl_i2c2: i2c2grp { 402 pinctrl_i2c2: i2c2grp {
689 fsl,pins = < 403 fsl,pins = <
690 MX8MM_IOMUXC_I2C2_SCL_ 404 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
691 MX8MM_IOMUXC_I2C2_SDA_ 405 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
692 >; 406 >;
693 }; 407 };
694 408
695 pinctrl_i2c3: i2c3grp { 409 pinctrl_i2c3: i2c3grp {
696 fsl,pins = < 410 fsl,pins = <
697 MX8MM_IOMUXC_I2C3_SCL_ 411 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
698 MX8MM_IOMUXC_I2C3_SDA_ 412 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
699 >; 413 >;
700 }; 414 };
701 415
702 pinctrl_pcie0: pcie0grp { <<
703 fsl,pins = < <<
704 MX8MM_IOMUXC_I2C4_SCL_ <<
705 MX8MM_IOMUXC_SAI2_RXFS <<
706 >; <<
707 }; <<
708 <<
709 pinctrl_pcie0_reg: pcie0reggrp { <<
710 fsl,pins = < <<
711 MX8MM_IOMUXC_GPIO1_IO0 <<
712 >; <<
713 }; <<
714 <<
715 pinctrl_pdm: pdmgrp { <<
716 fsl,pins = < <<
717 MX8MM_IOMUXC_SAI5_MCLK <<
718 MX8MM_IOMUXC_SAI5_RXC_ <<
719 MX8MM_IOMUXC_SAI5_RXFS <<
720 MX8MM_IOMUXC_SAI5_RXD0 <<
721 MX8MM_IOMUXC_SAI5_RXD1 <<
722 MX8MM_IOMUXC_SAI5_RXD2 <<
723 MX8MM_IOMUXC_SAI5_RXD3 <<
724 >; <<
725 }; <<
726 <<
727 pinctrl_pmic: pmicirqgrp { 416 pinctrl_pmic: pmicirqgrp {
728 fsl,pins = < 417 fsl,pins = <
729 MX8MM_IOMUXC_GPIO1_IO0 418 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
730 >; 419 >;
731 }; 420 };
732 421
733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 422 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
734 fsl,pins = < 423 fsl,pins = <
735 MX8MM_IOMUXC_SD2_RESET 424 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
736 >; 425 >;
737 }; 426 };
738 427
739 pinctrl_sai2: sai2grp { <<
740 fsl,pins = < <<
741 MX8MM_IOMUXC_SAI2_TXC_ <<
742 MX8MM_IOMUXC_SAI2_TXFS <<
743 MX8MM_IOMUXC_SAI2_TXD0 <<
744 MX8MM_IOMUXC_SAI2_RXD0 <<
745 >; <<
746 }; <<
747 <<
748 pinctrl_sai3: sai3grp { 428 pinctrl_sai3: sai3grp {
749 fsl,pins = < 429 fsl,pins = <
750 MX8MM_IOMUXC_SAI3_TXFS 430 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
751 MX8MM_IOMUXC_SAI3_TXC_ 431 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
752 MX8MM_IOMUXC_SAI3_MCLK 432 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
753 MX8MM_IOMUXC_SAI3_TXD_ 433 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
754 >; 434 >;
755 }; 435 };
756 436
757 pinctrl_spdif1: spdif1grp { <<
758 fsl,pins = < <<
759 MX8MM_IOMUXC_SPDIF_TX_ <<
760 MX8MM_IOMUXC_SPDIF_RX_ <<
761 >; <<
762 }; <<
763 <<
764 pinctrl_typec1: typec1grp { 437 pinctrl_typec1: typec1grp {
765 fsl,pins = < 438 fsl,pins = <
766 MX8MM_IOMUXC_SD1_STROB 439 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
767 >; 440 >;
768 }; 441 };
769 442
770 pinctrl_uart2: uart2grp { 443 pinctrl_uart2: uart2grp {
771 fsl,pins = < 444 fsl,pins = <
772 MX8MM_IOMUXC_UART2_RXD 445 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
773 MX8MM_IOMUXC_UART2_TXD 446 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
774 >; 447 >;
775 }; 448 };
776 449
777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp 450 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
778 fsl,pins = < 451 fsl,pins = <
779 MX8MM_IOMUXC_GPIO1_IO1 452 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
780 >; 453 >;
781 }; 454 };
782 455
783 pinctrl_usdhc2: usdhc2grp { 456 pinctrl_usdhc2: usdhc2grp {
784 fsl,pins = < 457 fsl,pins = <
785 MX8MM_IOMUXC_SD2_CLK_U 458 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
786 MX8MM_IOMUXC_SD2_CMD_U 459 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
787 MX8MM_IOMUXC_SD2_DATA0 460 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
788 MX8MM_IOMUXC_SD2_DATA1 461 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
789 MX8MM_IOMUXC_SD2_DATA2 462 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
790 MX8MM_IOMUXC_SD2_DATA3 463 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
791 MX8MM_IOMUXC_GPIO1_IO0 464 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
792 >; 465 >;
793 }; 466 };
794 467
795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 468 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
796 fsl,pins = < 469 fsl,pins = <
797 MX8MM_IOMUXC_SD2_CLK_U 470 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
798 MX8MM_IOMUXC_SD2_CMD_U 471 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
799 MX8MM_IOMUXC_SD2_DATA0 472 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
800 MX8MM_IOMUXC_SD2_DATA1 473 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
801 MX8MM_IOMUXC_SD2_DATA2 474 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
802 MX8MM_IOMUXC_SD2_DATA3 475 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
803 MX8MM_IOMUXC_GPIO1_IO0 476 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
804 >; 477 >;
805 }; 478 };
806 479
807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 480 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
808 fsl,pins = < 481 fsl,pins = <
809 MX8MM_IOMUXC_SD2_CLK_U 482 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
810 MX8MM_IOMUXC_SD2_CMD_U 483 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
811 MX8MM_IOMUXC_SD2_DATA0 484 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
812 MX8MM_IOMUXC_SD2_DATA1 485 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
813 MX8MM_IOMUXC_SD2_DATA2 486 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
814 MX8MM_IOMUXC_SD2_DATA3 487 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
815 MX8MM_IOMUXC_GPIO1_IO0 488 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 489 >;
817 }; 490 };
818 491
819 pinctrl_wdog: wdoggrp { 492 pinctrl_wdog: wdoggrp {
820 fsl,pins = < 493 fsl,pins = <
821 MX8MM_IOMUXC_GPIO1_IO0 494 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
822 >; <<
823 }; <<
824 <<
825 pinctrl_backlight: backlightgrp { <<
826 fsl,pins = < <<
827 MX8MM_IOMUXC_GPIO1_IO0 <<
828 >; <<
829 }; <<
830 <<
831 pinctrl_camera: cameragrp { <<
832 fsl,pins = < <<
833 MX8MM_IOMUXC_GPIO1_IO0 <<
834 MX8MM_IOMUXC_GPIO1_IO0 <<
835 MX8MM_IOMUXC_GPIO1_IO1 <<
836 >; 495 >;
837 }; 496 };
838 }; 497 };
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