1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi" 10 #include "imx8mm.dtsi"
11 11
12 / { 12 / {
13 chosen { 13 chosen {
14 stdout-path = &uart2; 14 stdout-path = &uart2;
15 }; 15 };
16 16
17 memory@40000000 { 17 memory@40000000 {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x8000 19 reg = <0x0 0x40000000 0 0x80000000>;
20 }; 20 };
21 21
22 hdmi-connector { <<
23 compatible = "hdmi-connector"; <<
24 label = "hdmi"; <<
25 type = "a"; <<
26 <<
27 port { <<
28 hdmi_connector_in: end <<
29 remote-endpoin <<
30 }; <<
31 }; <<
32 }; <<
33 <<
34 leds { 22 leds {
35 compatible = "gpio-leds"; 23 compatible = "gpio-leds";
36 pinctrl-names = "default"; 24 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led 25 pinctrl-0 = <&pinctrl_gpio_led>;
38 26
39 status { 27 status {
40 label = "status"; 28 label = "status";
41 gpios = <&gpio3 16 GPI 29 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on"; 30 default-state = "on";
43 }; 31 };
44 }; 32 };
45 33
46 pcie0_refclk: pcie0-refclk { 34 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
48 #clock-cells = <0>; 36 #clock-cells = <0>;
49 clock-frequency = <100000000>; 37 clock-frequency = <100000000>;
50 }; 38 };
51 39
52 reg_pcie0: regulator-pcie { 40 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed" 41 compatible = "regulator-fixed";
54 pinctrl-names = "default"; 42 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_re 43 pinctrl-0 = <&pinctrl_pcie0_reg>;
56 regulator-name = "MPCIE_3V3"; 44 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <330 45 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <330 46 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio1 5 GPIO_ACTIVE_H 47 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
60 enable-active-high; 48 enable-active-high;
61 }; 49 };
62 50
63 reg_usdhc2_vmmc: regulator-usdhc2 { 51 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed" 52 compatible = "regulator-fixed";
65 pinctrl-names = "default"; 53 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdh 54 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3"; 55 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <330 56 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <330 57 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_ 58 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>; 59 off-on-delay-us = <20000>;
72 enable-active-high; 60 enable-active-high;
73 }; 61 };
74 62
75 reg_1v5: regulator-1v5 { <<
76 compatible = "regulator-fixed" <<
77 regulator-name = "VDD_1V5"; <<
78 regulator-min-microvolt = <150 <<
79 regulator-max-microvolt = <150 <<
80 }; <<
81 <<
82 reg_1v8: regulator-1v8 { <<
83 compatible = "regulator-fixed" <<
84 regulator-name = "VDD_1V8"; <<
85 regulator-min-microvolt = <180 <<
86 regulator-max-microvolt = <180 <<
87 }; <<
88 <<
89 reg_vddext_3v3: regulator-vddext-3v3 { <<
90 compatible = "regulator-fixed" <<
91 regulator-name = "VDDEXT_3V3"; <<
92 regulator-min-microvolt = <330 <<
93 regulator-max-microvolt = <330 <<
94 }; <<
95 <<
96 backlight: backlight { 63 backlight: backlight {
97 compatible = "pwm-backlight"; 64 compatible = "pwm-backlight";
98 pwms = <&pwm1 0 5000000 0>; 65 pwms = <&pwm1 0 5000000 0>;
99 brightness-levels = <0 255>; 66 brightness-levels = <0 255>;
100 num-interpolated-steps = <255> 67 num-interpolated-steps = <255>;
101 default-brightness-level = <25 68 default-brightness-level = <250>;
102 }; 69 };
103 70
104 ir-receiver { 71 ir-receiver {
105 compatible = "gpio-ir-receiver 72 compatible = "gpio-ir-receiver";
106 gpios = <&gpio1 13 GPIO_ACTIVE 73 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
107 pinctrl-names = "default"; 74 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_ir>; 75 pinctrl-0 = <&pinctrl_ir>;
109 linux,autosuspend-period = <12 76 linux,autosuspend-period = <125>;
110 }; 77 };
111 78
112 audio_codec_bt_sco: audio-codec-bt-sco 79 audio_codec_bt_sco: audio-codec-bt-sco {
113 compatible = "linux,bt-sco"; 80 compatible = "linux,bt-sco";
114 #sound-dai-cells = <1>; 81 #sound-dai-cells = <1>;
115 }; 82 };
116 83
117 wm8524: audio-codec { 84 wm8524: audio-codec {
118 #sound-dai-cells = <0>; 85 #sound-dai-cells = <0>;
119 compatible = "wlf,wm8524"; 86 compatible = "wlf,wm8524";
120 pinctrl-names = "default"; 87 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_gpio_wlf 88 pinctrl-0 = <&pinctrl_gpio_wlf>;
122 wlf,mute-gpios = <&gpio5 21 GP 89 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
123 }; 90 };
124 91
125 sound-bt-sco { 92 sound-bt-sco {
126 compatible = "simple-audio-car 93 compatible = "simple-audio-card";
127 simple-audio-card,name = "bt-s 94 simple-audio-card,name = "bt-sco-audio";
128 simple-audio-card,format = "ds 95 simple-audio-card,format = "dsp_a";
129 simple-audio-card,bitclock-inv 96 simple-audio-card,bitclock-inversion;
130 simple-audio-card,frame-master 97 simple-audio-card,frame-master = <&btcpu>;
131 simple-audio-card,bitclock-mas 98 simple-audio-card,bitclock-master = <&btcpu>;
132 99
133 btcpu: simple-audio-card,cpu { 100 btcpu: simple-audio-card,cpu {
134 sound-dai = <&sai2>; 101 sound-dai = <&sai2>;
135 dai-tdm-slot-num = <2> 102 dai-tdm-slot-num = <2>;
136 dai-tdm-slot-width = < 103 dai-tdm-slot-width = <16>;
137 }; 104 };
138 105
139 simple-audio-card,codec { 106 simple-audio-card,codec {
140 sound-dai = <&audio_co 107 sound-dai = <&audio_codec_bt_sco 1>;
141 }; 108 };
142 }; 109 };
143 110
144 sound-wm8524 { 111 sound-wm8524 {
145 compatible = "simple-audio-car 112 compatible = "simple-audio-card";
146 simple-audio-card,name = "wm85 113 simple-audio-card,name = "wm8524-audio";
147 simple-audio-card,format = "i2 114 simple-audio-card,format = "i2s";
148 simple-audio-card,frame-master 115 simple-audio-card,frame-master = <&cpudai>;
149 simple-audio-card,bitclock-mas 116 simple-audio-card,bitclock-master = <&cpudai>;
150 simple-audio-card,widgets = 117 simple-audio-card,widgets =
151 "Line", "Left Line Out 118 "Line", "Left Line Out Jack",
152 "Line", "Right Line Ou 119 "Line", "Right Line Out Jack";
153 simple-audio-card,routing = 120 simple-audio-card,routing =
154 "Left Line Out Jack", 121 "Left Line Out Jack", "LINEVOUTL",
155 "Right Line Out Jack", 122 "Right Line Out Jack", "LINEVOUTR";
156 123
157 cpudai: simple-audio-card,cpu 124 cpudai: simple-audio-card,cpu {
158 sound-dai = <&sai3>; 125 sound-dai = <&sai3>;
159 dai-tdm-slot-num = <2> 126 dai-tdm-slot-num = <2>;
160 dai-tdm-slot-width = < 127 dai-tdm-slot-width = <32>;
161 }; 128 };
162 129
163 simple-audio-card,codec { 130 simple-audio-card,codec {
164 sound-dai = <&wm8524>; 131 sound-dai = <&wm8524>;
165 clocks = <&clk IMX8MM_ 132 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
166 }; 133 };
167 }; 134 };
168 <<
169 sound-micfil { <<
170 compatible = "fsl,imx-audio-ca <<
171 model = "micfil-audio"; <<
172 <<
173 pri-dai-link { <<
174 link-name = "micfil hi <<
175 format = "i2s"; <<
176 <<
177 cpu { <<
178 sound-dai = <& <<
179 }; <<
180 }; <<
181 }; <<
182 <<
183 spdif_out: spdif-out { <<
184 compatible = "linux,spdif-dit" <<
185 #sound-dai-cells = <0>; <<
186 }; <<
187 <<
188 spdif_in: spdif-in { <<
189 compatible = "linux,spdif-dir" <<
190 #sound-dai-cells = <0>; <<
191 }; <<
192 <<
193 sound-spdif { <<
194 compatible = "fsl,imx-audio-sp <<
195 model = "imx-spdif"; <<
196 audio-cpu = <&spdif1>; <<
197 audio-codec = <&spdif_out>, <& <<
198 }; <<
199 }; 135 };
200 136
201 &A53_0 { 137 &A53_0 {
202 cpu-supply = <&buck2_reg>; 138 cpu-supply = <&buck2_reg>;
203 }; 139 };
204 140
205 &A53_1 { 141 &A53_1 {
206 cpu-supply = <&buck2_reg>; 142 cpu-supply = <&buck2_reg>;
207 }; 143 };
208 144
209 &A53_2 { 145 &A53_2 {
210 cpu-supply = <&buck2_reg>; 146 cpu-supply = <&buck2_reg>;
211 }; 147 };
212 148
213 &A53_3 { 149 &A53_3 {
214 cpu-supply = <&buck2_reg>; 150 cpu-supply = <&buck2_reg>;
215 }; 151 };
216 152
217 &fec1 { 153 &fec1 {
218 pinctrl-names = "default"; 154 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec1>; 155 pinctrl-0 = <&pinctrl_fec1>;
220 phy-mode = "rgmii-id"; 156 phy-mode = "rgmii-id";
221 phy-handle = <ðphy0>; 157 phy-handle = <ðphy0>;
222 fsl,magic-packet; 158 fsl,magic-packet;
223 status = "okay"; 159 status = "okay";
224 160
225 mdio { 161 mdio {
226 #address-cells = <1>; 162 #address-cells = <1>;
227 #size-cells = <0>; 163 #size-cells = <0>;
228 164
229 ethphy0: ethernet-phy@0 { 165 ethphy0: ethernet-phy@0 {
230 compatible = "ethernet 166 compatible = "ethernet-phy-ieee802.3-c22";
231 reg = <0>; 167 reg = <0>;
232 reset-gpios = <&gpio4 168 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
233 reset-assert-us = <100 169 reset-assert-us = <10000>;
234 qca,disable-smarteee; 170 qca,disable-smarteee;
235 vddio-supply = <&vddio 171 vddio-supply = <&vddio>;
236 172
237 vddio: vddio-regulator 173 vddio: vddio-regulator {
238 regulator-min- 174 regulator-min-microvolt = <1800000>;
239 regulator-max- 175 regulator-max-microvolt = <1800000>;
240 }; 176 };
241 }; 177 };
242 }; 178 };
243 }; 179 };
244 180
245 &i2c1 { 181 &i2c1 {
246 clock-frequency = <400000>; 182 clock-frequency = <400000>;
247 pinctrl-names = "default"; 183 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>; 184 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay"; 185 status = "okay";
250 186
251 pmic@4b { 187 pmic@4b {
252 compatible = "rohm,bd71847"; 188 compatible = "rohm,bd71847";
253 reg = <0x4b>; 189 reg = <0x4b>;
254 pinctrl-names = "default"; 190 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_pmic>; 191 pinctrl-0 = <&pinctrl_pmic>;
256 interrupt-parent = <&gpio1>; 192 interrupt-parent = <&gpio1>;
257 interrupts = <3 IRQ_TYPE_LEVEL 193 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
258 rohm,reset-snvs-powered; 194 rohm,reset-snvs-powered;
259 195
260 #clock-cells = <0>; 196 #clock-cells = <0>;
261 clocks = <&osc_32k>; 197 clocks = <&osc_32k>;
262 clock-output-names = "clk-32k- 198 clock-output-names = "clk-32k-out";
263 199
264 regulators { 200 regulators {
265 buck1_reg: BUCK1 { 201 buck1_reg: BUCK1 {
266 regulator-name 202 regulator-name = "buck1";
267 regulator-min- 203 regulator-min-microvolt = <700000>;
268 regulator-max- 204 regulator-max-microvolt = <1300000>;
269 regulator-boot 205 regulator-boot-on;
270 regulator-alwa 206 regulator-always-on;
271 regulator-ramp 207 regulator-ramp-delay = <1250>;
272 }; 208 };
273 209
274 buck2_reg: BUCK2 { 210 buck2_reg: BUCK2 {
275 regulator-name 211 regulator-name = "buck2";
276 regulator-min- 212 regulator-min-microvolt = <700000>;
277 regulator-max- 213 regulator-max-microvolt = <1300000>;
278 regulator-boot 214 regulator-boot-on;
279 regulator-alwa 215 regulator-always-on;
280 regulator-ramp 216 regulator-ramp-delay = <1250>;
281 rohm,dvs-run-v 217 rohm,dvs-run-voltage = <1000000>;
282 rohm,dvs-idle- 218 rohm,dvs-idle-voltage = <900000>;
283 }; 219 };
284 220
285 buck3_reg: BUCK3 { 221 buck3_reg: BUCK3 {
286 // BUCK5 in da 222 // BUCK5 in datasheet
287 regulator-name 223 regulator-name = "buck3";
288 regulator-min- 224 regulator-min-microvolt = <700000>;
289 regulator-max- 225 regulator-max-microvolt = <1350000>;
290 regulator-boot 226 regulator-boot-on;
291 regulator-alwa 227 regulator-always-on;
292 }; 228 };
293 229
294 buck4_reg: BUCK4 { 230 buck4_reg: BUCK4 {
295 // BUCK6 in da 231 // BUCK6 in datasheet
296 regulator-name 232 regulator-name = "buck4";
297 regulator-min- 233 regulator-min-microvolt = <3000000>;
298 regulator-max- 234 regulator-max-microvolt = <3300000>;
299 regulator-boot 235 regulator-boot-on;
300 regulator-alwa 236 regulator-always-on;
301 }; 237 };
302 238
303 buck5_reg: BUCK5 { 239 buck5_reg: BUCK5 {
304 // BUCK7 in da 240 // BUCK7 in datasheet
305 regulator-name 241 regulator-name = "buck5";
306 regulator-min- 242 regulator-min-microvolt = <1605000>;
307 regulator-max- 243 regulator-max-microvolt = <1995000>;
308 regulator-boot 244 regulator-boot-on;
309 regulator-alwa 245 regulator-always-on;
310 }; 246 };
311 247
312 buck6_reg: BUCK6 { 248 buck6_reg: BUCK6 {
313 // BUCK8 in da 249 // BUCK8 in datasheet
314 regulator-name 250 regulator-name = "buck6";
315 regulator-min- 251 regulator-min-microvolt = <800000>;
316 regulator-max- 252 regulator-max-microvolt = <1400000>;
317 regulator-boot 253 regulator-boot-on;
318 regulator-alwa 254 regulator-always-on;
319 }; 255 };
320 256
321 ldo1_reg: LDO1 { 257 ldo1_reg: LDO1 {
322 regulator-name 258 regulator-name = "ldo1";
323 regulator-min- 259 regulator-min-microvolt = <1600000>;
324 regulator-max- 260 regulator-max-microvolt = <3300000>;
325 regulator-boot 261 regulator-boot-on;
326 regulator-alwa 262 regulator-always-on;
327 }; 263 };
328 264
329 ldo2_reg: LDO2 { 265 ldo2_reg: LDO2 {
330 regulator-name 266 regulator-name = "ldo2";
331 regulator-min- 267 regulator-min-microvolt = <800000>;
332 regulator-max- 268 regulator-max-microvolt = <900000>;
333 regulator-boot 269 regulator-boot-on;
334 regulator-alwa 270 regulator-always-on;
335 }; 271 };
336 272
337 ldo3_reg: LDO3 { 273 ldo3_reg: LDO3 {
338 regulator-name 274 regulator-name = "ldo3";
339 regulator-min- 275 regulator-min-microvolt = <1800000>;
340 regulator-max- 276 regulator-max-microvolt = <3300000>;
341 regulator-boot 277 regulator-boot-on;
342 regulator-alwa 278 regulator-always-on;
343 }; 279 };
344 280
345 ldo4_reg: LDO4 { 281 ldo4_reg: LDO4 {
346 regulator-name 282 regulator-name = "ldo4";
347 regulator-min- 283 regulator-min-microvolt = <900000>;
348 regulator-max- 284 regulator-max-microvolt = <1800000>;
349 regulator-boot 285 regulator-boot-on;
350 regulator-alwa 286 regulator-always-on;
351 }; 287 };
352 288
353 ldo6_reg: LDO6 { 289 ldo6_reg: LDO6 {
354 regulator-name 290 regulator-name = "ldo6";
355 regulator-min- 291 regulator-min-microvolt = <900000>;
356 regulator-max- 292 regulator-max-microvolt = <1800000>;
357 regulator-boot 293 regulator-boot-on;
358 regulator-alwa 294 regulator-always-on;
359 }; 295 };
360 }; 296 };
361 }; 297 };
362 }; 298 };
363 299
364 &i2c2 { 300 &i2c2 {
365 clock-frequency = <400000>; 301 clock-frequency = <400000>;
366 pinctrl-names = "default"; 302 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c2>; 303 pinctrl-0 = <&pinctrl_i2c2>;
368 status = "okay"; 304 status = "okay";
369 305
370 hdmi@3d { <<
371 compatible = "adi,adv7535"; <<
372 reg = <0x3d>; <<
373 interrupt-parent = <&gpio1>; <<
374 interrupts = <9 IRQ_TYPE_EDGE_ <<
375 adi,dsi-lanes = <4>; <<
376 avdd-supply = <&buck5_reg>; <<
377 dvdd-supply = <&buck5_reg>; <<
378 pvdd-supply = <&buck5_reg>; <<
379 a2vdd-supply = <&buck5_reg>; <<
380 v3p3-supply = <®_vddext_3v3 <<
381 v1p2-supply = <&buck5_reg>; <<
382 <<
383 ports { <<
384 #address-cells = <1>; <<
385 #size-cells = <0>; <<
386 <<
387 port@0 { <<
388 reg = <0>; <<
389 <<
390 adv7535_in: en <<
391 remote <<
392 }; <<
393 }; <<
394 <<
395 port@1 { <<
396 reg = <1>; <<
397 <<
398 adv7535_out: e <<
399 remote <<
400 }; <<
401 }; <<
402 <<
403 }; <<
404 }; <<
405 <<
406 ptn5110: tcpc@50 { 306 ptn5110: tcpc@50 {
407 compatible = "nxp,ptn5110", "t !! 307 compatible = "nxp,ptn5110";
408 pinctrl-names = "default"; 308 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_typec1>; 309 pinctrl-0 = <&pinctrl_typec1>;
410 reg = <0x50>; 310 reg = <0x50>;
411 interrupt-parent = <&gpio2>; 311 interrupt-parent = <&gpio2>;
412 interrupts = <11 IRQ_TYPE_LEVE !! 312 interrupts = <11 8>;
413 status = "okay"; 313 status = "okay";
414 314
>> 315 port {
>> 316 typec1_dr_sw: endpoint {
>> 317 remote-endpoint = <&usb1_drd_sw>;
>> 318 };
>> 319 };
>> 320
415 typec1_con: connector { 321 typec1_con: connector {
416 compatible = "usb-c-co 322 compatible = "usb-c-connector";
417 label = "USB-C"; 323 label = "USB-C";
418 power-role = "dual"; 324 power-role = "dual";
419 data-role = "dual"; 325 data-role = "dual";
420 try-power-role = "sink 326 try-power-role = "sink";
421 source-pdos = <PDO_FIX 327 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
422 sink-pdos = <PDO_FIXED 328 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
423 PDO_VAR(5 329 PDO_VAR(5000, 20000, 3000)>;
424 op-sink-microwatt = <1 330 op-sink-microwatt = <15000000>;
425 self-powered; 331 self-powered;
426 <<
427 port { <<
428 typec1_dr_sw: <<
429 remote <<
430 }; <<
431 }; <<
432 }; 332 };
433 }; 333 };
434 }; 334 };
435 335
436 <<
437 &csi { <<
438 status = "okay"; <<
439 }; <<
440 <<
441 &i2c3 { 336 &i2c3 {
442 clock-frequency = <400000>; 337 clock-frequency = <400000>;
443 pinctrl-names = "default"; 338 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>; 339 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay"; 340 status = "okay";
446 341
447 pca6416: gpio@20 { 342 pca6416: gpio@20 {
448 compatible = "nxp,pca6416"; 343 compatible = "nxp,pca6416";
449 reg = <0x20>; 344 reg = <0x20>;
450 gpio-controller; 345 gpio-controller;
451 #gpio-cells = <2>; 346 #gpio-cells = <2>;
452 vcc-supply = <&buck4_reg>; 347 vcc-supply = <&buck4_reg>;
453 }; 348 };
454 <<
455 camera@3c { <<
456 compatible = "ovti,ov5640"; <<
457 reg = <0x3c>; <<
458 pinctrl-names = "default"; <<
459 pinctrl-0 = <&pinctrl_camera>; <<
460 clocks = <&clk IMX8MM_CLK_CLKO <<
461 clock-names = "xclk"; <<
462 assigned-clocks = <&clk IMX8MM <<
463 assigned-clock-parents = <&clk <<
464 assigned-clock-rates = <240000 <<
465 powerdown-gpios = <&gpio1 7 GP <<
466 reset-gpios = <&gpio1 6 GPIO_A <<
467 DOVDD-supply = <&buck5_reg>; <<
468 AVDD-supply = <®_1v8>; <<
469 DVDD-supply = <®_1v5>; <<
470 <<
471 port { <<
472 ov5640_to_mipi_csi2: e <<
473 remote-endpoin <<
474 clock-lanes = <<
475 data-lanes = < <<
476 }; <<
477 }; <<
478 }; <<
479 }; <<
480 <<
481 &lcdif { <<
482 status = "okay"; <<
483 }; <<
484 <<
485 &micfil { <<
486 #sound-dai-cells = <0>; <<
487 pinctrl-names = "default"; <<
488 pinctrl-0 = <&pinctrl_pdm>; <<
489 assigned-clocks = <&clk IMX8MM_CLK_PDM <<
490 assigned-clock-parents = <&clk IMX8MM_ <<
491 assigned-clock-rates = <196608000>; <<
492 status = "okay"; <<
493 }; <<
494 <<
495 &mipi_csi { <<
496 status = "okay"; <<
497 <<
498 ports { <<
499 port@0 { <<
500 imx8mm_mipi_csi_in: en <<
501 remote-endpoin <<
502 data-lanes = < <<
503 }; <<
504 }; <<
505 }; <<
506 }; <<
507 <<
508 &mipi_dsi { <<
509 samsung,esc-clock-frequency = <1000000 <<
510 status = "okay"; <<
511 <<
512 ports { <<
513 port@1 { <<
514 reg = <1>; <<
515 <<
516 dsi_out: endpoint { <<
517 remote-endpoin <<
518 data-lanes = < <<
519 }; <<
520 }; <<
521 }; <<
522 }; 349 };
523 350
524 &pcie_phy { 351 &pcie_phy {
525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 352 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
526 fsl,tx-deemph-gen1 = <0x2d>; 353 fsl,tx-deemph-gen1 = <0x2d>;
527 fsl,tx-deemph-gen2 = <0xf>; 354 fsl,tx-deemph-gen2 = <0xf>;
528 clocks = <&pcie0_refclk>; 355 clocks = <&pcie0_refclk>;
529 status = "okay"; 356 status = "okay";
530 }; 357 };
531 358
532 &pcie0 { 359 &pcie0 {
533 pinctrl-names = "default"; 360 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_pcie0>; 361 pinctrl-0 = <&pinctrl_pcie0>;
535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LO 362 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 363 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
537 <&clk IMX8MM_CLK_PCIE1_AUX>; 364 <&clk IMX8MM_CLK_PCIE1_AUX>;
538 assigned-clocks = <&clk IMX8MM_CLK_PCI 365 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
539 <&clk IMX8MM_CLK_PCI 366 <&clk IMX8MM_CLK_PCIE1_CTRL>;
540 assigned-clock-rates = <10000000>, <25 367 assigned-clock-rates = <10000000>, <250000000>;
541 assigned-clock-parents = <&clk IMX8MM_ 368 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
542 <&clk IMX8MM_ 369 <&clk IMX8MM_SYS_PLL2_250M>;
543 vpcie-supply = <®_pcie0>; 370 vpcie-supply = <®_pcie0>;
544 status = "okay"; 371 status = "okay";
545 }; 372 };
546 373
547 &sai2 { 374 &sai2 {
548 #sound-dai-cells = <0>; 375 #sound-dai-cells = <0>;
549 pinctrl-names = "default"; 376 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_sai2>; 377 pinctrl-0 = <&pinctrl_sai2>;
551 assigned-clocks = <&clk IMX8MM_CLK_SAI 378 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
552 assigned-clock-parents = <&clk IMX8MM_ 379 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
553 assigned-clock-rates = <24576000>; 380 assigned-clock-rates = <24576000>;
554 status = "okay"; 381 status = "okay";
555 }; 382 };
556 383
557 &sai3 { 384 &sai3 {
558 pinctrl-names = "default"; 385 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_sai3>; 386 pinctrl-0 = <&pinctrl_sai3>;
560 assigned-clocks = <&clk IMX8MM_CLK_SAI 387 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
561 assigned-clock-parents = <&clk IMX8MM_ 388 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
562 assigned-clock-rates = <24576000>; 389 assigned-clock-rates = <24576000>;
563 status = "okay"; 390 status = "okay";
564 }; 391 };
565 392
566 &snvs_pwrkey { 393 &snvs_pwrkey {
567 status = "okay"; 394 status = "okay";
568 }; 395 };
569 396
570 &spdif1 { <<
571 pinctrl-names = "default"; <<
572 pinctrl-0 = <&pinctrl_spdif1>; <<
573 assigned-clocks = <&clk IMX8MM_CLK_SPD <<
574 assigned-clock-parents = <&clk IMX8MM_ <<
575 assigned-clock-rates = <24576000>; <<
576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <<
577 <&clk IMX8MM_CLK_SPDIF1>, <&c <<
578 <&clk IMX8MM_CLK_DUMMY>, <&cl <<
579 <&clk IMX8MM_CLK_AUDIO_AHB>, <<
580 <&clk IMX8MM_CLK_DUMMY>, <&cl <<
581 <&clk IMX8MM_AUDIO_PLL1_OUT>, <<
582 clock-names = "core", "rxtx0", "rxtx1" <<
583 "rxtx4", "rxtx5", "rxtx6 <<
584 "pll8k", "pll11k"; <<
585 status = "okay"; <<
586 }; <<
587 <<
588 &uart2 { /* console */ 397 &uart2 { /* console */
589 pinctrl-names = "default"; 398 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart2>; 399 pinctrl-0 = <&pinctrl_uart2>;
591 status = "okay"; 400 status = "okay";
592 }; 401 };
593 402
594 &usbphynop1 { 403 &usbphynop1 {
595 wakeup-source; 404 wakeup-source;
596 }; 405 };
597 406
598 &usbotg1 { 407 &usbotg1 {
599 dr_mode = "otg"; 408 dr_mode = "otg";
600 hnp-disable; 409 hnp-disable;
601 srp-disable; 410 srp-disable;
602 adp-disable; 411 adp-disable;
603 usb-role-switch; 412 usb-role-switch;
604 disable-over-current; 413 disable-over-current;
605 samsung,picophy-pre-emp-curr-control = 414 samsung,picophy-pre-emp-curr-control = <3>;
606 samsung,picophy-dc-vol-level-adjust = 415 samsung,picophy-dc-vol-level-adjust = <7>;
607 status = "okay"; 416 status = "okay";
608 417
609 port { 418 port {
610 usb1_drd_sw: endpoint { 419 usb1_drd_sw: endpoint {
611 remote-endpoint = <&ty 420 remote-endpoint = <&typec1_dr_sw>;
612 }; 421 };
613 }; 422 };
614 }; 423 };
615 424
616 &usdhc2 { 425 &usdhc2 {
617 assigned-clocks = <&clk IMX8MM_CLK_USD 426 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
618 assigned-clock-rates = <200000000>; 427 assigned-clock-rates = <200000000>;
619 pinctrl-names = "default", "state_100m 428 pinctrl-names = "default", "state_100mhz", "state_200mhz";
620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 429 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 430 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 431 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 432 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
624 bus-width = <4>; 433 bus-width = <4>;
625 vmmc-supply = <®_usdhc2_vmmc>; 434 vmmc-supply = <®_usdhc2_vmmc>;
626 status = "okay"; 435 status = "okay";
627 }; 436 };
628 437
629 &wdog1 { 438 &wdog1 {
630 pinctrl-names = "default"; 439 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_wdog>; 440 pinctrl-0 = <&pinctrl_wdog>;
632 fsl,ext-reset-output; 441 fsl,ext-reset-output;
633 status = "okay"; 442 status = "okay";
634 }; 443 };
635 444
636 &pwm1 { 445 &pwm1 {
637 pinctrl-names = "default"; 446 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_backlight>; 447 pinctrl-0 = <&pinctrl_backlight>;
639 status = "okay"; 448 status = "okay";
640 }; 449 };
641 450
642 &iomuxc { 451 &iomuxc {
643 pinctrl_fec1: fec1grp { 452 pinctrl_fec1: fec1grp {
644 fsl,pins = < 453 fsl,pins = <
645 MX8MM_IOMUXC_ENET_MDC_ 454 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
646 MX8MM_IOMUXC_ENET_MDIO 455 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
647 MX8MM_IOMUXC_ENET_TD3_ 456 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
648 MX8MM_IOMUXC_ENET_TD2_ 457 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
649 MX8MM_IOMUXC_ENET_TD1_ 458 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
650 MX8MM_IOMUXC_ENET_TD0_ 459 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
651 MX8MM_IOMUXC_ENET_RD3_ 460 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
652 MX8MM_IOMUXC_ENET_RD2_ 461 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
653 MX8MM_IOMUXC_ENET_RD1_ 462 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
654 MX8MM_IOMUXC_ENET_RD0_ 463 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
655 MX8MM_IOMUXC_ENET_TXC_ 464 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
656 MX8MM_IOMUXC_ENET_RXC_ 465 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
657 MX8MM_IOMUXC_ENET_RX_C 466 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
658 MX8MM_IOMUXC_ENET_TX_C 467 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
659 MX8MM_IOMUXC_SAI2_RXC_ 468 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
660 >; 469 >;
661 }; 470 };
662 471
663 pinctrl_gpio_led: gpioledgrp { 472 pinctrl_gpio_led: gpioledgrp {
664 fsl,pins = < 473 fsl,pins = <
665 MX8MM_IOMUXC_NAND_READ 474 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
666 >; 475 >;
667 }; 476 };
668 477
669 pinctrl_ir: irgrp { 478 pinctrl_ir: irgrp {
670 fsl,pins = < 479 fsl,pins = <
671 MX8MM_IOMUXC_GPIO1_IO1 480 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
672 >; 481 >;
673 }; 482 };
674 483
675 pinctrl_gpio_wlf: gpiowlfgrp { 484 pinctrl_gpio_wlf: gpiowlfgrp {
676 fsl,pins = < 485 fsl,pins = <
677 MX8MM_IOMUXC_I2C4_SDA_ 486 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
678 >; 487 >;
679 }; 488 };
680 489
681 pinctrl_i2c1: i2c1grp { 490 pinctrl_i2c1: i2c1grp {
682 fsl,pins = < 491 fsl,pins = <
683 MX8MM_IOMUXC_I2C1_SCL_ 492 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
684 MX8MM_IOMUXC_I2C1_SDA_ 493 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
685 >; 494 >;
686 }; 495 };
687 496
688 pinctrl_i2c2: i2c2grp { 497 pinctrl_i2c2: i2c2grp {
689 fsl,pins = < 498 fsl,pins = <
690 MX8MM_IOMUXC_I2C2_SCL_ 499 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
691 MX8MM_IOMUXC_I2C2_SDA_ 500 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
692 >; 501 >;
693 }; 502 };
694 503
695 pinctrl_i2c3: i2c3grp { 504 pinctrl_i2c3: i2c3grp {
696 fsl,pins = < 505 fsl,pins = <
697 MX8MM_IOMUXC_I2C3_SCL_ 506 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
698 MX8MM_IOMUXC_I2C3_SDA_ 507 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
699 >; 508 >;
700 }; 509 };
701 510
702 pinctrl_pcie0: pcie0grp { 511 pinctrl_pcie0: pcie0grp {
703 fsl,pins = < 512 fsl,pins = <
704 MX8MM_IOMUXC_I2C4_SCL_ 513 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
705 MX8MM_IOMUXC_SAI2_RXFS 514 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
706 >; 515 >;
707 }; 516 };
708 517
709 pinctrl_pcie0_reg: pcie0reggrp { 518 pinctrl_pcie0_reg: pcie0reggrp {
710 fsl,pins = < 519 fsl,pins = <
711 MX8MM_IOMUXC_GPIO1_IO0 520 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
712 >; 521 >;
713 }; 522 };
714 523
715 pinctrl_pdm: pdmgrp { <<
716 fsl,pins = < <<
717 MX8MM_IOMUXC_SAI5_MCLK <<
718 MX8MM_IOMUXC_SAI5_RXC_ <<
719 MX8MM_IOMUXC_SAI5_RXFS <<
720 MX8MM_IOMUXC_SAI5_RXD0 <<
721 MX8MM_IOMUXC_SAI5_RXD1 <<
722 MX8MM_IOMUXC_SAI5_RXD2 <<
723 MX8MM_IOMUXC_SAI5_RXD3 <<
724 >; <<
725 }; <<
726 <<
727 pinctrl_pmic: pmicirqgrp { 524 pinctrl_pmic: pmicirqgrp {
728 fsl,pins = < 525 fsl,pins = <
729 MX8MM_IOMUXC_GPIO1_IO0 526 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
730 >; 527 >;
731 }; 528 };
732 529
733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 530 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
734 fsl,pins = < 531 fsl,pins = <
735 MX8MM_IOMUXC_SD2_RESET 532 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
736 >; 533 >;
737 }; 534 };
738 535
739 pinctrl_sai2: sai2grp { 536 pinctrl_sai2: sai2grp {
740 fsl,pins = < 537 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXC_ 538 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
742 MX8MM_IOMUXC_SAI2_TXFS 539 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
743 MX8MM_IOMUXC_SAI2_TXD0 540 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
744 MX8MM_IOMUXC_SAI2_RXD0 541 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
745 >; 542 >;
746 }; 543 };
747 544
748 pinctrl_sai3: sai3grp { 545 pinctrl_sai3: sai3grp {
749 fsl,pins = < 546 fsl,pins = <
750 MX8MM_IOMUXC_SAI3_TXFS 547 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
751 MX8MM_IOMUXC_SAI3_TXC_ 548 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
752 MX8MM_IOMUXC_SAI3_MCLK 549 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
753 MX8MM_IOMUXC_SAI3_TXD_ 550 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
754 >; 551 >;
755 }; 552 };
756 553
757 pinctrl_spdif1: spdif1grp { <<
758 fsl,pins = < <<
759 MX8MM_IOMUXC_SPDIF_TX_ <<
760 MX8MM_IOMUXC_SPDIF_RX_ <<
761 >; <<
762 }; <<
763 <<
764 pinctrl_typec1: typec1grp { 554 pinctrl_typec1: typec1grp {
765 fsl,pins = < 555 fsl,pins = <
766 MX8MM_IOMUXC_SD1_STROB 556 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
767 >; 557 >;
768 }; 558 };
769 559
770 pinctrl_uart2: uart2grp { 560 pinctrl_uart2: uart2grp {
771 fsl,pins = < 561 fsl,pins = <
772 MX8MM_IOMUXC_UART2_RXD 562 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
773 MX8MM_IOMUXC_UART2_TXD 563 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
774 >; 564 >;
775 }; 565 };
776 566
777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp 567 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
778 fsl,pins = < 568 fsl,pins = <
779 MX8MM_IOMUXC_GPIO1_IO1 569 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
780 >; 570 >;
781 }; 571 };
782 572
783 pinctrl_usdhc2: usdhc2grp { 573 pinctrl_usdhc2: usdhc2grp {
784 fsl,pins = < 574 fsl,pins = <
785 MX8MM_IOMUXC_SD2_CLK_U 575 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
786 MX8MM_IOMUXC_SD2_CMD_U 576 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
787 MX8MM_IOMUXC_SD2_DATA0 577 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
788 MX8MM_IOMUXC_SD2_DATA1 578 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
789 MX8MM_IOMUXC_SD2_DATA2 579 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
790 MX8MM_IOMUXC_SD2_DATA3 580 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
791 MX8MM_IOMUXC_GPIO1_IO0 581 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
792 >; 582 >;
793 }; 583 };
794 584
795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 585 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
796 fsl,pins = < 586 fsl,pins = <
797 MX8MM_IOMUXC_SD2_CLK_U 587 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
798 MX8MM_IOMUXC_SD2_CMD_U 588 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
799 MX8MM_IOMUXC_SD2_DATA0 589 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
800 MX8MM_IOMUXC_SD2_DATA1 590 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
801 MX8MM_IOMUXC_SD2_DATA2 591 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
802 MX8MM_IOMUXC_SD2_DATA3 592 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
803 MX8MM_IOMUXC_GPIO1_IO0 593 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
804 >; 594 >;
805 }; 595 };
806 596
807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 597 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
808 fsl,pins = < 598 fsl,pins = <
809 MX8MM_IOMUXC_SD2_CLK_U 599 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
810 MX8MM_IOMUXC_SD2_CMD_U 600 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
811 MX8MM_IOMUXC_SD2_DATA0 601 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
812 MX8MM_IOMUXC_SD2_DATA1 602 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
813 MX8MM_IOMUXC_SD2_DATA2 603 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
814 MX8MM_IOMUXC_SD2_DATA3 604 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
815 MX8MM_IOMUXC_GPIO1_IO0 605 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 606 >;
817 }; 607 };
818 608
819 pinctrl_wdog: wdoggrp { 609 pinctrl_wdog: wdoggrp {
820 fsl,pins = < 610 fsl,pins = <
821 MX8MM_IOMUXC_GPIO1_IO0 611 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
822 >; 612 >;
823 }; 613 };
824 614
825 pinctrl_backlight: backlightgrp { 615 pinctrl_backlight: backlightgrp {
826 fsl,pins = < 616 fsl,pins = <
827 MX8MM_IOMUXC_GPIO1_IO0 617 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
828 >; <<
829 }; <<
830 <<
831 pinctrl_camera: cameragrp { <<
832 fsl,pins = < <<
833 MX8MM_IOMUXC_GPIO1_IO0 <<
834 MX8MM_IOMUXC_GPIO1_IO0 <<
835 MX8MM_IOMUXC_GPIO1_IO1 <<
836 >; 618 >;
837 }; 619 };
838 }; 620 };
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