1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi" 10 #include "imx8mm.dtsi"
11 11
12 / { 12 / {
13 chosen { 13 chosen {
14 stdout-path = &uart2; 14 stdout-path = &uart2;
15 }; 15 };
16 16
17 memory@40000000 { 17 memory@40000000 {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x8000 19 reg = <0x0 0x40000000 0 0x80000000>;
20 }; 20 };
21 21
22 hdmi-connector { 22 hdmi-connector {
23 compatible = "hdmi-connector"; 23 compatible = "hdmi-connector";
24 label = "hdmi"; 24 label = "hdmi";
25 type = "a"; 25 type = "a";
26 26
27 port { 27 port {
28 hdmi_connector_in: end 28 hdmi_connector_in: endpoint {
29 remote-endpoin 29 remote-endpoint = <&adv7535_out>;
30 }; 30 };
31 }; 31 };
32 }; 32 };
33 33
34 leds { 34 leds {
35 compatible = "gpio-leds"; 35 compatible = "gpio-leds";
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led 37 pinctrl-0 = <&pinctrl_gpio_led>;
38 38
39 status { 39 status {
40 label = "status"; 40 label = "status";
41 gpios = <&gpio3 16 GPI 41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on"; 42 default-state = "on";
43 }; 43 };
44 }; 44 };
45 45
46 pcie0_refclk: pcie0-refclk { 46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock"; 47 compatible = "fixed-clock";
48 #clock-cells = <0>; 48 #clock-cells = <0>;
49 clock-frequency = <100000000>; 49 clock-frequency = <100000000>;
50 }; 50 };
51 51
52 reg_pcie0: regulator-pcie { 52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_re 55 pinctrl-0 = <&pinctrl_pcie0_reg>;
56 regulator-name = "MPCIE_3V3"; 56 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <330 57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <330 58 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio1 5 GPIO_ACTIVE_H 59 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
60 enable-active-high; 60 enable-active-high;
61 }; 61 };
62 62
63 reg_usdhc2_vmmc: regulator-usdhc2 { 63 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed" 64 compatible = "regulator-fixed";
65 pinctrl-names = "default"; 65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdh 66 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3"; 67 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <330 68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_ 70 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>; 71 off-on-delay-us = <20000>;
72 enable-active-high; 72 enable-active-high;
73 }; 73 };
74 74
75 reg_1v5: regulator-1v5 { <<
76 compatible = "regulator-fixed" <<
77 regulator-name = "VDD_1V5"; <<
78 regulator-min-microvolt = <150 <<
79 regulator-max-microvolt = <150 <<
80 }; <<
81 <<
82 reg_1v8: regulator-1v8 { <<
83 compatible = "regulator-fixed" <<
84 regulator-name = "VDD_1V8"; <<
85 regulator-min-microvolt = <180 <<
86 regulator-max-microvolt = <180 <<
87 }; <<
88 <<
89 reg_vddext_3v3: regulator-vddext-3v3 { 75 reg_vddext_3v3: regulator-vddext-3v3 {
90 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
91 regulator-name = "VDDEXT_3V3"; 77 regulator-name = "VDDEXT_3V3";
92 regulator-min-microvolt = <330 78 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <330 79 regulator-max-microvolt = <3300000>;
94 }; 80 };
95 81
96 backlight: backlight { 82 backlight: backlight {
97 compatible = "pwm-backlight"; 83 compatible = "pwm-backlight";
98 pwms = <&pwm1 0 5000000 0>; 84 pwms = <&pwm1 0 5000000 0>;
99 brightness-levels = <0 255>; 85 brightness-levels = <0 255>;
100 num-interpolated-steps = <255> 86 num-interpolated-steps = <255>;
101 default-brightness-level = <25 87 default-brightness-level = <250>;
102 }; 88 };
103 89
104 ir-receiver { 90 ir-receiver {
105 compatible = "gpio-ir-receiver 91 compatible = "gpio-ir-receiver";
106 gpios = <&gpio1 13 GPIO_ACTIVE 92 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
107 pinctrl-names = "default"; 93 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_ir>; 94 pinctrl-0 = <&pinctrl_ir>;
109 linux,autosuspend-period = <12 95 linux,autosuspend-period = <125>;
110 }; 96 };
111 97
112 audio_codec_bt_sco: audio-codec-bt-sco 98 audio_codec_bt_sco: audio-codec-bt-sco {
113 compatible = "linux,bt-sco"; 99 compatible = "linux,bt-sco";
114 #sound-dai-cells = <1>; 100 #sound-dai-cells = <1>;
115 }; 101 };
116 102
117 wm8524: audio-codec { 103 wm8524: audio-codec {
118 #sound-dai-cells = <0>; 104 #sound-dai-cells = <0>;
119 compatible = "wlf,wm8524"; 105 compatible = "wlf,wm8524";
120 pinctrl-names = "default"; 106 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_gpio_wlf 107 pinctrl-0 = <&pinctrl_gpio_wlf>;
122 wlf,mute-gpios = <&gpio5 21 GP 108 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
123 }; 109 };
124 110
125 sound-bt-sco { 111 sound-bt-sco {
126 compatible = "simple-audio-car 112 compatible = "simple-audio-card";
127 simple-audio-card,name = "bt-s 113 simple-audio-card,name = "bt-sco-audio";
128 simple-audio-card,format = "ds 114 simple-audio-card,format = "dsp_a";
129 simple-audio-card,bitclock-inv 115 simple-audio-card,bitclock-inversion;
130 simple-audio-card,frame-master 116 simple-audio-card,frame-master = <&btcpu>;
131 simple-audio-card,bitclock-mas 117 simple-audio-card,bitclock-master = <&btcpu>;
132 118
133 btcpu: simple-audio-card,cpu { 119 btcpu: simple-audio-card,cpu {
134 sound-dai = <&sai2>; 120 sound-dai = <&sai2>;
135 dai-tdm-slot-num = <2> 121 dai-tdm-slot-num = <2>;
136 dai-tdm-slot-width = < 122 dai-tdm-slot-width = <16>;
137 }; 123 };
138 124
139 simple-audio-card,codec { 125 simple-audio-card,codec {
140 sound-dai = <&audio_co 126 sound-dai = <&audio_codec_bt_sco 1>;
141 }; 127 };
142 }; 128 };
143 129
144 sound-wm8524 { 130 sound-wm8524 {
145 compatible = "simple-audio-car 131 compatible = "simple-audio-card";
146 simple-audio-card,name = "wm85 132 simple-audio-card,name = "wm8524-audio";
147 simple-audio-card,format = "i2 133 simple-audio-card,format = "i2s";
148 simple-audio-card,frame-master 134 simple-audio-card,frame-master = <&cpudai>;
149 simple-audio-card,bitclock-mas 135 simple-audio-card,bitclock-master = <&cpudai>;
150 simple-audio-card,widgets = 136 simple-audio-card,widgets =
151 "Line", "Left Line Out 137 "Line", "Left Line Out Jack",
152 "Line", "Right Line Ou 138 "Line", "Right Line Out Jack";
153 simple-audio-card,routing = 139 simple-audio-card,routing =
154 "Left Line Out Jack", 140 "Left Line Out Jack", "LINEVOUTL",
155 "Right Line Out Jack", 141 "Right Line Out Jack", "LINEVOUTR";
156 142
157 cpudai: simple-audio-card,cpu 143 cpudai: simple-audio-card,cpu {
158 sound-dai = <&sai3>; 144 sound-dai = <&sai3>;
159 dai-tdm-slot-num = <2> 145 dai-tdm-slot-num = <2>;
160 dai-tdm-slot-width = < 146 dai-tdm-slot-width = <32>;
161 }; 147 };
162 148
163 simple-audio-card,codec { 149 simple-audio-card,codec {
164 sound-dai = <&wm8524>; 150 sound-dai = <&wm8524>;
165 clocks = <&clk IMX8MM_ 151 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
166 }; 152 };
167 }; 153 };
168 154
169 sound-micfil { 155 sound-micfil {
170 compatible = "fsl,imx-audio-ca 156 compatible = "fsl,imx-audio-card";
171 model = "micfil-audio"; 157 model = "micfil-audio";
172 158
173 pri-dai-link { 159 pri-dai-link {
174 link-name = "micfil hi 160 link-name = "micfil hifi";
175 format = "i2s"; 161 format = "i2s";
176 162
177 cpu { 163 cpu {
178 sound-dai = <& 164 sound-dai = <&micfil>;
179 }; 165 };
180 }; 166 };
181 }; 167 };
182 168
183 spdif_out: spdif-out { <<
184 compatible = "linux,spdif-dit" <<
185 #sound-dai-cells = <0>; <<
186 }; <<
187 <<
188 spdif_in: spdif-in { <<
189 compatible = "linux,spdif-dir" <<
190 #sound-dai-cells = <0>; <<
191 }; <<
192 <<
193 sound-spdif { 169 sound-spdif {
194 compatible = "fsl,imx-audio-sp 170 compatible = "fsl,imx-audio-spdif";
195 model = "imx-spdif"; 171 model = "imx-spdif";
196 audio-cpu = <&spdif1>; !! 172 spdif-controller = <&spdif1>;
197 audio-codec = <&spdif_out>, <& !! 173 spdif-out;
>> 174 spdif-in;
198 }; 175 };
199 }; 176 };
200 177
201 &A53_0 { 178 &A53_0 {
202 cpu-supply = <&buck2_reg>; 179 cpu-supply = <&buck2_reg>;
203 }; 180 };
204 181
205 &A53_1 { 182 &A53_1 {
206 cpu-supply = <&buck2_reg>; 183 cpu-supply = <&buck2_reg>;
207 }; 184 };
208 185
209 &A53_2 { 186 &A53_2 {
210 cpu-supply = <&buck2_reg>; 187 cpu-supply = <&buck2_reg>;
211 }; 188 };
212 189
213 &A53_3 { 190 &A53_3 {
214 cpu-supply = <&buck2_reg>; 191 cpu-supply = <&buck2_reg>;
215 }; 192 };
216 193
217 &fec1 { 194 &fec1 {
218 pinctrl-names = "default"; 195 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec1>; 196 pinctrl-0 = <&pinctrl_fec1>;
220 phy-mode = "rgmii-id"; 197 phy-mode = "rgmii-id";
221 phy-handle = <ðphy0>; 198 phy-handle = <ðphy0>;
222 fsl,magic-packet; 199 fsl,magic-packet;
223 status = "okay"; 200 status = "okay";
224 201
225 mdio { 202 mdio {
226 #address-cells = <1>; 203 #address-cells = <1>;
227 #size-cells = <0>; 204 #size-cells = <0>;
228 205
229 ethphy0: ethernet-phy@0 { 206 ethphy0: ethernet-phy@0 {
230 compatible = "ethernet 207 compatible = "ethernet-phy-ieee802.3-c22";
231 reg = <0>; 208 reg = <0>;
232 reset-gpios = <&gpio4 209 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
233 reset-assert-us = <100 210 reset-assert-us = <10000>;
234 qca,disable-smarteee; 211 qca,disable-smarteee;
235 vddio-supply = <&vddio 212 vddio-supply = <&vddio>;
236 213
237 vddio: vddio-regulator 214 vddio: vddio-regulator {
238 regulator-min- 215 regulator-min-microvolt = <1800000>;
239 regulator-max- 216 regulator-max-microvolt = <1800000>;
240 }; 217 };
241 }; 218 };
242 }; 219 };
243 }; 220 };
244 221
245 &i2c1 { 222 &i2c1 {
246 clock-frequency = <400000>; 223 clock-frequency = <400000>;
247 pinctrl-names = "default"; 224 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>; 225 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay"; 226 status = "okay";
250 227
251 pmic@4b { 228 pmic@4b {
252 compatible = "rohm,bd71847"; 229 compatible = "rohm,bd71847";
253 reg = <0x4b>; 230 reg = <0x4b>;
254 pinctrl-names = "default"; 231 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_pmic>; 232 pinctrl-0 = <&pinctrl_pmic>;
256 interrupt-parent = <&gpio1>; 233 interrupt-parent = <&gpio1>;
257 interrupts = <3 IRQ_TYPE_LEVEL 234 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
258 rohm,reset-snvs-powered; 235 rohm,reset-snvs-powered;
259 236
260 #clock-cells = <0>; 237 #clock-cells = <0>;
261 clocks = <&osc_32k>; 238 clocks = <&osc_32k>;
262 clock-output-names = "clk-32k- 239 clock-output-names = "clk-32k-out";
263 240
264 regulators { 241 regulators {
265 buck1_reg: BUCK1 { 242 buck1_reg: BUCK1 {
266 regulator-name 243 regulator-name = "buck1";
267 regulator-min- 244 regulator-min-microvolt = <700000>;
268 regulator-max- 245 regulator-max-microvolt = <1300000>;
269 regulator-boot 246 regulator-boot-on;
270 regulator-alwa 247 regulator-always-on;
271 regulator-ramp 248 regulator-ramp-delay = <1250>;
272 }; 249 };
273 250
274 buck2_reg: BUCK2 { 251 buck2_reg: BUCK2 {
275 regulator-name 252 regulator-name = "buck2";
276 regulator-min- 253 regulator-min-microvolt = <700000>;
277 regulator-max- 254 regulator-max-microvolt = <1300000>;
278 regulator-boot 255 regulator-boot-on;
279 regulator-alwa 256 regulator-always-on;
280 regulator-ramp 257 regulator-ramp-delay = <1250>;
281 rohm,dvs-run-v 258 rohm,dvs-run-voltage = <1000000>;
282 rohm,dvs-idle- 259 rohm,dvs-idle-voltage = <900000>;
283 }; 260 };
284 261
285 buck3_reg: BUCK3 { 262 buck3_reg: BUCK3 {
286 // BUCK5 in da 263 // BUCK5 in datasheet
287 regulator-name 264 regulator-name = "buck3";
288 regulator-min- 265 regulator-min-microvolt = <700000>;
289 regulator-max- 266 regulator-max-microvolt = <1350000>;
290 regulator-boot 267 regulator-boot-on;
291 regulator-alwa 268 regulator-always-on;
292 }; 269 };
293 270
294 buck4_reg: BUCK4 { 271 buck4_reg: BUCK4 {
295 // BUCK6 in da 272 // BUCK6 in datasheet
296 regulator-name 273 regulator-name = "buck4";
297 regulator-min- 274 regulator-min-microvolt = <3000000>;
298 regulator-max- 275 regulator-max-microvolt = <3300000>;
299 regulator-boot 276 regulator-boot-on;
300 regulator-alwa 277 regulator-always-on;
301 }; 278 };
302 279
303 buck5_reg: BUCK5 { 280 buck5_reg: BUCK5 {
304 // BUCK7 in da 281 // BUCK7 in datasheet
305 regulator-name 282 regulator-name = "buck5";
306 regulator-min- 283 regulator-min-microvolt = <1605000>;
307 regulator-max- 284 regulator-max-microvolt = <1995000>;
308 regulator-boot 285 regulator-boot-on;
309 regulator-alwa 286 regulator-always-on;
310 }; 287 };
311 288
312 buck6_reg: BUCK6 { 289 buck6_reg: BUCK6 {
313 // BUCK8 in da 290 // BUCK8 in datasheet
314 regulator-name 291 regulator-name = "buck6";
315 regulator-min- 292 regulator-min-microvolt = <800000>;
316 regulator-max- 293 regulator-max-microvolt = <1400000>;
317 regulator-boot 294 regulator-boot-on;
318 regulator-alwa 295 regulator-always-on;
319 }; 296 };
320 297
321 ldo1_reg: LDO1 { 298 ldo1_reg: LDO1 {
322 regulator-name 299 regulator-name = "ldo1";
323 regulator-min- 300 regulator-min-microvolt = <1600000>;
324 regulator-max- 301 regulator-max-microvolt = <3300000>;
325 regulator-boot 302 regulator-boot-on;
326 regulator-alwa 303 regulator-always-on;
327 }; 304 };
328 305
329 ldo2_reg: LDO2 { 306 ldo2_reg: LDO2 {
330 regulator-name 307 regulator-name = "ldo2";
331 regulator-min- 308 regulator-min-microvolt = <800000>;
332 regulator-max- 309 regulator-max-microvolt = <900000>;
333 regulator-boot 310 regulator-boot-on;
334 regulator-alwa 311 regulator-always-on;
335 }; 312 };
336 313
337 ldo3_reg: LDO3 { 314 ldo3_reg: LDO3 {
338 regulator-name 315 regulator-name = "ldo3";
339 regulator-min- 316 regulator-min-microvolt = <1800000>;
340 regulator-max- 317 regulator-max-microvolt = <3300000>;
341 regulator-boot 318 regulator-boot-on;
342 regulator-alwa 319 regulator-always-on;
343 }; 320 };
344 321
345 ldo4_reg: LDO4 { 322 ldo4_reg: LDO4 {
346 regulator-name 323 regulator-name = "ldo4";
347 regulator-min- 324 regulator-min-microvolt = <900000>;
348 regulator-max- 325 regulator-max-microvolt = <1800000>;
349 regulator-boot 326 regulator-boot-on;
350 regulator-alwa 327 regulator-always-on;
351 }; 328 };
352 329
353 ldo6_reg: LDO6 { 330 ldo6_reg: LDO6 {
354 regulator-name 331 regulator-name = "ldo6";
355 regulator-min- 332 regulator-min-microvolt = <900000>;
356 regulator-max- 333 regulator-max-microvolt = <1800000>;
357 regulator-boot 334 regulator-boot-on;
358 regulator-alwa 335 regulator-always-on;
359 }; 336 };
360 }; 337 };
361 }; 338 };
362 }; 339 };
363 340
364 &i2c2 { 341 &i2c2 {
365 clock-frequency = <400000>; 342 clock-frequency = <400000>;
366 pinctrl-names = "default"; 343 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c2>; 344 pinctrl-0 = <&pinctrl_i2c2>;
368 status = "okay"; 345 status = "okay";
369 346
370 hdmi@3d { 347 hdmi@3d {
371 compatible = "adi,adv7535"; 348 compatible = "adi,adv7535";
372 reg = <0x3d>; 349 reg = <0x3d>;
373 interrupt-parent = <&gpio1>; 350 interrupt-parent = <&gpio1>;
374 interrupts = <9 IRQ_TYPE_EDGE_ 351 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
375 adi,dsi-lanes = <4>; 352 adi,dsi-lanes = <4>;
376 avdd-supply = <&buck5_reg>; 353 avdd-supply = <&buck5_reg>;
377 dvdd-supply = <&buck5_reg>; 354 dvdd-supply = <&buck5_reg>;
378 pvdd-supply = <&buck5_reg>; 355 pvdd-supply = <&buck5_reg>;
379 a2vdd-supply = <&buck5_reg>; 356 a2vdd-supply = <&buck5_reg>;
380 v3p3-supply = <®_vddext_3v3 357 v3p3-supply = <®_vddext_3v3>;
381 v1p2-supply = <&buck5_reg>; 358 v1p2-supply = <&buck5_reg>;
382 359
383 ports { 360 ports {
384 #address-cells = <1>; 361 #address-cells = <1>;
385 #size-cells = <0>; 362 #size-cells = <0>;
386 363
387 port@0 { 364 port@0 {
388 reg = <0>; 365 reg = <0>;
389 366
390 adv7535_in: en 367 adv7535_in: endpoint {
391 remote 368 remote-endpoint = <&dsi_out>;
392 }; 369 };
393 }; 370 };
394 371
395 port@1 { 372 port@1 {
396 reg = <1>; 373 reg = <1>;
397 374
398 adv7535_out: e 375 adv7535_out: endpoint {
399 remote 376 remote-endpoint = <&hdmi_connector_in>;
400 }; 377 };
401 }; 378 };
402 379
403 }; 380 };
404 }; 381 };
405 382
406 ptn5110: tcpc@50 { 383 ptn5110: tcpc@50 {
407 compatible = "nxp,ptn5110", "t !! 384 compatible = "nxp,ptn5110";
408 pinctrl-names = "default"; 385 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_typec1>; 386 pinctrl-0 = <&pinctrl_typec1>;
410 reg = <0x50>; 387 reg = <0x50>;
411 interrupt-parent = <&gpio2>; 388 interrupt-parent = <&gpio2>;
412 interrupts = <11 IRQ_TYPE_LEVE !! 389 interrupts = <11 8>;
413 status = "okay"; 390 status = "okay";
414 391
415 typec1_con: connector { 392 typec1_con: connector {
416 compatible = "usb-c-co 393 compatible = "usb-c-connector";
417 label = "USB-C"; 394 label = "USB-C";
418 power-role = "dual"; 395 power-role = "dual";
419 data-role = "dual"; 396 data-role = "dual";
420 try-power-role = "sink 397 try-power-role = "sink";
421 source-pdos = <PDO_FIX 398 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
422 sink-pdos = <PDO_FIXED 399 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
423 PDO_VAR(5 400 PDO_VAR(5000, 20000, 3000)>;
424 op-sink-microwatt = <1 401 op-sink-microwatt = <15000000>;
425 self-powered; 402 self-powered;
426 403
427 port { 404 port {
428 typec1_dr_sw: 405 typec1_dr_sw: endpoint {
429 remote 406 remote-endpoint = <&usb1_drd_sw>;
430 }; 407 };
431 }; 408 };
432 }; 409 };
433 }; 410 };
434 }; 411 };
435 412
436 413
437 &csi { 414 &csi {
438 status = "okay"; 415 status = "okay";
439 }; 416 };
440 417
441 &i2c3 { 418 &i2c3 {
442 clock-frequency = <400000>; 419 clock-frequency = <400000>;
443 pinctrl-names = "default"; 420 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>; 421 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay"; 422 status = "okay";
446 423
447 pca6416: gpio@20 { 424 pca6416: gpio@20 {
448 compatible = "nxp,pca6416"; 425 compatible = "nxp,pca6416";
449 reg = <0x20>; 426 reg = <0x20>;
450 gpio-controller; 427 gpio-controller;
451 #gpio-cells = <2>; 428 #gpio-cells = <2>;
452 vcc-supply = <&buck4_reg>; 429 vcc-supply = <&buck4_reg>;
453 }; 430 };
454 431
455 camera@3c { 432 camera@3c {
456 compatible = "ovti,ov5640"; 433 compatible = "ovti,ov5640";
457 reg = <0x3c>; 434 reg = <0x3c>;
458 pinctrl-names = "default"; 435 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_camera>; 436 pinctrl-0 = <&pinctrl_camera>;
460 clocks = <&clk IMX8MM_CLK_CLKO 437 clocks = <&clk IMX8MM_CLK_CLKO1>;
461 clock-names = "xclk"; 438 clock-names = "xclk";
462 assigned-clocks = <&clk IMX8MM 439 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
463 assigned-clock-parents = <&clk 440 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
464 assigned-clock-rates = <240000 441 assigned-clock-rates = <24000000>;
465 powerdown-gpios = <&gpio1 7 GP 442 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
466 reset-gpios = <&gpio1 6 GPIO_A 443 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
467 DOVDD-supply = <&buck5_reg>; <<
468 AVDD-supply = <®_1v8>; <<
469 DVDD-supply = <®_1v5>; <<
470 444
471 port { 445 port {
472 ov5640_to_mipi_csi2: e 446 ov5640_to_mipi_csi2: endpoint {
473 remote-endpoin 447 remote-endpoint = <&imx8mm_mipi_csi_in>;
474 clock-lanes = 448 clock-lanes = <0>;
475 data-lanes = < 449 data-lanes = <1 2>;
476 }; 450 };
477 }; 451 };
478 }; 452 };
479 }; 453 };
480 454
481 &lcdif { 455 &lcdif {
482 status = "okay"; 456 status = "okay";
483 }; 457 };
484 458
485 &micfil { 459 &micfil {
486 #sound-dai-cells = <0>; 460 #sound-dai-cells = <0>;
487 pinctrl-names = "default"; 461 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_pdm>; 462 pinctrl-0 = <&pinctrl_pdm>;
489 assigned-clocks = <&clk IMX8MM_CLK_PDM 463 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
490 assigned-clock-parents = <&clk IMX8MM_ 464 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
491 assigned-clock-rates = <196608000>; 465 assigned-clock-rates = <196608000>;
492 status = "okay"; 466 status = "okay";
493 }; 467 };
494 468
495 &mipi_csi { 469 &mipi_csi {
496 status = "okay"; 470 status = "okay";
497 471
498 ports { 472 ports {
499 port@0 { 473 port@0 {
500 imx8mm_mipi_csi_in: en 474 imx8mm_mipi_csi_in: endpoint {
501 remote-endpoin 475 remote-endpoint = <&ov5640_to_mipi_csi2>;
502 data-lanes = < 476 data-lanes = <1 2>;
503 }; 477 };
504 }; 478 };
505 }; 479 };
506 }; 480 };
507 481
508 &mipi_dsi { 482 &mipi_dsi {
509 samsung,esc-clock-frequency = <1000000 483 samsung,esc-clock-frequency = <10000000>;
510 status = "okay"; 484 status = "okay";
511 485
512 ports { 486 ports {
513 port@1 { 487 port@1 {
514 reg = <1>; 488 reg = <1>;
515 489
516 dsi_out: endpoint { 490 dsi_out: endpoint {
517 remote-endpoin 491 remote-endpoint = <&adv7535_in>;
518 data-lanes = < 492 data-lanes = <1 2 3 4>;
519 }; 493 };
520 }; 494 };
521 }; 495 };
522 }; 496 };
523 497
524 &pcie_phy { 498 &pcie_phy {
525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 499 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
526 fsl,tx-deemph-gen1 = <0x2d>; 500 fsl,tx-deemph-gen1 = <0x2d>;
527 fsl,tx-deemph-gen2 = <0xf>; 501 fsl,tx-deemph-gen2 = <0xf>;
528 clocks = <&pcie0_refclk>; 502 clocks = <&pcie0_refclk>;
529 status = "okay"; 503 status = "okay";
530 }; 504 };
531 505
532 &pcie0 { 506 &pcie0 {
533 pinctrl-names = "default"; 507 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_pcie0>; 508 pinctrl-0 = <&pinctrl_pcie0>;
535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LO 509 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 510 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
537 <&clk IMX8MM_CLK_PCIE1_AUX>; 511 <&clk IMX8MM_CLK_PCIE1_AUX>;
538 assigned-clocks = <&clk IMX8MM_CLK_PCI 512 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
539 <&clk IMX8MM_CLK_PCI 513 <&clk IMX8MM_CLK_PCIE1_CTRL>;
540 assigned-clock-rates = <10000000>, <25 514 assigned-clock-rates = <10000000>, <250000000>;
541 assigned-clock-parents = <&clk IMX8MM_ 515 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
542 <&clk IMX8MM_ 516 <&clk IMX8MM_SYS_PLL2_250M>;
543 vpcie-supply = <®_pcie0>; 517 vpcie-supply = <®_pcie0>;
544 status = "okay"; 518 status = "okay";
545 }; 519 };
546 520
547 &sai2 { 521 &sai2 {
548 #sound-dai-cells = <0>; 522 #sound-dai-cells = <0>;
549 pinctrl-names = "default"; 523 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_sai2>; 524 pinctrl-0 = <&pinctrl_sai2>;
551 assigned-clocks = <&clk IMX8MM_CLK_SAI 525 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
552 assigned-clock-parents = <&clk IMX8MM_ 526 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
553 assigned-clock-rates = <24576000>; 527 assigned-clock-rates = <24576000>;
554 status = "okay"; 528 status = "okay";
555 }; 529 };
556 530
557 &sai3 { 531 &sai3 {
558 pinctrl-names = "default"; 532 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_sai3>; 533 pinctrl-0 = <&pinctrl_sai3>;
560 assigned-clocks = <&clk IMX8MM_CLK_SAI 534 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
561 assigned-clock-parents = <&clk IMX8MM_ 535 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
562 assigned-clock-rates = <24576000>; 536 assigned-clock-rates = <24576000>;
563 status = "okay"; 537 status = "okay";
564 }; 538 };
565 539
566 &snvs_pwrkey { 540 &snvs_pwrkey {
567 status = "okay"; 541 status = "okay";
568 }; 542 };
569 543
570 &spdif1 { 544 &spdif1 {
571 pinctrl-names = "default"; 545 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_spdif1>; 546 pinctrl-0 = <&pinctrl_spdif1>;
573 assigned-clocks = <&clk IMX8MM_CLK_SPD 547 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
574 assigned-clock-parents = <&clk IMX8MM_ 548 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
575 assigned-clock-rates = <24576000>; 549 assigned-clock-rates = <24576000>;
576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, 550 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
577 <&clk IMX8MM_CLK_SPDIF1>, <&c 551 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
578 <&clk IMX8MM_CLK_DUMMY>, <&cl 552 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
579 <&clk IMX8MM_CLK_AUDIO_AHB>, 553 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
580 <&clk IMX8MM_CLK_DUMMY>, <&cl 554 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
581 <&clk IMX8MM_AUDIO_PLL1_OUT>, 555 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
582 clock-names = "core", "rxtx0", "rxtx1" 556 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
583 "rxtx4", "rxtx5", "rxtx6 557 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
584 "pll8k", "pll11k"; 558 "pll8k", "pll11k";
585 status = "okay"; 559 status = "okay";
586 }; 560 };
587 561
588 &uart2 { /* console */ 562 &uart2 { /* console */
589 pinctrl-names = "default"; 563 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart2>; 564 pinctrl-0 = <&pinctrl_uart2>;
591 status = "okay"; 565 status = "okay";
592 }; 566 };
593 567
594 &usbphynop1 { 568 &usbphynop1 {
595 wakeup-source; 569 wakeup-source;
596 }; 570 };
597 571
598 &usbotg1 { 572 &usbotg1 {
599 dr_mode = "otg"; 573 dr_mode = "otg";
600 hnp-disable; 574 hnp-disable;
601 srp-disable; 575 srp-disable;
602 adp-disable; 576 adp-disable;
603 usb-role-switch; 577 usb-role-switch;
604 disable-over-current; 578 disable-over-current;
605 samsung,picophy-pre-emp-curr-control = 579 samsung,picophy-pre-emp-curr-control = <3>;
606 samsung,picophy-dc-vol-level-adjust = 580 samsung,picophy-dc-vol-level-adjust = <7>;
607 status = "okay"; 581 status = "okay";
608 582
609 port { 583 port {
610 usb1_drd_sw: endpoint { 584 usb1_drd_sw: endpoint {
611 remote-endpoint = <&ty 585 remote-endpoint = <&typec1_dr_sw>;
612 }; 586 };
613 }; 587 };
614 }; 588 };
615 589
616 &usdhc2 { 590 &usdhc2 {
617 assigned-clocks = <&clk IMX8MM_CLK_USD 591 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
618 assigned-clock-rates = <200000000>; 592 assigned-clock-rates = <200000000>;
619 pinctrl-names = "default", "state_100m 593 pinctrl-names = "default", "state_100mhz", "state_200mhz";
620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 594 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 595 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 596 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 597 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
624 bus-width = <4>; 598 bus-width = <4>;
625 vmmc-supply = <®_usdhc2_vmmc>; 599 vmmc-supply = <®_usdhc2_vmmc>;
626 status = "okay"; 600 status = "okay";
627 }; 601 };
628 602
629 &wdog1 { 603 &wdog1 {
630 pinctrl-names = "default"; 604 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_wdog>; 605 pinctrl-0 = <&pinctrl_wdog>;
632 fsl,ext-reset-output; 606 fsl,ext-reset-output;
633 status = "okay"; 607 status = "okay";
634 }; 608 };
635 609
636 &pwm1 { 610 &pwm1 {
637 pinctrl-names = "default"; 611 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_backlight>; 612 pinctrl-0 = <&pinctrl_backlight>;
639 status = "okay"; 613 status = "okay";
640 }; 614 };
641 615
642 &iomuxc { 616 &iomuxc {
643 pinctrl_fec1: fec1grp { 617 pinctrl_fec1: fec1grp {
644 fsl,pins = < 618 fsl,pins = <
645 MX8MM_IOMUXC_ENET_MDC_ 619 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
646 MX8MM_IOMUXC_ENET_MDIO 620 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
647 MX8MM_IOMUXC_ENET_TD3_ 621 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
648 MX8MM_IOMUXC_ENET_TD2_ 622 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
649 MX8MM_IOMUXC_ENET_TD1_ 623 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
650 MX8MM_IOMUXC_ENET_TD0_ 624 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
651 MX8MM_IOMUXC_ENET_RD3_ 625 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
652 MX8MM_IOMUXC_ENET_RD2_ 626 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
653 MX8MM_IOMUXC_ENET_RD1_ 627 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
654 MX8MM_IOMUXC_ENET_RD0_ 628 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
655 MX8MM_IOMUXC_ENET_TXC_ 629 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
656 MX8MM_IOMUXC_ENET_RXC_ 630 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
657 MX8MM_IOMUXC_ENET_RX_C 631 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
658 MX8MM_IOMUXC_ENET_TX_C 632 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
659 MX8MM_IOMUXC_SAI2_RXC_ 633 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
660 >; 634 >;
661 }; 635 };
662 636
663 pinctrl_gpio_led: gpioledgrp { 637 pinctrl_gpio_led: gpioledgrp {
664 fsl,pins = < 638 fsl,pins = <
665 MX8MM_IOMUXC_NAND_READ 639 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
666 >; 640 >;
667 }; 641 };
668 642
669 pinctrl_ir: irgrp { 643 pinctrl_ir: irgrp {
670 fsl,pins = < 644 fsl,pins = <
671 MX8MM_IOMUXC_GPIO1_IO1 645 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
672 >; 646 >;
673 }; 647 };
674 648
675 pinctrl_gpio_wlf: gpiowlfgrp { 649 pinctrl_gpio_wlf: gpiowlfgrp {
676 fsl,pins = < 650 fsl,pins = <
677 MX8MM_IOMUXC_I2C4_SDA_ 651 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
678 >; 652 >;
679 }; 653 };
680 654
681 pinctrl_i2c1: i2c1grp { 655 pinctrl_i2c1: i2c1grp {
682 fsl,pins = < 656 fsl,pins = <
683 MX8MM_IOMUXC_I2C1_SCL_ 657 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
684 MX8MM_IOMUXC_I2C1_SDA_ 658 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
685 >; 659 >;
686 }; 660 };
687 661
688 pinctrl_i2c2: i2c2grp { 662 pinctrl_i2c2: i2c2grp {
689 fsl,pins = < 663 fsl,pins = <
690 MX8MM_IOMUXC_I2C2_SCL_ 664 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
691 MX8MM_IOMUXC_I2C2_SDA_ 665 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
692 >; 666 >;
693 }; 667 };
694 668
695 pinctrl_i2c3: i2c3grp { 669 pinctrl_i2c3: i2c3grp {
696 fsl,pins = < 670 fsl,pins = <
697 MX8MM_IOMUXC_I2C3_SCL_ 671 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
698 MX8MM_IOMUXC_I2C3_SDA_ 672 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
699 >; 673 >;
700 }; 674 };
701 675
702 pinctrl_pcie0: pcie0grp { 676 pinctrl_pcie0: pcie0grp {
703 fsl,pins = < 677 fsl,pins = <
704 MX8MM_IOMUXC_I2C4_SCL_ 678 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
705 MX8MM_IOMUXC_SAI2_RXFS 679 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
706 >; 680 >;
707 }; 681 };
708 682
709 pinctrl_pcie0_reg: pcie0reggrp { 683 pinctrl_pcie0_reg: pcie0reggrp {
710 fsl,pins = < 684 fsl,pins = <
711 MX8MM_IOMUXC_GPIO1_IO0 685 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
712 >; 686 >;
713 }; 687 };
714 688
715 pinctrl_pdm: pdmgrp { 689 pinctrl_pdm: pdmgrp {
716 fsl,pins = < 690 fsl,pins = <
717 MX8MM_IOMUXC_SAI5_MCLK 691 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
718 MX8MM_IOMUXC_SAI5_RXC_ 692 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
719 MX8MM_IOMUXC_SAI5_RXFS 693 MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
720 MX8MM_IOMUXC_SAI5_RXD0 694 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
721 MX8MM_IOMUXC_SAI5_RXD1 695 MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
722 MX8MM_IOMUXC_SAI5_RXD2 696 MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
723 MX8MM_IOMUXC_SAI5_RXD3 697 MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
724 >; 698 >;
725 }; 699 };
726 700
727 pinctrl_pmic: pmicirqgrp { 701 pinctrl_pmic: pmicirqgrp {
728 fsl,pins = < 702 fsl,pins = <
729 MX8MM_IOMUXC_GPIO1_IO0 703 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
730 >; 704 >;
731 }; 705 };
732 706
733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 707 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
734 fsl,pins = < 708 fsl,pins = <
735 MX8MM_IOMUXC_SD2_RESET 709 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
736 >; 710 >;
737 }; 711 };
738 712
739 pinctrl_sai2: sai2grp { 713 pinctrl_sai2: sai2grp {
740 fsl,pins = < 714 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXC_ 715 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
742 MX8MM_IOMUXC_SAI2_TXFS 716 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
743 MX8MM_IOMUXC_SAI2_TXD0 717 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
744 MX8MM_IOMUXC_SAI2_RXD0 718 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
745 >; 719 >;
746 }; 720 };
747 721
748 pinctrl_sai3: sai3grp { 722 pinctrl_sai3: sai3grp {
749 fsl,pins = < 723 fsl,pins = <
750 MX8MM_IOMUXC_SAI3_TXFS 724 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
751 MX8MM_IOMUXC_SAI3_TXC_ 725 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
752 MX8MM_IOMUXC_SAI3_MCLK 726 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
753 MX8MM_IOMUXC_SAI3_TXD_ 727 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
754 >; 728 >;
755 }; 729 };
756 730
757 pinctrl_spdif1: spdif1grp { 731 pinctrl_spdif1: spdif1grp {
758 fsl,pins = < 732 fsl,pins = <
759 MX8MM_IOMUXC_SPDIF_TX_ 733 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
760 MX8MM_IOMUXC_SPDIF_RX_ 734 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
761 >; 735 >;
762 }; 736 };
763 737
764 pinctrl_typec1: typec1grp { 738 pinctrl_typec1: typec1grp {
765 fsl,pins = < 739 fsl,pins = <
766 MX8MM_IOMUXC_SD1_STROB 740 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
767 >; 741 >;
768 }; 742 };
769 743
770 pinctrl_uart2: uart2grp { 744 pinctrl_uart2: uart2grp {
771 fsl,pins = < 745 fsl,pins = <
772 MX8MM_IOMUXC_UART2_RXD 746 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
773 MX8MM_IOMUXC_UART2_TXD 747 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
774 >; 748 >;
775 }; 749 };
776 750
777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp 751 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
778 fsl,pins = < 752 fsl,pins = <
779 MX8MM_IOMUXC_GPIO1_IO1 753 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
780 >; 754 >;
781 }; 755 };
782 756
783 pinctrl_usdhc2: usdhc2grp { 757 pinctrl_usdhc2: usdhc2grp {
784 fsl,pins = < 758 fsl,pins = <
785 MX8MM_IOMUXC_SD2_CLK_U 759 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
786 MX8MM_IOMUXC_SD2_CMD_U 760 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
787 MX8MM_IOMUXC_SD2_DATA0 761 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
788 MX8MM_IOMUXC_SD2_DATA1 762 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
789 MX8MM_IOMUXC_SD2_DATA2 763 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
790 MX8MM_IOMUXC_SD2_DATA3 764 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
791 MX8MM_IOMUXC_GPIO1_IO0 765 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
792 >; 766 >;
793 }; 767 };
794 768
795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 769 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
796 fsl,pins = < 770 fsl,pins = <
797 MX8MM_IOMUXC_SD2_CLK_U 771 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
798 MX8MM_IOMUXC_SD2_CMD_U 772 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
799 MX8MM_IOMUXC_SD2_DATA0 773 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
800 MX8MM_IOMUXC_SD2_DATA1 774 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
801 MX8MM_IOMUXC_SD2_DATA2 775 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
802 MX8MM_IOMUXC_SD2_DATA3 776 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
803 MX8MM_IOMUXC_GPIO1_IO0 777 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
804 >; 778 >;
805 }; 779 };
806 780
807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 781 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
808 fsl,pins = < 782 fsl,pins = <
809 MX8MM_IOMUXC_SD2_CLK_U 783 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
810 MX8MM_IOMUXC_SD2_CMD_U 784 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
811 MX8MM_IOMUXC_SD2_DATA0 785 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
812 MX8MM_IOMUXC_SD2_DATA1 786 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
813 MX8MM_IOMUXC_SD2_DATA2 787 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
814 MX8MM_IOMUXC_SD2_DATA3 788 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
815 MX8MM_IOMUXC_GPIO1_IO0 789 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 790 >;
817 }; 791 };
818 792
819 pinctrl_wdog: wdoggrp { 793 pinctrl_wdog: wdoggrp {
820 fsl,pins = < 794 fsl,pins = <
821 MX8MM_IOMUXC_GPIO1_IO0 795 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
822 >; 796 >;
823 }; 797 };
824 798
825 pinctrl_backlight: backlightgrp { 799 pinctrl_backlight: backlightgrp {
826 fsl,pins = < 800 fsl,pins = <
827 MX8MM_IOMUXC_GPIO1_IO0 801 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
828 >; 802 >;
829 }; 803 };
830 804
831 pinctrl_camera: cameragrp { 805 pinctrl_camera: cameragrp {
832 fsl,pins = < 806 fsl,pins = <
833 MX8MM_IOMUXC_GPIO1_IO0 807 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
834 MX8MM_IOMUXC_GPIO1_IO0 808 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
835 MX8MM_IOMUXC_GPIO1_IO1 809 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
836 >; 810 >;
837 }; 811 };
838 }; 812 };
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