1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 #include "imx8mm.dtsi" 10 #include "imx8mm.dtsi"
11 11
12 / { 12 / {
13 chosen { 13 chosen {
14 stdout-path = &uart2; 14 stdout-path = &uart2;
15 }; 15 };
16 16
17 memory@40000000 { 17 memory@40000000 {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x8000 19 reg = <0x0 0x40000000 0 0x80000000>;
20 }; 20 };
21 21
22 hdmi-connector { 22 hdmi-connector {
23 compatible = "hdmi-connector"; 23 compatible = "hdmi-connector";
24 label = "hdmi"; 24 label = "hdmi";
25 type = "a"; 25 type = "a";
26 26
27 port { 27 port {
28 hdmi_connector_in: end 28 hdmi_connector_in: endpoint {
29 remote-endpoin 29 remote-endpoint = <&adv7535_out>;
30 }; 30 };
31 }; 31 };
32 }; 32 };
33 33
34 leds { 34 leds {
35 compatible = "gpio-leds"; 35 compatible = "gpio-leds";
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_led 37 pinctrl-0 = <&pinctrl_gpio_led>;
38 38
39 status { 39 status {
40 label = "status"; 40 label = "status";
41 gpios = <&gpio3 16 GPI 41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42 default-state = "on"; 42 default-state = "on";
43 }; 43 };
44 }; 44 };
45 45
46 pcie0_refclk: pcie0-refclk { 46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock"; 47 compatible = "fixed-clock";
48 #clock-cells = <0>; 48 #clock-cells = <0>;
49 clock-frequency = <100000000>; 49 clock-frequency = <100000000>;
50 }; 50 };
51 51
52 reg_pcie0: regulator-pcie { 52 reg_pcie0: regulator-pcie {
53 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_pcie0_re 55 pinctrl-0 = <&pinctrl_pcie0_reg>;
56 regulator-name = "MPCIE_3V3"; 56 regulator-name = "MPCIE_3V3";
57 regulator-min-microvolt = <330 57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <330 58 regulator-max-microvolt = <3300000>;
59 gpio = <&gpio1 5 GPIO_ACTIVE_H 59 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
60 enable-active-high; 60 enable-active-high;
61 }; 61 };
62 62
63 reg_usdhc2_vmmc: regulator-usdhc2 { 63 reg_usdhc2_vmmc: regulator-usdhc2 {
64 compatible = "regulator-fixed" 64 compatible = "regulator-fixed";
65 pinctrl-names = "default"; 65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_reg_usdh 66 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67 regulator-name = "VSD_3V3"; 67 regulator-name = "VSD_3V3";
68 regulator-min-microvolt = <330 68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
70 gpio = <&gpio2 19 GPIO_ACTIVE_ 70 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71 off-on-delay-us = <20000>; 71 off-on-delay-us = <20000>;
72 enable-active-high; 72 enable-active-high;
73 }; 73 };
74 74
75 reg_1v5: regulator-1v5 { 75 reg_1v5: regulator-1v5 {
76 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
77 regulator-name = "VDD_1V5"; 77 regulator-name = "VDD_1V5";
78 regulator-min-microvolt = <150 78 regulator-min-microvolt = <1500000>;
79 regulator-max-microvolt = <150 79 regulator-max-microvolt = <1500000>;
80 }; 80 };
81 81
82 reg_1v8: regulator-1v8 { 82 reg_1v8: regulator-1v8 {
83 compatible = "regulator-fixed" 83 compatible = "regulator-fixed";
84 regulator-name = "VDD_1V8"; 84 regulator-name = "VDD_1V8";
85 regulator-min-microvolt = <180 85 regulator-min-microvolt = <1800000>;
86 regulator-max-microvolt = <180 86 regulator-max-microvolt = <1800000>;
87 }; 87 };
88 88
89 reg_vddext_3v3: regulator-vddext-3v3 { 89 reg_vddext_3v3: regulator-vddext-3v3 {
90 compatible = "regulator-fixed" 90 compatible = "regulator-fixed";
91 regulator-name = "VDDEXT_3V3"; 91 regulator-name = "VDDEXT_3V3";
92 regulator-min-microvolt = <330 92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <330 93 regulator-max-microvolt = <3300000>;
94 }; 94 };
95 95
96 backlight: backlight { 96 backlight: backlight {
97 compatible = "pwm-backlight"; 97 compatible = "pwm-backlight";
98 pwms = <&pwm1 0 5000000 0>; 98 pwms = <&pwm1 0 5000000 0>;
99 brightness-levels = <0 255>; 99 brightness-levels = <0 255>;
100 num-interpolated-steps = <255> 100 num-interpolated-steps = <255>;
101 default-brightness-level = <25 101 default-brightness-level = <250>;
102 }; 102 };
103 103
104 ir-receiver { 104 ir-receiver {
105 compatible = "gpio-ir-receiver 105 compatible = "gpio-ir-receiver";
106 gpios = <&gpio1 13 GPIO_ACTIVE 106 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
107 pinctrl-names = "default"; 107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_ir>; 108 pinctrl-0 = <&pinctrl_ir>;
109 linux,autosuspend-period = <12 109 linux,autosuspend-period = <125>;
110 }; 110 };
111 111
112 audio_codec_bt_sco: audio-codec-bt-sco 112 audio_codec_bt_sco: audio-codec-bt-sco {
113 compatible = "linux,bt-sco"; 113 compatible = "linux,bt-sco";
114 #sound-dai-cells = <1>; 114 #sound-dai-cells = <1>;
115 }; 115 };
116 116
117 wm8524: audio-codec { 117 wm8524: audio-codec {
118 #sound-dai-cells = <0>; 118 #sound-dai-cells = <0>;
119 compatible = "wlf,wm8524"; 119 compatible = "wlf,wm8524";
120 pinctrl-names = "default"; 120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_gpio_wlf 121 pinctrl-0 = <&pinctrl_gpio_wlf>;
122 wlf,mute-gpios = <&gpio5 21 GP 122 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
123 }; 123 };
124 124
125 sound-bt-sco { 125 sound-bt-sco {
126 compatible = "simple-audio-car 126 compatible = "simple-audio-card";
127 simple-audio-card,name = "bt-s 127 simple-audio-card,name = "bt-sco-audio";
128 simple-audio-card,format = "ds 128 simple-audio-card,format = "dsp_a";
129 simple-audio-card,bitclock-inv 129 simple-audio-card,bitclock-inversion;
130 simple-audio-card,frame-master 130 simple-audio-card,frame-master = <&btcpu>;
131 simple-audio-card,bitclock-mas 131 simple-audio-card,bitclock-master = <&btcpu>;
132 132
133 btcpu: simple-audio-card,cpu { 133 btcpu: simple-audio-card,cpu {
134 sound-dai = <&sai2>; 134 sound-dai = <&sai2>;
135 dai-tdm-slot-num = <2> 135 dai-tdm-slot-num = <2>;
136 dai-tdm-slot-width = < 136 dai-tdm-slot-width = <16>;
137 }; 137 };
138 138
139 simple-audio-card,codec { 139 simple-audio-card,codec {
140 sound-dai = <&audio_co 140 sound-dai = <&audio_codec_bt_sco 1>;
141 }; 141 };
142 }; 142 };
143 143
144 sound-wm8524 { 144 sound-wm8524 {
145 compatible = "simple-audio-car 145 compatible = "simple-audio-card";
146 simple-audio-card,name = "wm85 146 simple-audio-card,name = "wm8524-audio";
147 simple-audio-card,format = "i2 147 simple-audio-card,format = "i2s";
148 simple-audio-card,frame-master 148 simple-audio-card,frame-master = <&cpudai>;
149 simple-audio-card,bitclock-mas 149 simple-audio-card,bitclock-master = <&cpudai>;
150 simple-audio-card,widgets = 150 simple-audio-card,widgets =
151 "Line", "Left Line Out 151 "Line", "Left Line Out Jack",
152 "Line", "Right Line Ou 152 "Line", "Right Line Out Jack";
153 simple-audio-card,routing = 153 simple-audio-card,routing =
154 "Left Line Out Jack", 154 "Left Line Out Jack", "LINEVOUTL",
155 "Right Line Out Jack", 155 "Right Line Out Jack", "LINEVOUTR";
156 156
157 cpudai: simple-audio-card,cpu 157 cpudai: simple-audio-card,cpu {
158 sound-dai = <&sai3>; 158 sound-dai = <&sai3>;
159 dai-tdm-slot-num = <2> 159 dai-tdm-slot-num = <2>;
160 dai-tdm-slot-width = < 160 dai-tdm-slot-width = <32>;
161 }; 161 };
162 162
163 simple-audio-card,codec { 163 simple-audio-card,codec {
164 sound-dai = <&wm8524>; 164 sound-dai = <&wm8524>;
165 clocks = <&clk IMX8MM_ 165 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
166 }; 166 };
167 }; 167 };
168 168
169 sound-micfil { 169 sound-micfil {
170 compatible = "fsl,imx-audio-ca 170 compatible = "fsl,imx-audio-card";
171 model = "micfil-audio"; 171 model = "micfil-audio";
172 172
173 pri-dai-link { 173 pri-dai-link {
174 link-name = "micfil hi 174 link-name = "micfil hifi";
175 format = "i2s"; 175 format = "i2s";
176 176
177 cpu { 177 cpu {
178 sound-dai = <& 178 sound-dai = <&micfil>;
179 }; 179 };
180 }; 180 };
181 }; 181 };
182 182
183 spdif_out: spdif-out { 183 spdif_out: spdif-out {
184 compatible = "linux,spdif-dit" 184 compatible = "linux,spdif-dit";
185 #sound-dai-cells = <0>; 185 #sound-dai-cells = <0>;
186 }; 186 };
187 187
188 spdif_in: spdif-in { 188 spdif_in: spdif-in {
189 compatible = "linux,spdif-dir" 189 compatible = "linux,spdif-dir";
190 #sound-dai-cells = <0>; 190 #sound-dai-cells = <0>;
191 }; 191 };
192 192
193 sound-spdif { 193 sound-spdif {
194 compatible = "fsl,imx-audio-sp 194 compatible = "fsl,imx-audio-spdif";
195 model = "imx-spdif"; 195 model = "imx-spdif";
196 audio-cpu = <&spdif1>; 196 audio-cpu = <&spdif1>;
197 audio-codec = <&spdif_out>, <& 197 audio-codec = <&spdif_out>, <&spdif_in>;
198 }; 198 };
199 }; 199 };
200 200
201 &A53_0 { 201 &A53_0 {
202 cpu-supply = <&buck2_reg>; 202 cpu-supply = <&buck2_reg>;
203 }; 203 };
204 204
205 &A53_1 { 205 &A53_1 {
206 cpu-supply = <&buck2_reg>; 206 cpu-supply = <&buck2_reg>;
207 }; 207 };
208 208
209 &A53_2 { 209 &A53_2 {
210 cpu-supply = <&buck2_reg>; 210 cpu-supply = <&buck2_reg>;
211 }; 211 };
212 212
213 &A53_3 { 213 &A53_3 {
214 cpu-supply = <&buck2_reg>; 214 cpu-supply = <&buck2_reg>;
215 }; 215 };
216 216
217 &fec1 { 217 &fec1 {
218 pinctrl-names = "default"; 218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec1>; 219 pinctrl-0 = <&pinctrl_fec1>;
220 phy-mode = "rgmii-id"; 220 phy-mode = "rgmii-id";
221 phy-handle = <ðphy0>; 221 phy-handle = <ðphy0>;
222 fsl,magic-packet; 222 fsl,magic-packet;
223 status = "okay"; 223 status = "okay";
224 224
225 mdio { 225 mdio {
226 #address-cells = <1>; 226 #address-cells = <1>;
227 #size-cells = <0>; 227 #size-cells = <0>;
228 228
229 ethphy0: ethernet-phy@0 { 229 ethphy0: ethernet-phy@0 {
230 compatible = "ethernet 230 compatible = "ethernet-phy-ieee802.3-c22";
231 reg = <0>; 231 reg = <0>;
232 reset-gpios = <&gpio4 232 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
233 reset-assert-us = <100 233 reset-assert-us = <10000>;
234 qca,disable-smarteee; 234 qca,disable-smarteee;
235 vddio-supply = <&vddio 235 vddio-supply = <&vddio>;
236 236
237 vddio: vddio-regulator 237 vddio: vddio-regulator {
238 regulator-min- 238 regulator-min-microvolt = <1800000>;
239 regulator-max- 239 regulator-max-microvolt = <1800000>;
240 }; 240 };
241 }; 241 };
242 }; 242 };
243 }; 243 };
244 244
245 &i2c1 { 245 &i2c1 {
246 clock-frequency = <400000>; 246 clock-frequency = <400000>;
247 pinctrl-names = "default"; 247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>; 248 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay"; 249 status = "okay";
250 250
251 pmic@4b { 251 pmic@4b {
252 compatible = "rohm,bd71847"; 252 compatible = "rohm,bd71847";
253 reg = <0x4b>; 253 reg = <0x4b>;
254 pinctrl-names = "default"; 254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_pmic>; 255 pinctrl-0 = <&pinctrl_pmic>;
256 interrupt-parent = <&gpio1>; 256 interrupt-parent = <&gpio1>;
257 interrupts = <3 IRQ_TYPE_LEVEL 257 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
258 rohm,reset-snvs-powered; 258 rohm,reset-snvs-powered;
259 259
260 #clock-cells = <0>; 260 #clock-cells = <0>;
261 clocks = <&osc_32k>; 261 clocks = <&osc_32k>;
262 clock-output-names = "clk-32k- 262 clock-output-names = "clk-32k-out";
263 263
264 regulators { 264 regulators {
265 buck1_reg: BUCK1 { 265 buck1_reg: BUCK1 {
266 regulator-name 266 regulator-name = "buck1";
267 regulator-min- 267 regulator-min-microvolt = <700000>;
268 regulator-max- 268 regulator-max-microvolt = <1300000>;
269 regulator-boot 269 regulator-boot-on;
270 regulator-alwa 270 regulator-always-on;
271 regulator-ramp 271 regulator-ramp-delay = <1250>;
272 }; 272 };
273 273
274 buck2_reg: BUCK2 { 274 buck2_reg: BUCK2 {
275 regulator-name 275 regulator-name = "buck2";
276 regulator-min- 276 regulator-min-microvolt = <700000>;
277 regulator-max- 277 regulator-max-microvolt = <1300000>;
278 regulator-boot 278 regulator-boot-on;
279 regulator-alwa 279 regulator-always-on;
280 regulator-ramp 280 regulator-ramp-delay = <1250>;
281 rohm,dvs-run-v 281 rohm,dvs-run-voltage = <1000000>;
282 rohm,dvs-idle- 282 rohm,dvs-idle-voltage = <900000>;
283 }; 283 };
284 284
285 buck3_reg: BUCK3 { 285 buck3_reg: BUCK3 {
286 // BUCK5 in da 286 // BUCK5 in datasheet
287 regulator-name 287 regulator-name = "buck3";
288 regulator-min- 288 regulator-min-microvolt = <700000>;
289 regulator-max- 289 regulator-max-microvolt = <1350000>;
290 regulator-boot 290 regulator-boot-on;
291 regulator-alwa 291 regulator-always-on;
292 }; 292 };
293 293
294 buck4_reg: BUCK4 { 294 buck4_reg: BUCK4 {
295 // BUCK6 in da 295 // BUCK6 in datasheet
296 regulator-name 296 regulator-name = "buck4";
297 regulator-min- 297 regulator-min-microvolt = <3000000>;
298 regulator-max- 298 regulator-max-microvolt = <3300000>;
299 regulator-boot 299 regulator-boot-on;
300 regulator-alwa 300 regulator-always-on;
301 }; 301 };
302 302
303 buck5_reg: BUCK5 { 303 buck5_reg: BUCK5 {
304 // BUCK7 in da 304 // BUCK7 in datasheet
305 regulator-name 305 regulator-name = "buck5";
306 regulator-min- 306 regulator-min-microvolt = <1605000>;
307 regulator-max- 307 regulator-max-microvolt = <1995000>;
308 regulator-boot 308 regulator-boot-on;
309 regulator-alwa 309 regulator-always-on;
310 }; 310 };
311 311
312 buck6_reg: BUCK6 { 312 buck6_reg: BUCK6 {
313 // BUCK8 in da 313 // BUCK8 in datasheet
314 regulator-name 314 regulator-name = "buck6";
315 regulator-min- 315 regulator-min-microvolt = <800000>;
316 regulator-max- 316 regulator-max-microvolt = <1400000>;
317 regulator-boot 317 regulator-boot-on;
318 regulator-alwa 318 regulator-always-on;
319 }; 319 };
320 320
321 ldo1_reg: LDO1 { 321 ldo1_reg: LDO1 {
322 regulator-name 322 regulator-name = "ldo1";
323 regulator-min- 323 regulator-min-microvolt = <1600000>;
324 regulator-max- 324 regulator-max-microvolt = <3300000>;
325 regulator-boot 325 regulator-boot-on;
326 regulator-alwa 326 regulator-always-on;
327 }; 327 };
328 328
329 ldo2_reg: LDO2 { 329 ldo2_reg: LDO2 {
330 regulator-name 330 regulator-name = "ldo2";
331 regulator-min- 331 regulator-min-microvolt = <800000>;
332 regulator-max- 332 regulator-max-microvolt = <900000>;
333 regulator-boot 333 regulator-boot-on;
334 regulator-alwa 334 regulator-always-on;
335 }; 335 };
336 336
337 ldo3_reg: LDO3 { 337 ldo3_reg: LDO3 {
338 regulator-name 338 regulator-name = "ldo3";
339 regulator-min- 339 regulator-min-microvolt = <1800000>;
340 regulator-max- 340 regulator-max-microvolt = <3300000>;
341 regulator-boot 341 regulator-boot-on;
342 regulator-alwa 342 regulator-always-on;
343 }; 343 };
344 344
345 ldo4_reg: LDO4 { 345 ldo4_reg: LDO4 {
346 regulator-name 346 regulator-name = "ldo4";
347 regulator-min- 347 regulator-min-microvolt = <900000>;
348 regulator-max- 348 regulator-max-microvolt = <1800000>;
349 regulator-boot 349 regulator-boot-on;
350 regulator-alwa 350 regulator-always-on;
351 }; 351 };
352 352
353 ldo6_reg: LDO6 { 353 ldo6_reg: LDO6 {
354 regulator-name 354 regulator-name = "ldo6";
355 regulator-min- 355 regulator-min-microvolt = <900000>;
356 regulator-max- 356 regulator-max-microvolt = <1800000>;
357 regulator-boot 357 regulator-boot-on;
358 regulator-alwa 358 regulator-always-on;
359 }; 359 };
360 }; 360 };
361 }; 361 };
362 }; 362 };
363 363
364 &i2c2 { 364 &i2c2 {
365 clock-frequency = <400000>; 365 clock-frequency = <400000>;
366 pinctrl-names = "default"; 366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c2>; 367 pinctrl-0 = <&pinctrl_i2c2>;
368 status = "okay"; 368 status = "okay";
369 369
370 hdmi@3d { 370 hdmi@3d {
371 compatible = "adi,adv7535"; 371 compatible = "adi,adv7535";
372 reg = <0x3d>; 372 reg = <0x3d>;
373 interrupt-parent = <&gpio1>; 373 interrupt-parent = <&gpio1>;
374 interrupts = <9 IRQ_TYPE_EDGE_ 374 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
375 adi,dsi-lanes = <4>; 375 adi,dsi-lanes = <4>;
376 avdd-supply = <&buck5_reg>; 376 avdd-supply = <&buck5_reg>;
377 dvdd-supply = <&buck5_reg>; 377 dvdd-supply = <&buck5_reg>;
378 pvdd-supply = <&buck5_reg>; 378 pvdd-supply = <&buck5_reg>;
379 a2vdd-supply = <&buck5_reg>; 379 a2vdd-supply = <&buck5_reg>;
380 v3p3-supply = <®_vddext_3v3 380 v3p3-supply = <®_vddext_3v3>;
381 v1p2-supply = <&buck5_reg>; 381 v1p2-supply = <&buck5_reg>;
382 382
383 ports { 383 ports {
384 #address-cells = <1>; 384 #address-cells = <1>;
385 #size-cells = <0>; 385 #size-cells = <0>;
386 386
387 port@0 { 387 port@0 {
388 reg = <0>; 388 reg = <0>;
389 389
390 adv7535_in: en 390 adv7535_in: endpoint {
391 remote 391 remote-endpoint = <&dsi_out>;
392 }; 392 };
393 }; 393 };
394 394
395 port@1 { 395 port@1 {
396 reg = <1>; 396 reg = <1>;
397 397
398 adv7535_out: e 398 adv7535_out: endpoint {
399 remote 399 remote-endpoint = <&hdmi_connector_in>;
400 }; 400 };
401 }; 401 };
402 402
403 }; 403 };
404 }; 404 };
405 405
406 ptn5110: tcpc@50 { 406 ptn5110: tcpc@50 {
407 compatible = "nxp,ptn5110", "t 407 compatible = "nxp,ptn5110", "tcpci";
408 pinctrl-names = "default"; 408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_typec1>; 409 pinctrl-0 = <&pinctrl_typec1>;
410 reg = <0x50>; 410 reg = <0x50>;
411 interrupt-parent = <&gpio2>; 411 interrupt-parent = <&gpio2>;
412 interrupts = <11 IRQ_TYPE_LEVE 412 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
413 status = "okay"; 413 status = "okay";
414 414
415 typec1_con: connector { 415 typec1_con: connector {
416 compatible = "usb-c-co 416 compatible = "usb-c-connector";
417 label = "USB-C"; 417 label = "USB-C";
418 power-role = "dual"; 418 power-role = "dual";
419 data-role = "dual"; 419 data-role = "dual";
420 try-power-role = "sink 420 try-power-role = "sink";
421 source-pdos = <PDO_FIX 421 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
422 sink-pdos = <PDO_FIXED 422 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
423 PDO_VAR(5 423 PDO_VAR(5000, 20000, 3000)>;
424 op-sink-microwatt = <1 424 op-sink-microwatt = <15000000>;
425 self-powered; 425 self-powered;
426 426
427 port { 427 port {
428 typec1_dr_sw: 428 typec1_dr_sw: endpoint {
429 remote 429 remote-endpoint = <&usb1_drd_sw>;
430 }; 430 };
431 }; 431 };
432 }; 432 };
433 }; 433 };
434 }; 434 };
435 435
436 436
437 &csi { 437 &csi {
438 status = "okay"; 438 status = "okay";
439 }; 439 };
440 440
441 &i2c3 { 441 &i2c3 {
442 clock-frequency = <400000>; 442 clock-frequency = <400000>;
443 pinctrl-names = "default"; 443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>; 444 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay"; 445 status = "okay";
446 446
447 pca6416: gpio@20 { 447 pca6416: gpio@20 {
448 compatible = "nxp,pca6416"; 448 compatible = "nxp,pca6416";
449 reg = <0x20>; 449 reg = <0x20>;
450 gpio-controller; 450 gpio-controller;
451 #gpio-cells = <2>; 451 #gpio-cells = <2>;
452 vcc-supply = <&buck4_reg>; 452 vcc-supply = <&buck4_reg>;
453 }; 453 };
454 454
455 camera@3c { 455 camera@3c {
456 compatible = "ovti,ov5640"; 456 compatible = "ovti,ov5640";
457 reg = <0x3c>; 457 reg = <0x3c>;
458 pinctrl-names = "default"; 458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_camera>; 459 pinctrl-0 = <&pinctrl_camera>;
460 clocks = <&clk IMX8MM_CLK_CLKO 460 clocks = <&clk IMX8MM_CLK_CLKO1>;
461 clock-names = "xclk"; 461 clock-names = "xclk";
462 assigned-clocks = <&clk IMX8MM 462 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
463 assigned-clock-parents = <&clk 463 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
464 assigned-clock-rates = <240000 464 assigned-clock-rates = <24000000>;
465 powerdown-gpios = <&gpio1 7 GP 465 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
466 reset-gpios = <&gpio1 6 GPIO_A 466 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
467 DOVDD-supply = <&buck5_reg>; 467 DOVDD-supply = <&buck5_reg>;
468 AVDD-supply = <®_1v8>; 468 AVDD-supply = <®_1v8>;
469 DVDD-supply = <®_1v5>; 469 DVDD-supply = <®_1v5>;
470 470
471 port { 471 port {
472 ov5640_to_mipi_csi2: e 472 ov5640_to_mipi_csi2: endpoint {
473 remote-endpoin 473 remote-endpoint = <&imx8mm_mipi_csi_in>;
474 clock-lanes = 474 clock-lanes = <0>;
475 data-lanes = < 475 data-lanes = <1 2>;
476 }; 476 };
477 }; 477 };
478 }; 478 };
479 }; 479 };
480 480
481 &lcdif { 481 &lcdif {
482 status = "okay"; 482 status = "okay";
483 }; 483 };
484 484
485 &micfil { 485 &micfil {
486 #sound-dai-cells = <0>; 486 #sound-dai-cells = <0>;
487 pinctrl-names = "default"; 487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_pdm>; 488 pinctrl-0 = <&pinctrl_pdm>;
489 assigned-clocks = <&clk IMX8MM_CLK_PDM 489 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
490 assigned-clock-parents = <&clk IMX8MM_ 490 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
491 assigned-clock-rates = <196608000>; 491 assigned-clock-rates = <196608000>;
492 status = "okay"; 492 status = "okay";
493 }; 493 };
494 494
495 &mipi_csi { 495 &mipi_csi {
496 status = "okay"; 496 status = "okay";
497 497
498 ports { 498 ports {
499 port@0 { 499 port@0 {
500 imx8mm_mipi_csi_in: en 500 imx8mm_mipi_csi_in: endpoint {
501 remote-endpoin 501 remote-endpoint = <&ov5640_to_mipi_csi2>;
502 data-lanes = < 502 data-lanes = <1 2>;
503 }; 503 };
504 }; 504 };
505 }; 505 };
506 }; 506 };
507 507
508 &mipi_dsi { 508 &mipi_dsi {
509 samsung,esc-clock-frequency = <1000000 509 samsung,esc-clock-frequency = <10000000>;
510 status = "okay"; 510 status = "okay";
511 511
512 ports { 512 ports {
513 port@1 { 513 port@1 {
514 reg = <1>; 514 reg = <1>;
515 515
516 dsi_out: endpoint { 516 dsi_out: endpoint {
517 remote-endpoin 517 remote-endpoint = <&adv7535_in>;
518 data-lanes = < 518 data-lanes = <1 2 3 4>;
519 }; 519 };
520 }; 520 };
521 }; 521 };
522 }; 522 };
523 523
524 &pcie_phy { 524 &pcie_phy {
525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 525 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
526 fsl,tx-deemph-gen1 = <0x2d>; 526 fsl,tx-deemph-gen1 = <0x2d>;
527 fsl,tx-deemph-gen2 = <0xf>; 527 fsl,tx-deemph-gen2 = <0xf>;
528 clocks = <&pcie0_refclk>; 528 clocks = <&pcie0_refclk>;
529 status = "okay"; 529 status = "okay";
530 }; 530 };
531 531
532 &pcie0 { 532 &pcie0 {
533 pinctrl-names = "default"; 533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_pcie0>; 534 pinctrl-0 = <&pinctrl_pcie0>;
535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LO 535 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 536 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
537 <&clk IMX8MM_CLK_PCIE1_AUX>; 537 <&clk IMX8MM_CLK_PCIE1_AUX>;
538 assigned-clocks = <&clk IMX8MM_CLK_PCI 538 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
539 <&clk IMX8MM_CLK_PCI 539 <&clk IMX8MM_CLK_PCIE1_CTRL>;
540 assigned-clock-rates = <10000000>, <25 540 assigned-clock-rates = <10000000>, <250000000>;
541 assigned-clock-parents = <&clk IMX8MM_ 541 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
542 <&clk IMX8MM_ 542 <&clk IMX8MM_SYS_PLL2_250M>;
543 vpcie-supply = <®_pcie0>; 543 vpcie-supply = <®_pcie0>;
544 status = "okay"; 544 status = "okay";
545 }; 545 };
546 546
547 &sai2 { 547 &sai2 {
548 #sound-dai-cells = <0>; 548 #sound-dai-cells = <0>;
549 pinctrl-names = "default"; 549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_sai2>; 550 pinctrl-0 = <&pinctrl_sai2>;
551 assigned-clocks = <&clk IMX8MM_CLK_SAI 551 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
552 assigned-clock-parents = <&clk IMX8MM_ 552 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
553 assigned-clock-rates = <24576000>; 553 assigned-clock-rates = <24576000>;
554 status = "okay"; 554 status = "okay";
555 }; 555 };
556 556
557 &sai3 { 557 &sai3 {
558 pinctrl-names = "default"; 558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_sai3>; 559 pinctrl-0 = <&pinctrl_sai3>;
560 assigned-clocks = <&clk IMX8MM_CLK_SAI 560 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
561 assigned-clock-parents = <&clk IMX8MM_ 561 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
562 assigned-clock-rates = <24576000>; 562 assigned-clock-rates = <24576000>;
563 status = "okay"; 563 status = "okay";
564 }; 564 };
565 565
566 &snvs_pwrkey { 566 &snvs_pwrkey {
567 status = "okay"; 567 status = "okay";
568 }; 568 };
569 569
570 &spdif1 { 570 &spdif1 {
571 pinctrl-names = "default"; 571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_spdif1>; 572 pinctrl-0 = <&pinctrl_spdif1>;
573 assigned-clocks = <&clk IMX8MM_CLK_SPD 573 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
574 assigned-clock-parents = <&clk IMX8MM_ 574 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
575 assigned-clock-rates = <24576000>; 575 assigned-clock-rates = <24576000>;
576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, 576 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
577 <&clk IMX8MM_CLK_SPDIF1>, <&c 577 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
578 <&clk IMX8MM_CLK_DUMMY>, <&cl 578 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
579 <&clk IMX8MM_CLK_AUDIO_AHB>, 579 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
580 <&clk IMX8MM_CLK_DUMMY>, <&cl 580 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
581 <&clk IMX8MM_AUDIO_PLL1_OUT>, 581 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
582 clock-names = "core", "rxtx0", "rxtx1" 582 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
583 "rxtx4", "rxtx5", "rxtx6 583 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
584 "pll8k", "pll11k"; 584 "pll8k", "pll11k";
585 status = "okay"; 585 status = "okay";
586 }; 586 };
587 587
588 &uart2 { /* console */ 588 &uart2 { /* console */
589 pinctrl-names = "default"; 589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart2>; 590 pinctrl-0 = <&pinctrl_uart2>;
591 status = "okay"; 591 status = "okay";
592 }; 592 };
593 593
594 &usbphynop1 { 594 &usbphynop1 {
595 wakeup-source; 595 wakeup-source;
596 }; 596 };
597 597
598 &usbotg1 { 598 &usbotg1 {
599 dr_mode = "otg"; 599 dr_mode = "otg";
600 hnp-disable; 600 hnp-disable;
601 srp-disable; 601 srp-disable;
602 adp-disable; 602 adp-disable;
603 usb-role-switch; 603 usb-role-switch;
604 disable-over-current; 604 disable-over-current;
605 samsung,picophy-pre-emp-curr-control = 605 samsung,picophy-pre-emp-curr-control = <3>;
606 samsung,picophy-dc-vol-level-adjust = 606 samsung,picophy-dc-vol-level-adjust = <7>;
607 status = "okay"; 607 status = "okay";
608 608
609 port { 609 port {
610 usb1_drd_sw: endpoint { 610 usb1_drd_sw: endpoint {
611 remote-endpoint = <&ty 611 remote-endpoint = <&typec1_dr_sw>;
612 }; 612 };
613 }; 613 };
614 }; 614 };
615 615
616 &usdhc2 { 616 &usdhc2 {
617 assigned-clocks = <&clk IMX8MM_CLK_USD 617 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
618 assigned-clock-rates = <200000000>; 618 assigned-clock-rates = <200000000>;
619 pinctrl-names = "default", "state_100m 619 pinctrl-names = "default", "state_100mhz", "state_200mhz";
620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 620 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 621 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 622 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 623 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
624 bus-width = <4>; 624 bus-width = <4>;
625 vmmc-supply = <®_usdhc2_vmmc>; 625 vmmc-supply = <®_usdhc2_vmmc>;
626 status = "okay"; 626 status = "okay";
627 }; 627 };
628 628
629 &wdog1 { 629 &wdog1 {
630 pinctrl-names = "default"; 630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_wdog>; 631 pinctrl-0 = <&pinctrl_wdog>;
632 fsl,ext-reset-output; 632 fsl,ext-reset-output;
633 status = "okay"; 633 status = "okay";
634 }; 634 };
635 635
636 &pwm1 { 636 &pwm1 {
637 pinctrl-names = "default"; 637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_backlight>; 638 pinctrl-0 = <&pinctrl_backlight>;
639 status = "okay"; 639 status = "okay";
640 }; 640 };
641 641
642 &iomuxc { 642 &iomuxc {
643 pinctrl_fec1: fec1grp { 643 pinctrl_fec1: fec1grp {
644 fsl,pins = < 644 fsl,pins = <
645 MX8MM_IOMUXC_ENET_MDC_ 645 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
646 MX8MM_IOMUXC_ENET_MDIO 646 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
647 MX8MM_IOMUXC_ENET_TD3_ 647 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
648 MX8MM_IOMUXC_ENET_TD2_ 648 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
649 MX8MM_IOMUXC_ENET_TD1_ 649 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
650 MX8MM_IOMUXC_ENET_TD0_ 650 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
651 MX8MM_IOMUXC_ENET_RD3_ 651 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
652 MX8MM_IOMUXC_ENET_RD2_ 652 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
653 MX8MM_IOMUXC_ENET_RD1_ 653 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
654 MX8MM_IOMUXC_ENET_RD0_ 654 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
655 MX8MM_IOMUXC_ENET_TXC_ 655 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
656 MX8MM_IOMUXC_ENET_RXC_ 656 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
657 MX8MM_IOMUXC_ENET_RX_C 657 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
658 MX8MM_IOMUXC_ENET_TX_C 658 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
659 MX8MM_IOMUXC_SAI2_RXC_ 659 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
660 >; 660 >;
661 }; 661 };
662 662
663 pinctrl_gpio_led: gpioledgrp { 663 pinctrl_gpio_led: gpioledgrp {
664 fsl,pins = < 664 fsl,pins = <
665 MX8MM_IOMUXC_NAND_READ 665 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
666 >; 666 >;
667 }; 667 };
668 668
669 pinctrl_ir: irgrp { 669 pinctrl_ir: irgrp {
670 fsl,pins = < 670 fsl,pins = <
671 MX8MM_IOMUXC_GPIO1_IO1 671 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
672 >; 672 >;
673 }; 673 };
674 674
675 pinctrl_gpio_wlf: gpiowlfgrp { 675 pinctrl_gpio_wlf: gpiowlfgrp {
676 fsl,pins = < 676 fsl,pins = <
677 MX8MM_IOMUXC_I2C4_SDA_ 677 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
678 >; 678 >;
679 }; 679 };
680 680
681 pinctrl_i2c1: i2c1grp { 681 pinctrl_i2c1: i2c1grp {
682 fsl,pins = < 682 fsl,pins = <
683 MX8MM_IOMUXC_I2C1_SCL_ 683 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
684 MX8MM_IOMUXC_I2C1_SDA_ 684 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
685 >; 685 >;
686 }; 686 };
687 687
688 pinctrl_i2c2: i2c2grp { 688 pinctrl_i2c2: i2c2grp {
689 fsl,pins = < 689 fsl,pins = <
690 MX8MM_IOMUXC_I2C2_SCL_ 690 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
691 MX8MM_IOMUXC_I2C2_SDA_ 691 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
692 >; 692 >;
693 }; 693 };
694 694
695 pinctrl_i2c3: i2c3grp { 695 pinctrl_i2c3: i2c3grp {
696 fsl,pins = < 696 fsl,pins = <
697 MX8MM_IOMUXC_I2C3_SCL_ 697 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
698 MX8MM_IOMUXC_I2C3_SDA_ 698 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
699 >; 699 >;
700 }; 700 };
701 701
702 pinctrl_pcie0: pcie0grp { 702 pinctrl_pcie0: pcie0grp {
703 fsl,pins = < 703 fsl,pins = <
704 MX8MM_IOMUXC_I2C4_SCL_ 704 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
705 MX8MM_IOMUXC_SAI2_RXFS 705 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
706 >; 706 >;
707 }; 707 };
708 708
709 pinctrl_pcie0_reg: pcie0reggrp { 709 pinctrl_pcie0_reg: pcie0reggrp {
710 fsl,pins = < 710 fsl,pins = <
711 MX8MM_IOMUXC_GPIO1_IO0 711 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
712 >; 712 >;
713 }; 713 };
714 714
715 pinctrl_pdm: pdmgrp { 715 pinctrl_pdm: pdmgrp {
716 fsl,pins = < 716 fsl,pins = <
717 MX8MM_IOMUXC_SAI5_MCLK 717 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
718 MX8MM_IOMUXC_SAI5_RXC_ 718 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
719 MX8MM_IOMUXC_SAI5_RXFS 719 MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
720 MX8MM_IOMUXC_SAI5_RXD0 720 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
721 MX8MM_IOMUXC_SAI5_RXD1 721 MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
722 MX8MM_IOMUXC_SAI5_RXD2 722 MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
723 MX8MM_IOMUXC_SAI5_RXD3 723 MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
724 >; 724 >;
725 }; 725 };
726 726
727 pinctrl_pmic: pmicirqgrp { 727 pinctrl_pmic: pmicirqgrp {
728 fsl,pins = < 728 fsl,pins = <
729 MX8MM_IOMUXC_GPIO1_IO0 729 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
730 >; 730 >;
731 }; 731 };
732 732
733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 733 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
734 fsl,pins = < 734 fsl,pins = <
735 MX8MM_IOMUXC_SD2_RESET 735 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
736 >; 736 >;
737 }; 737 };
738 738
739 pinctrl_sai2: sai2grp { 739 pinctrl_sai2: sai2grp {
740 fsl,pins = < 740 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXC_ 741 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
742 MX8MM_IOMUXC_SAI2_TXFS 742 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
743 MX8MM_IOMUXC_SAI2_TXD0 743 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
744 MX8MM_IOMUXC_SAI2_RXD0 744 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
745 >; 745 >;
746 }; 746 };
747 747
748 pinctrl_sai3: sai3grp { 748 pinctrl_sai3: sai3grp {
749 fsl,pins = < 749 fsl,pins = <
750 MX8MM_IOMUXC_SAI3_TXFS 750 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
751 MX8MM_IOMUXC_SAI3_TXC_ 751 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
752 MX8MM_IOMUXC_SAI3_MCLK 752 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
753 MX8MM_IOMUXC_SAI3_TXD_ 753 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
754 >; 754 >;
755 }; 755 };
756 756
757 pinctrl_spdif1: spdif1grp { 757 pinctrl_spdif1: spdif1grp {
758 fsl,pins = < 758 fsl,pins = <
759 MX8MM_IOMUXC_SPDIF_TX_ 759 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
760 MX8MM_IOMUXC_SPDIF_RX_ 760 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
761 >; 761 >;
762 }; 762 };
763 763
764 pinctrl_typec1: typec1grp { 764 pinctrl_typec1: typec1grp {
765 fsl,pins = < 765 fsl,pins = <
766 MX8MM_IOMUXC_SD1_STROB 766 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
767 >; 767 >;
768 }; 768 };
769 769
770 pinctrl_uart2: uart2grp { 770 pinctrl_uart2: uart2grp {
771 fsl,pins = < 771 fsl,pins = <
772 MX8MM_IOMUXC_UART2_RXD 772 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
773 MX8MM_IOMUXC_UART2_TXD 773 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
774 >; 774 >;
775 }; 775 };
776 776
777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp 777 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
778 fsl,pins = < 778 fsl,pins = <
779 MX8MM_IOMUXC_GPIO1_IO1 779 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
780 >; 780 >;
781 }; 781 };
782 782
783 pinctrl_usdhc2: usdhc2grp { 783 pinctrl_usdhc2: usdhc2grp {
784 fsl,pins = < 784 fsl,pins = <
785 MX8MM_IOMUXC_SD2_CLK_U 785 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
786 MX8MM_IOMUXC_SD2_CMD_U 786 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
787 MX8MM_IOMUXC_SD2_DATA0 787 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
788 MX8MM_IOMUXC_SD2_DATA1 788 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
789 MX8MM_IOMUXC_SD2_DATA2 789 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
790 MX8MM_IOMUXC_SD2_DATA3 790 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
791 MX8MM_IOMUXC_GPIO1_IO0 791 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
792 >; 792 >;
793 }; 793 };
794 794
795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 795 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
796 fsl,pins = < 796 fsl,pins = <
797 MX8MM_IOMUXC_SD2_CLK_U 797 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
798 MX8MM_IOMUXC_SD2_CMD_U 798 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
799 MX8MM_IOMUXC_SD2_DATA0 799 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
800 MX8MM_IOMUXC_SD2_DATA1 800 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
801 MX8MM_IOMUXC_SD2_DATA2 801 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
802 MX8MM_IOMUXC_SD2_DATA3 802 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
803 MX8MM_IOMUXC_GPIO1_IO0 803 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
804 >; 804 >;
805 }; 805 };
806 806
807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 807 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
808 fsl,pins = < 808 fsl,pins = <
809 MX8MM_IOMUXC_SD2_CLK_U 809 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
810 MX8MM_IOMUXC_SD2_CMD_U 810 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
811 MX8MM_IOMUXC_SD2_DATA0 811 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
812 MX8MM_IOMUXC_SD2_DATA1 812 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
813 MX8MM_IOMUXC_SD2_DATA2 813 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
814 MX8MM_IOMUXC_SD2_DATA3 814 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
815 MX8MM_IOMUXC_GPIO1_IO0 815 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 816 >;
817 }; 817 };
818 818
819 pinctrl_wdog: wdoggrp { 819 pinctrl_wdog: wdoggrp {
820 fsl,pins = < 820 fsl,pins = <
821 MX8MM_IOMUXC_GPIO1_IO0 821 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
822 >; 822 >;
823 }; 823 };
824 824
825 pinctrl_backlight: backlightgrp { 825 pinctrl_backlight: backlightgrp {
826 fsl,pins = < 826 fsl,pins = <
827 MX8MM_IOMUXC_GPIO1_IO0 827 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
828 >; 828 >;
829 }; 829 };
830 830
831 pinctrl_camera: cameragrp { 831 pinctrl_camera: cameragrp {
832 fsl,pins = < 832 fsl,pins = <
833 MX8MM_IOMUXC_GPIO1_IO0 833 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
834 MX8MM_IOMUXC_GPIO1_IO0 834 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
835 MX8MM_IOMUXC_GPIO1_IO1 835 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
836 >; 836 >;
837 }; 837 };
838 }; 838 };
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