1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2018 Bang & Olufsen
4 */
5
6 #include "imx8mm.dtsi"
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
8
9 / {
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed"
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_re
14 regulator-min-microvolt = <330
15 regulator-max-microvolt = <330
16 regulator-name = "epdev_on";
17 gpio = <&gpio3 16 GPIO_ACTIVE_
18 enable-active-high;
19 regulator-always-on;
20 };
21
22 reg_3v3_out: regulator-3v3-out {
23 compatible = "regulator-fixed"
24 regulator-name = "3V3_OUT";
25 regulator-min-microvolt = <330
26 regulator-max-microvolt = <330
27 };
28 };
29
30 &cpu_alert0 {
31 temperature = <95000>;
32 };
33
34 &cpu_crit0 {
35 temperature = <105000>;
36 };
37
38 &ddrc {
39 operating-points-v2 = <&ddrc_opp_table
40
41 ddrc_opp_table: opp-table {
42 compatible = "operating-points
43
44 opp-25000000 {
45 opp-hz = /bits/ 64 <25
46 };
47
48 opp-100000000 {
49 opp-hz = /bits/ 64 <10
50 };
51
52 opp-600000000 {
53 opp-hz = /bits/ 64 <60
54 };
55 };
56 };
57
58 &i2c1 {
59 clock-frequency = <100000>;
60 pinctrl-names = "default", "gpio";
61 pinctrl-0 = <&pinctrl_i2c1>;
62 pinctrl-1 = <&pinctrl_i2c1_gpio>;
63 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI
64 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI
65 status = "okay";
66
67 pmic@4b {
68 compatible = "rohm,bd71847";
69 reg = <0x4b>;
70 pinctrl-0 = <&pinctrl_pmic>;
71 interrupt-parent = <&gpio1>;
72 interrupts = <3 IRQ_TYPE_LEVEL
73 rohm,reset-snvs-powered;
74
75 regulators {
76 buck1_reg: BUCK1 {
77 regulator-name
78 regulator-min-
79 regulator-max-
80 regulator-boot
81 regulator-alwa
82 regulator-ramp
83 rohm,dvs-run-v
84 rohm,dvs-idle-
85 rohm,dvs-suspe
86 };
87
88 buck2_reg: BUCK2 {
89 regulator-name
90 regulator-min-
91 regulator-max-
92 regulator-boot
93 regulator-alwa
94 regulator-ramp
95 rohm,dvs-run-v
96 rohm,dvs-idle-
97 };
98
99 buck3_reg: BUCK3 {
100 // buck5 in da
101 regulator-name
102 regulator-min-
103 regulator-max-
104 regulator-boot
105 regulator-alwa
106 };
107
108 buck4_reg: BUCK4 {
109 // buck6 in da
110 regulator-name
111 regulator-min-
112 regulator-max-
113 regulator-boot
114 regulator-alwa
115 };
116
117 buck5_reg: BUCK5 {
118 // buck7 in da
119 regulator-name
120 regulator-min-
121 regulator-max-
122 regulator-boot
123 regulator-alwa
124 };
125
126 buck6_reg: BUCK6 {
127 // buck8 in da
128 regulator-name
129 regulator-min-
130 regulator-max-
131 regulator-boot
132 regulator-alwa
133 };
134
135 ldo1_reg: LDO1 {
136 regulator-name
137 regulator-min-
138 regulator-max-
139 regulator-boot
140 regulator-alwa
141 };
142
143 ldo2_reg: LDO2 {
144 regulator-name
145 regulator-min-
146 regulator-max-
147 regulator-boot
148 regulator-alwa
149 };
150
151 ldo3_reg: LDO3 {
152 regulator-name
153 regulator-min-
154 regulator-max-
155 regulator-boot
156 regulator-alwa
157 };
158
159 ldo4_reg: LDO4 {
160 regulator-name
161 regulator-min-
162 regulator-max-
163 regulator-boot
164 regulator-alwa
165 };
166
167 ldo5_reg: LDO5 {
168 regulator-name
169 regulator-min-
170 regulator-max-
171 };
172
173 ldo6_reg: LDO6 {
174 regulator-name
175 regulator-min-
176 regulator-max-
177 regulator-boot
178 regulator-alwa
179 };
180 };
181 };
182 };
183
184 &i2c2 {
185 clock-frequency = <100000>;
186 pinctrl-names = "default", "gpio";
187 pinctrl-0 = <&pinctrl_i2c2>;
188 pinctrl-1 = <&pinctrl_i2c2_gpio>;
189 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI
190 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI
191 status = "okay";
192 };
193
194 &i2c3 {
195 pinctrl-names = "default", "gpio";
196 pinctrl-0 = <&pinctrl_i2c3>;
197 pinctrl-1 = <&pinctrl_i2c3_gpio>;
198 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI
199 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI
200 };
201
202 &pcie_phy {
203 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
204 fsl,tx-deemph-gen1 = <0x2d>;
205 fsl,tx-deemph-gen2 = <0xf>;
206 status = "okay";
207 };
208
209 &pcie0 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_pcie0>;
212 reset-gpio = <&gpio5 21 GPIO_ACTIVE_LO
213 fsl,max-link-speed = <1>;
214 assigned-clocks = <&clk IMX8MM_CLK_PCI
215 assigned-clock-rates = <10000000>, <25
216 assigned-clock-parents = <&clk IMX8MM_
217 status = "okay";
218 };
219
220 &uart1 { /* BT */
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_uart1>;
223 assigned-clocks = <&clk IMX8MM_CLK_UAR
224 assigned-clock-parents = <&clk IMX8MM_
225 uart-has-rtscts;
226 status = "okay";
227
228 bluetooth {
229 compatible = "brcm,bcm4349-bt"
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_modem_bt
232 device-wakeup-gpios = <&gpio3
233 host-wakeup-gpios = <&gpio3 4
234 shutdown-gpios = <&gpio3 15 GP
235 vbat-supply = <®_3v3_out>;
236 vddio-supply = <®_3v3_out>;
237 clocks = <&osc_32k>;
238 max-speed = <3000000>;
239 clock-names = "extclk";
240 };
241 };
242
243 &uart2 { /* console */
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_uart2>;
246 };
247
248 &usdhc1 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_usdhc1>;
251 bus-width = <8>;
252 no-sd;
253 no-sdio;
254 non-removable;
255 status = "okay";
256 };
257
258 &usdhc2 {
259 pinctrl-names = "default", "state_100m
260 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
261 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
262 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
263 bus-width = <4>;
264 };
265
266 &wdog1 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_wdog>;
269 fsl,ext-reset-output;
270 status = "okay";
271 };
272
273 &A53_0 {
274 cpu-supply = <&buck2_reg>;
275 };
276
277 &A53_1 {
278 cpu-supply = <&buck2_reg>;
279 };
280
281 &A53_2 {
282 cpu-supply = <&buck2_reg>;
283 };
284
285 &A53_3 {
286 cpu-supply = <&buck2_reg>;
287 };
288
289 /delete-node/ &sec_jr1; /* Job ring in use by
290
291 &iomuxc {
292 pinctrl_i2c1: i2c1-grp {
293 fsl,pins = <
294 MX8MM_IOMUXC_I2C1_SCL_
295 MX8MM_IOMUXC_I2C1_SDA_
296 >;
297 };
298
299 pinctrl_i2c1_gpio: i2c1-gpio-grp {
300 fsl,pins = <
301 MX8MM_IOMUXC_I2C1_SCL_
302 MX8MM_IOMUXC_I2C1_SDA_
303 >;
304 };
305
306 pinctrl_i2c2: i2c2-grp {
307 fsl,pins = <
308 MX8MM_IOMUXC_I2C2_SCL_
309 MX8MM_IOMUXC_I2C2_SDA_
310 >;
311 };
312
313 pinctrl_i2c2_gpio: i2c2-gpio-grp {
314 fsl,pins = <
315 MX8MM_IOMUXC_I2C2_SCL_
316 MX8MM_IOMUXC_I2C2_SDA_
317 >;
318 };
319
320 pinctrl_i2c3: i2c3-grp {
321 fsl,pins = <
322 MX8MM_IOMUXC_I2C3_SCL_
323 MX8MM_IOMUXC_I2C3_SDA_
324 >;
325 };
326
327 pinctrl_i2c3_gpio: i2c3-gpio-grp {
328 fsl,pins = <
329 MX8MM_IOMUXC_I2C3_SCL_
330 MX8MM_IOMUXC_I2C3_SDA_
331 >;
332 };
333
334 pinctrl_pcie0: pcie0-grp {
335 fsl,pins = <
336 MX8MM_IOMUXC_I2C4_SCL_
337 MX8MM_IOMUXC_I2C4_SDA_
338 >;
339 };
340
341 pinctrl_modem_bt: modem-bt-grp {
342 fsl,pins = <
343 MX8MM_IOMUXC_NAND_CLE_
344 MX8MM_IOMUXC_NAND_CE2_
345 MX8MM_IOMUXC_NAND_CE3_
346 MX8MM_IOMUXC_NAND_RE_B
347 MX8MM_IOMUXC_GPIO1_IO0
348 >;
349 };
350
351 pinctrl_modem_regulator: modem-reg-grp
352 fsl,pins = <
353 MX8MM_IOMUXC_NAND_READ
354 >;
355 };
356
357 pinctrl_pmic: pmic-irq-grp {
358 fsl,pins = <
359 MX8MM_IOMUXC_GPIO1_IO0
360 >;
361 };
362
363 pinctrl_uart1: uart1-grp {
364 fsl,pins = <
365 MX8MM_IOMUXC_UART1_RXD
366 MX8MM_IOMUXC_UART1_TXD
367 MX8MM_IOMUXC_UART3_RXD
368 MX8MM_IOMUXC_UART3_TXD
369 >;
370 };
371
372 pinctrl_uart2: uart2-grp {
373 fsl,pins = <
374 MX8MM_IOMUXC_UART2_RXD
375 MX8MM_IOMUXC_UART2_TXD
376 >;
377 };
378
379 pinctrl_usdhc1: usdhc1-grp {
380 fsl,pins = <
381 MX8MM_IOMUXC_SD1_CLK_U
382 MX8MM_IOMUXC_SD1_CMD_U
383 MX8MM_IOMUXC_SD1_DATA0
384 MX8MM_IOMUXC_SD1_DATA1
385 MX8MM_IOMUXC_SD1_DATA2
386 MX8MM_IOMUXC_SD1_DATA3
387 MX8MM_IOMUXC_SD1_DATA4
388 MX8MM_IOMUXC_SD1_DATA5
389 MX8MM_IOMUXC_SD1_DATA6
390 MX8MM_IOMUXC_SD1_DATA7
391 MX8MM_IOMUXC_SD1_STROB
392 MX8MM_IOMUXC_SD1_RESET
393 >;
394 };
395
396 pinctrl_usdhc1_100mhz: usdhc1-100mhz-g
397 fsl,pins = <
398 MX8MM_IOMUXC_SD1_CLK_U
399 MX8MM_IOMUXC_SD1_CMD_U
400 MX8MM_IOMUXC_SD1_DATA0
401 MX8MM_IOMUXC_SD1_DATA1
402 MX8MM_IOMUXC_SD1_DATA2
403 MX8MM_IOMUXC_SD1_DATA3
404 MX8MM_IOMUXC_SD1_DATA4
405 MX8MM_IOMUXC_SD1_DATA5
406 MX8MM_IOMUXC_SD1_DATA6
407 MX8MM_IOMUXC_SD1_DATA7
408 MX8MM_IOMUXC_SD1_STROB
409 MX8MM_IOMUXC_SD1_RESET
410 >;
411 };
412
413 pinctrl_usdhc1_200mhz: usdhc1-200mhz-g
414 fsl,pins = <
415 MX8MM_IOMUXC_SD1_CLK_U
416 MX8MM_IOMUXC_SD1_CMD_U
417 MX8MM_IOMUXC_SD1_DATA0
418 MX8MM_IOMUXC_SD1_DATA1
419 MX8MM_IOMUXC_SD1_DATA2
420 MX8MM_IOMUXC_SD1_DATA3
421 MX8MM_IOMUXC_SD1_DATA4
422 MX8MM_IOMUXC_SD1_DATA5
423 MX8MM_IOMUXC_SD1_DATA6
424 MX8MM_IOMUXC_SD1_DATA7
425 MX8MM_IOMUXC_SD1_STROB
426 MX8MM_IOMUXC_SD1_RESET
427 >;
428 };
429
430 pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
431 fsl,pins = <
432 MX8MM_IOMUXC_SD2_RESET
433 >;
434 };
435
436 pinctrl_usdhc2: usdhc2-grp {
437 fsl,pins = <
438 MX8MM_IOMUXC_SD2_CLK_U
439 MX8MM_IOMUXC_SD2_CMD_U
440 MX8MM_IOMUXC_SD2_DATA0
441 MX8MM_IOMUXC_SD2_DATA1
442 MX8MM_IOMUXC_SD2_DATA2
443 MX8MM_IOMUXC_SD2_DATA3
444 MX8MM_IOMUXC_GPIO1_IO0
445 >;
446 };
447
448 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g
449 fsl,pins = <
450 MX8MM_IOMUXC_SD2_CLK_U
451 MX8MM_IOMUXC_SD2_CMD_U
452 MX8MM_IOMUXC_SD2_DATA0
453 MX8MM_IOMUXC_SD2_DATA1
454 MX8MM_IOMUXC_SD2_DATA2
455 MX8MM_IOMUXC_SD2_DATA3
456 MX8MM_IOMUXC_GPIO1_IO0
457 >;
458 };
459
460 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g
461 fsl,pins = <
462 MX8MM_IOMUXC_SD2_CLK_U
463 MX8MM_IOMUXC_SD2_CMD_U
464 MX8MM_IOMUXC_SD2_DATA0
465 MX8MM_IOMUXC_SD2_DATA1
466 MX8MM_IOMUXC_SD2_DATA2
467 MX8MM_IOMUXC_SD2_DATA3
468 MX8MM_IOMUXC_GPIO1_IO0
469 >;
470 };
471
472 pinctrl_wdog: wdog-grp {
473 fsl,pins = <
474 MX8MM_IOMUXC_GPIO1_IO0
475 >;
476 };
477 };
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