1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6 /dts-v1/;
7
8 #include "imx8mm-kontron-sl.dtsi"
9
10 / {
11 model = "Kontron BL i.MX8MM (N801X S)"
12 compatible = "kontron,imx8mm-bl", "kon
13
14 aliases {
15 ethernet1 = &usbnet;
16 rtc0 = &rx8900;
17 rtc1 = &snvs_rtc;
18 };
19
20 /* fixed crystal dedicated to mcp2515
21 osc_can: clock-osc-can {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <16000000>;
25 clock-output-names = "osc-can"
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_led
32
33 led1 {
34 label = "led1";
35 gpios = <&gpio4 17 GPI
36 linux,default-trigger
37 };
38
39 led2 {
40 label = "led2";
41 gpios = <&gpio4 19 GPI
42 };
43
44 led3 {
45 label = "led3";
46 gpios = <&gpio4 18 GPI
47 };
48
49 led4 {
50 label = "led4";
51 gpios = <&gpio4 8 GPIO
52 };
53
54 led5 {
55 label = "led5";
56 gpios = <&gpio4 9 GPIO
57 };
58
59 led6 {
60 label = "led6";
61 gpios = <&gpio4 7 GPIO
62 };
63 };
64
65 pwm-beeper {
66 compatible = "pwm-beeper";
67 pwms = <&pwm2 0 5000 0>;
68 };
69
70 reg_rst_eth2: regulator-rst-eth2 {
71 compatible = "regulator-fixed"
72 regulator-name = "rst-usb-eth2
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usb_eth2
75 gpio = <&gpio3 2 GPIO_ACTIVE_H
76 enable-active-high;
77 regulator-always-on;
78 };
79
80 reg_vdd_5v: regulator-5v {
81 compatible = "regulator-fixed"
82 regulator-name = "vdd-5v";
83 regulator-min-microvolt = <500
84 regulator-max-microvolt = <500
85 };
86 };
87
88 &ecspi2 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi2>;
91 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
92 status = "okay";
93
94 can0: can@0 {
95 compatible = "microchip,mcp251
96 reg = <0>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_can>;
99 clocks = <&osc_can>;
100 interrupt-parent = <&gpio4>;
101 interrupts = <28 IRQ_TYPE_EDGE
102 spi-max-frequency = <10000000>
103 vdd-supply = <®_vdd_3v3>;
104 xceiver-supply = <®_vdd_5v>
105 };
106 };
107
108 &ecspi3 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_ecspi3>;
111 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>
112 status = "okay";
113 };
114
115 &fec1 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_enet>;
118 phy-connection-type = "rgmii-rxid";
119 phy-handle = <ðphy>;
120 status = "okay";
121
122 mdio {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 ethphy: ethernet-phy@0 {
127 reg = <0>;
128 reset-assert-us = <1>;
129 reset-deassert-us = <1
130 reset-gpios = <&gpio4
131 };
132 };
133 };
134
135 &i2c4 {
136 clock-frequency = <100000>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c4>;
139 status = "okay";
140
141 rx8900: rtc@32 {
142 compatible = "epson,rx8900";
143 reg = <0x32>;
144 };
145 };
146
147 &pwm2 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_pwm2>;
150 status = "okay";
151 };
152
153 &uart1 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_uart1>;
156 uart-has-rtscts;
157 status = "okay";
158 };
159
160 &uart2 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart2>;
163 linux,rs485-enabled-at-boot-time;
164 uart-has-rtscts;
165 status = "okay";
166 };
167
168 &usbotg1 {
169 dr_mode = "otg";
170 over-current-active-low;
171 status = "okay";
172 };
173
174 &usbotg2 {
175 dr_mode = "host";
176 disable-over-current;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 status = "okay";
180
181 usb1@1 {
182 compatible = "usb424,9514";
183 reg = <1>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 usbnet: ethernet@1 {
188 compatible = "usb424,e
189 reg = <1>;
190 local-mac-address = [
191 };
192 };
193 };
194
195 &usdhc2 {
196 pinctrl-names = "default", "state_100m
197 pinctrl-0 = <&pinctrl_usdhc2>;
198 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
199 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
200 vmmc-supply = <®_vdd_3v3>;
201 vqmmc-supply = <®_nvcc_sd>;
202 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
203 status = "okay";
204 };
205
206 &iomuxc {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_gpio>;
209
210 pinctrl_can: cangrp {
211 fsl,pins = <
212 MX8MM_IOMUXC_SAI3_RXFS
213 >;
214 };
215
216 pinctrl_ecspi2: ecspi2grp {
217 fsl,pins = <
218 MX8MM_IOMUXC_ECSPI2_MI
219 MX8MM_IOMUXC_ECSPI2_MO
220 MX8MM_IOMUXC_ECSPI2_SC
221 MX8MM_IOMUXC_ECSPI2_SS
222 >;
223 };
224
225 pinctrl_ecspi3: ecspi3grp {
226 fsl,pins = <
227 MX8MM_IOMUXC_UART2_RXD
228 MX8MM_IOMUXC_UART1_TXD
229 MX8MM_IOMUXC_UART1_RXD
230 MX8MM_IOMUXC_UART2_TXD
231 >;
232 };
233
234 pinctrl_enet: enetgrp {
235 fsl,pins = <
236 MX8MM_IOMUXC_ENET_MDC_
237 MX8MM_IOMUXC_ENET_MDIO
238 MX8MM_IOMUXC_ENET_TD3_
239 MX8MM_IOMUXC_ENET_TD2_
240 MX8MM_IOMUXC_ENET_TD1_
241 MX8MM_IOMUXC_ENET_TD0_
242 MX8MM_IOMUXC_ENET_RD3_
243 MX8MM_IOMUXC_ENET_RD2_
244 MX8MM_IOMUXC_ENET_RD1_
245 MX8MM_IOMUXC_ENET_RD0_
246 MX8MM_IOMUXC_ENET_TXC_
247 MX8MM_IOMUXC_ENET_RXC_
248 MX8MM_IOMUXC_ENET_RX_C
249 MX8MM_IOMUXC_ENET_TX_C
250 MX8MM_IOMUXC_SAI2_MCLK
251 MX8MM_IOMUXC_SAI2_TXC_
252 >;
253 };
254
255 pinctrl_gpio_led: gpioledgrp {
256 fsl,pins = <
257 MX8MM_IOMUXC_NAND_READ
258 MX8MM_IOMUXC_SAI1_RXD5
259 MX8MM_IOMUXC_SAI1_RXD6
260 MX8MM_IOMUXC_SAI1_RXD7
261 MX8MM_IOMUXC_SAI1_TXD5
262 MX8MM_IOMUXC_SAI1_TXD6
263 MX8MM_IOMUXC_SAI1_TXD7
264 >;
265 };
266
267 pinctrl_gpio: gpiogrp {
268 fsl,pins = <
269 MX8MM_IOMUXC_GPIO1_IO0
270 MX8MM_IOMUXC_GPIO1_IO0
271 MX8MM_IOMUXC_GPIO1_IO0
272 MX8MM_IOMUXC_GPIO1_IO1
273 MX8MM_IOMUXC_GPIO1_IO0
274 MX8MM_IOMUXC_GPIO1_IO0
275 MX8MM_IOMUXC_GPIO1_IO1
276 MX8MM_IOMUXC_SAI3_MCLK
277 >;
278 };
279
280 pinctrl_i2c4: i2c4grp {
281 fsl,pins = <
282 MX8MM_IOMUXC_I2C4_SCL_
283 MX8MM_IOMUXC_I2C4_SDA_
284 >;
285 };
286
287 pinctrl_pwm2: pwm2grp {
288 fsl,pins = <
289 MX8MM_IOMUXC_SPDIF_RX_
290 >;
291 };
292
293 pinctrl_uart1: uart1grp {
294 fsl,pins = <
295 MX8MM_IOMUXC_SAI2_RXC_
296 MX8MM_IOMUXC_SAI2_RXFS
297 MX8MM_IOMUXC_SAI2_RXD0
298 MX8MM_IOMUXC_SAI2_TXFS
299 >;
300 };
301
302 pinctrl_uart2: uart2grp {
303 fsl,pins = <
304 MX8MM_IOMUXC_SAI3_TXFS
305 MX8MM_IOMUXC_SAI3_TXC_
306 MX8MM_IOMUXC_SAI3_RXD_
307 MX8MM_IOMUXC_SAI3_RXC_
308 >;
309 };
310
311 pinctrl_usb_eth2: usbeth2grp {
312 fsl,pins = <
313 MX8MM_IOMUXC_NAND_CE1_
314 >;
315 };
316
317 pinctrl_usdhc2: usdhc2grp {
318 fsl,pins = <
319 MX8MM_IOMUXC_SD2_CLK_U
320 MX8MM_IOMUXC_SD2_CMD_U
321 MX8MM_IOMUXC_SD2_DATA0
322 MX8MM_IOMUXC_SD2_DATA1
323 MX8MM_IOMUXC_SD2_DATA2
324 MX8MM_IOMUXC_SD2_DATA3
325 MX8MM_IOMUXC_SD2_CD_B_
326 MX8MM_IOMUXC_GPIO1_IO0
327 >;
328 };
329
330 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
331 fsl,pins = <
332 MX8MM_IOMUXC_SD2_CLK_U
333 MX8MM_IOMUXC_SD2_CMD_U
334 MX8MM_IOMUXC_SD2_DATA0
335 MX8MM_IOMUXC_SD2_DATA1
336 MX8MM_IOMUXC_SD2_DATA2
337 MX8MM_IOMUXC_SD2_DATA3
338 MX8MM_IOMUXC_SD2_CD_B_
339 MX8MM_IOMUXC_GPIO1_IO0
340 >;
341 };
342
343 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
344 fsl,pins = <
345 MX8MM_IOMUXC_SD2_CLK_U
346 MX8MM_IOMUXC_SD2_CMD_U
347 MX8MM_IOMUXC_SD2_DATA0
348 MX8MM_IOMUXC_SD2_DATA1
349 MX8MM_IOMUXC_SD2_DATA2
350 MX8MM_IOMUXC_SD2_DATA3
351 MX8MM_IOMUXC_SD2_CD_B_
352 MX8MM_IOMUXC_GPIO1_IO0
353 >;
354 };
355 };
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