1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6 #include "imx8mm.dtsi"
7
8 / {
9 model = "Kontron SL i.MX8MM (N801X SOM
10 compatible = "kontron,imx8mm-sl", "fsl
11
12 memory@40000000 {
13 device_type = "memory";
14 /*
15 * There are multiple SoM flav
16 * The smallest is 1GB. For la
17 * update the reg property.
18 */
19 reg = <0x0 0x40000000 0 0x8000
20 };
21
22 chosen {
23 stdout-path = &uart3;
24 };
25 };
26
27 &A53_0 {
28 cpu-supply = <®_vdd_arm>;
29 };
30
31 &A53_1 {
32 cpu-supply = <®_vdd_arm>;
33 };
34
35 &A53_2 {
36 cpu-supply = <®_vdd_arm>;
37 };
38
39 &A53_3 {
40 cpu-supply = <®_vdd_arm>;
41 };
42
43 &ddrc {
44 operating-points-v2 = <&ddrc_opp_table
45
46 ddrc_opp_table: opp-table {
47 compatible = "operating-points
48
49 opp-100000000 {
50 opp-hz = /bits/ 64 <10
51 };
52
53 opp-750000000 {
54 opp-hz = /bits/ 64 <75
55 };
56 };
57 };
58
59 &ecspi1 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_ecspi1>;
62 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
63 status = "okay";
64
65 flash@0 {
66 compatible = "mxicy,mx25r1635f
67 spi-max-frequency = <80000000>
68 reg = <0>;
69
70 partitions {
71 compatible = "fixed-pa
72 #address-cells = <1>;
73 #size-cells = <1>;
74
75 partition@0 {
76 label = "u-boo
77 reg = <0x0 0x1
78 };
79
80 partition@1e0000 {
81 label = "env";
82 reg = <0x1e000
83 };
84
85 partition@1f0000 {
86 label = "env_r
87 reg = <0x1f000
88 };
89 };
90 };
91 };
92
93 &i2c1 {
94 clock-frequency = <400000>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_i2c1>;
97 status = "okay";
98
99 pca9450: pmic@25 {
100 compatible = "nxp,pca9450a";
101 reg = <0x25>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_pmic>;
104 interrupt-parent = <&gpio1>;
105 interrupts = <0 IRQ_TYPE_LEVEL
106
107 regulators {
108 reg_vdd_soc: BUCK1 {
109 regulator-name
110 regulator-min-
111 regulator-max-
112 regulator-boot
113 regulator-alwa
114 regulator-ramp
115 nxp,dvs-run-vo
116 nxp,dvs-standb
117 };
118
119 reg_vdd_arm: BUCK2 {
120 regulator-name
121 regulator-min-
122 regulator-max-
123 regulator-boot
124 regulator-alwa
125 regulator-ramp
126 nxp,dvs-run-vo
127 nxp,dvs-standb
128 };
129
130 reg_vdd_dram: BUCK3 {
131 regulator-name
132 regulator-min-
133 regulator-max-
134 regulator-boot
135 regulator-alwa
136 };
137
138 reg_vdd_3v3: BUCK4 {
139 regulator-name
140 regulator-min-
141 regulator-max-
142 regulator-boot
143 regulator-alwa
144 };
145
146 reg_vdd_1v8: BUCK5 {
147 regulator-name
148 regulator-min-
149 regulator-max-
150 regulator-boot
151 regulator-alwa
152 };
153
154 reg_nvcc_dram: BUCK6 {
155 regulator-name
156 regulator-min-
157 regulator-max-
158 regulator-boot
159 regulator-alwa
160 };
161
162 reg_nvcc_snvs: LDO1 {
163 regulator-name
164 regulator-min-
165 regulator-max-
166 regulator-boot
167 regulator-alwa
168 };
169
170 reg_vdd_snvs: LDO2 {
171 regulator-name
172 regulator-min-
173 regulator-max-
174 regulator-boot
175 regulator-alwa
176 };
177
178 reg_vdda: LDO3 {
179 regulator-name
180 regulator-min-
181 regulator-max-
182 regulator-boot
183 regulator-alwa
184 };
185
186 reg_vdd_phy: LDO4 {
187 regulator-name
188 regulator-min-
189 regulator-max-
190 regulator-boot
191 regulator-alwa
192 };
193
194 reg_nvcc_sd: LDO5 {
195 regulator-name
196 regulator-min-
197 regulator-max-
198 };
199 };
200 };
201 };
202
203 &uart3 { /* console */
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_uart3>;
206 status = "okay";
207 };
208
209 &usdhc1 {
210 pinctrl-names = "default", "state_100m
211 pinctrl-0 = <&pinctrl_usdhc1>;
212 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
213 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
214 vmmc-supply = <®_vdd_3v3>;
215 vqmmc-supply = <®_vdd_1v8>;
216 bus-width = <8>;
217 non-removable;
218 status = "okay";
219 };
220
221 &wdog1 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_wdog>;
224 fsl,ext-reset-output;
225 status = "okay";
226 };
227
228 &iomuxc {
229 pinctrl_ecspi1: ecspi1grp {
230 fsl,pins = <
231 MX8MM_IOMUXC_ECSPI1_MI
232 MX8MM_IOMUXC_ECSPI1_MO
233 MX8MM_IOMUXC_ECSPI1_SC
234 MX8MM_IOMUXC_ECSPI1_SS
235 >;
236 };
237
238 pinctrl_i2c1: i2c1grp {
239 fsl,pins = <
240 MX8MM_IOMUXC_I2C1_SCL_
241 MX8MM_IOMUXC_I2C1_SDA_
242 >;
243 };
244
245 pinctrl_pmic: pmicgrp {
246 fsl,pins = <
247 MX8MM_IOMUXC_GPIO1_IO0
248 >;
249 };
250
251 pinctrl_uart3: uart3grp {
252 fsl,pins = <
253 MX8MM_IOMUXC_UART3_RXD
254 MX8MM_IOMUXC_UART3_TXD
255 >;
256 };
257
258 pinctrl_usdhc1: usdhc1grp {
259 fsl,pins = <
260 MX8MM_IOMUXC_SD1_CLK_U
261 MX8MM_IOMUXC_SD1_CMD_U
262 MX8MM_IOMUXC_SD1_DATA0
263 MX8MM_IOMUXC_SD1_DATA1
264 MX8MM_IOMUXC_SD1_DATA2
265 MX8MM_IOMUXC_SD1_DATA3
266 MX8MM_IOMUXC_SD1_DATA4
267 MX8MM_IOMUXC_SD1_DATA5
268 MX8MM_IOMUXC_SD1_DATA6
269 MX8MM_IOMUXC_SD1_DATA7
270 MX8MM_IOMUXC_SD1_RESET
271 MX8MM_IOMUXC_SD1_STROB
272 >;
273 };
274
275 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
276 fsl,pins = <
277 MX8MM_IOMUXC_SD1_CLK_U
278 MX8MM_IOMUXC_SD1_CMD_U
279 MX8MM_IOMUXC_SD1_DATA0
280 MX8MM_IOMUXC_SD1_DATA1
281 MX8MM_IOMUXC_SD1_DATA2
282 MX8MM_IOMUXC_SD1_DATA3
283 MX8MM_IOMUXC_SD1_DATA4
284 MX8MM_IOMUXC_SD1_DATA5
285 MX8MM_IOMUXC_SD1_DATA6
286 MX8MM_IOMUXC_SD1_DATA7
287 MX8MM_IOMUXC_SD1_RESET
288 MX8MM_IOMUXC_SD1_STROB
289 >;
290 };
291
292 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
293 fsl,pins = <
294 MX8MM_IOMUXC_SD1_CLK_U
295 MX8MM_IOMUXC_SD1_CMD_U
296 MX8MM_IOMUXC_SD1_DATA0
297 MX8MM_IOMUXC_SD1_DATA1
298 MX8MM_IOMUXC_SD1_DATA2
299 MX8MM_IOMUXC_SD1_DATA3
300 MX8MM_IOMUXC_SD1_DATA4
301 MX8MM_IOMUXC_SD1_DATA5
302 MX8MM_IOMUXC_SD1_DATA6
303 MX8MM_IOMUXC_SD1_DATA7
304 MX8MM_IOMUXC_SD1_RESET
305 MX8MM_IOMUXC_SD1_STROB
306 >;
307 };
308
309 pinctrl_wdog: wdoggrp {
310 fsl,pins = <
311 MX8MM_IOMUXC_GPIO1_IO0
312 >;
313 };
314 };
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