1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree file for Boundary Devices i.MX8
4 * Adrien Grassein <adrien.grassein@gmail.com.c
5 */
6 /dts-v1/;
7 #include "imx8mm.dtsi"
8
9 / {
10 model = "Boundary Devices i.MX8MMini N
11 compatible = "boundary,imx8mm-nitrogen
12
13 reg_vref_1v8: regulator-vref-1v8 {
14 compatible = "regulator-fixed"
15 regulator-name = "vref-1v8";
16 regulator-min-microvolt = <180
17 regulator-max-microvolt = <180
18 };
19
20 reg_vref_3v3: regulator-vref-3v3 {
21 compatible = "regulator-fixed"
22 regulator-name = "vref-3v3";
23 regulator-min-microvolt = <330
24 regulator-max-microvolt = <330
25 };
26
27 reg_wlan_vmmc: regulator-wlan-vmmc {
28 compatible = "regulator-fixed"
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_wlan
31 regulator-name = "reg_wlan_vmm
32 regulator-min-microvolt = <330
33 regulator-max-microvolt = <330
34 gpio = <&gpio3 20 GPIO_ACTIVE_
35 enable-active-high;
36 };
37
38 sound-wm8960 {
39 audio-cpu = <&sai1>;
40 audio-codec = <&wm8960>;
41 audio-routing =
42 "Headphone Jack", "HP_
43 "Headphone Jack", "HP_
44 "Ext Spk", "SPK_LP",
45 "Ext Spk", "SPK_LN",
46 "Ext Spk", "SPK_RP",
47 "Ext Spk", "SPK_RN",
48 "RINPUT1", "Mic Jack",
49 "Mic Jack", "MICB";
50 compatible = "fsl,imx-audio-wm
51 /* JD2: hp detect high for hea
52 hp-det-gpios = <&gpio4 28 GPIO
53 /* Jack is not stuffed */
54 mic-det-gpios = <&gpio1 10 GPI
55 model = "wm8960-audio";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_sound_wm
58 };
59 };
60
61 &A53_0 {
62 cpu-supply = <®_buck3>;
63 };
64
65 &A53_1 {
66 cpu-supply = <®_buck3>;
67 };
68
69 &A53_2 {
70 cpu-supply = <®_buck3>;
71 };
72
73 &A53_3 {
74 cpu-supply = <®_buck3>;
75 };
76
77 /* J15 */
78 &ecspi2 {
79 assigned-clocks = <&clk IMX8MM_CLK_ECS
80 assigned-clock-parents = <&clk IMX8MM_
81 assigned-clock-rates = <40000000>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi2>;
84 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
85 status = "okay";
86 };
87
88 &fec1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_fec1>;
91 phy-mode = "rgmii-id";
92 phy-handle = <ðphy0>;
93 fsl,magic-packet;
94 status = "okay";
95
96 mdio {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 ethphy0: ethernet-phy@4 {
101 compatible = "ethernet
102 reg = <4>;
103 interrupts-extended =
104 };
105 };
106 };
107
108 &flexspi {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_flexspi>;
111 status = "okay";
112 };
113
114 &i2c1 {
115 clock-frequency = <100000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay";
119
120 pmic@8 {
121 compatible = "nxp,pf8121a";
122 reg = <0x8>;
123
124 regulators {
125 reg_ldo1: ldo1 {
126 regulator-min-
127 regulator-max-
128 regulator-boot
129 regulator-alwa
130 };
131
132 reg_ldo2: ldo2 {
133 regulator-min-
134 regulator-max-
135 regulator-boot
136 regulator-alwa
137 };
138
139 reg_ldo3: ldo3 {
140 regulator-min-
141 regulator-max-
142 regulator-boot
143 regulator-alwa
144 };
145
146 reg_ldo4: ldo4 {
147 regulator-min-
148 regulator-max-
149 regulator-boot
150 regulator-alwa
151 };
152
153 reg_buck1: buck1 {
154 regulator-min-
155 regulator-max-
156 regulator-boot
157 regulator-alwa
158 };
159
160 reg_buck2: buck2 {
161 regulator-min-
162 regulator-max-
163 regulator-boot
164 regulator-alwa
165 };
166
167 reg_buck3: buck3 {
168 regulator-min-
169 regulator-max-
170 regulator-boot
171 regulator-alwa
172 };
173
174 reg_buck4: buck4 {
175 regulator-min-
176 regulator-max-
177 regulator-boot
178 regulator-alwa
179 };
180
181 reg_buck5: buck5 {
182 regulator-min-
183 regulator-max-
184 regulator-boot
185 regulator-alwa
186 };
187
188 reg_buck6: buck6 {
189 regulator-min-
190 regulator-max-
191 regulator-boot
192 regulator-alwa
193 };
194
195 reg_buck7: buck7 {
196 regulator-min-
197 regulator-max-
198 regulator-boot
199 regulator-alwa
200 };
201
202 reg_vsnvs: vsnvs {
203 regulator-min-
204 regulator-max-
205 regulator-boot
206 };
207 };
208 };
209 };
210
211 &i2c3 {
212 clock-frequency = <100000>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c3>;
215 status = "okay";
216
217 i2c-mux@70 {
218 compatible = "nxp,pca9540";
219 reg = <0x70>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222
223 i2c@0 {
224 reg = <0>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 rtc@68 {
229 compatible = "
230 reg = <0x68>;
231 pinctrl-names
232 pinctrl-0 = <&
233 interrupts-ext
234 wakeup-source;
235 };
236 };
237 };
238 };
239
240 &i2c4 {
241 clock-frequency = <100000>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c4>;
244 status = "okay";
245
246 wm8960: codec@1a {
247 compatible = "wlf,wm8960";
248 reg = <0x1a>;
249 clocks = <&clk IMX8MM_CLK_SAI1
250 clock-names = "mclk";
251 wlf,shared-lrclk;
252 #sound-dai-cells = <0>;
253 };
254 };
255
256 &pwm1 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_pwm1>;
259 status = "okay";
260 };
261
262 &pwm2 {
263 assigned-clocks = <&clk IMX8MM_CLK_PWM
264 assigned-clock-parents = <&clk IMX8MM_
265 assigned-clock-rates = <40000000>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_pwm2>;
268 status = "okay";
269 };
270
271 &pwm3 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_pwm3>;
274 status = "okay";
275 };
276
277 &pwm4 {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_pwm4>;
280 status = "okay";
281 };
282
283 &sai1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_sai1>;
286 status = "okay";
287 };
288
289 &sai2 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_sai2>;
292 status = "okay";
293 };
294
295 /* BT */
296 &uart1 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_uart1>;
299 uart-has-rtscts;
300 status = "okay";
301 };
302
303 /* console */
304 &uart2 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_uart2>;
307 status = "okay";
308 };
309
310 /* J15 */
311 &uart3 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart3>;
314 uart-has-rtscts;
315 status = "okay";
316 };
317
318 /* J9 */
319 &uart4 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart4>;
322 status = "okay";
323 };
324
325 /* eMMC */
326 &usdhc1 {
327 bus-width = <8>;
328 sdhci-caps-mask = <0x80000000 0x0>;
329 non-removable;
330 pinctrl-names = "default", "state_100m
331 pinctrl-0 = <&pinctrl_usdhc1>;
332 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
333 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
334 vmmc-supply = <®_vref_3v3>;
335 vqmmc-supply = <®_vref_1v8>;
336 status = "okay";
337 };
338
339 /* sdcard */
340 &usdhc2 {
341 bus-width = <4>;
342 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
343 pinctrl-names = "default", "state_100m
344 pinctrl-0 = <&pinctrl_usdhc2>;
345 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
346 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
347 vqmmc-supply = <®_ldo2>;
348 status = "okay";
349 };
350
351 /* wlan */
352 &usdhc3 {
353 bus-width = <4>;
354 sdhci-caps-mask = <0x2 0x0>;
355 non-removable;
356 pinctrl-names = "default", "state_100m
357 pinctrl-0 = <&pinctrl_usdhc3>;
358 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
359 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
360 vmmc-supply = <®_wlan_vmmc>;
361 vqmmc-supply = <®_vref_1v8>;
362 status = "okay";
363 };
364
365 /* USB OTG port */
366 &usbotg1 {
367 dr_mode = "otg";
368 over-current-active-low;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_usbotg1>;
371 power-active-high;
372 status = "okay";
373 };
374
375 /* USB Host port */
376 &usbotg2 {
377 dr_mode = "host";
378 over-current-active-low;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_usbotg2>;
381 power-active-high;
382 /*
383 * FIXME: having USB2 enabled hangs th
384 *[ 1.655941] ci_hdrc ci_hdrc.1: EH
385 *[ 1.660880] ci_hdrc ci_hdrc.1: ne
386 *[ 1.681505] ci_hdrc ci_hdrc.1: US
387 *[ 1.687730] hub 2-0:1.0: USB hub
388 *[ 1.691528] hub 2-0:1.0: 1 port d
389 */
390 status = "disabled";
391 };
392
393 &wdog1 {
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_wdog>;
396 fsl,ext-reset-output;
397 status = "okay";
398 };
399
400 &iomuxc {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_hog>;
403
404 pinctrl_ecspi2: ecspi2grp {
405 fsl,pins = <
406 MX8MM_IOMUXC_ECSPI2_SS
407 MX8MM_IOMUXC_ECSPI2_MI
408 MX8MM_IOMUXC_ECSPI2_SC
409 MX8MM_IOMUXC_ECSPI2_MO
410 >;
411 };
412
413 pinctrl_fec1: fec1grp {
414 fsl,pins = <
415 MX8MM_IOMUXC_ENET_MDC_
416 MX8MM_IOMUXC_ENET_MDIO
417 MX8MM_IOMUXC_ENET_TD3_
418 MX8MM_IOMUXC_ENET_TD2_
419 MX8MM_IOMUXC_ENET_TD1_
420 MX8MM_IOMUXC_ENET_TD0_
421 MX8MM_IOMUXC_ENET_RD3_
422 MX8MM_IOMUXC_ENET_RD2_
423 MX8MM_IOMUXC_ENET_RD1_
424 MX8MM_IOMUXC_ENET_RD0_
425 MX8MM_IOMUXC_ENET_TXC_
426 MX8MM_IOMUXC_ENET_RXC_
427 MX8MM_IOMUXC_ENET_RX_C
428 MX8MM_IOMUXC_ENET_TX_C
429 MX8MM_IOMUXC_NAND_READ
430 >;
431 };
432
433 pinctrl_flexspi: flexspigrp {
434 fsl,pins = <
435 MX8MM_IOMUXC_NAND_ALE_
436 MX8MM_IOMUXC_NAND_CE0_
437 MX8MM_IOMUXC_NAND_DATA
438 MX8MM_IOMUXC_NAND_DATA
439 MX8MM_IOMUXC_NAND_DATA
440 MX8MM_IOMUXC_NAND_DATA
441 >;
442 };
443
444 pinctrl_hog: hoggrp {
445 fsl,pins = <
446 MX8MM_IOMUXC_GPIO1_IO0
447 MX8MM_IOMUXC_GPIO1_IO0
448 >;
449 };
450
451 pinctrl_i2c1: i2c1grp {
452 fsl,pins = <
453 MX8MM_IOMUXC_I2C1_SCL_
454 MX8MM_IOMUXC_I2C1_SDA_
455 >;
456 };
457
458 pinctrl_i2c3: i2c3grp {
459 fsl,pins = <
460 MX8MM_IOMUXC_I2C3_SCL_
461 MX8MM_IOMUXC_I2C3_SDA_
462 >;
463 };
464
465 pinctrl_i2c4: i2c4grp {
466 fsl,pins = <
467 MX8MM_IOMUXC_I2C4_SCL_
468 MX8MM_IOMUXC_I2C4_SDA_
469 >;
470 };
471
472 pinctrl_i2c3a_rv4162: i2c3a-rv4162grp
473 fsl,pins = <
474 MX8MM_IOMUXC_SAI2_RXC_
475 >;
476 };
477
478 pinctrl_pwm1: pwm1grp {
479 fsl,pins = <
480 MX8MM_IOMUXC_SPDIF_EXT
481 >;
482 };
483
484 pinctrl_pwm2: pwm2grp {
485 fsl,pins = <
486 MX8MM_IOMUXC_SPDIF_RX_
487 >;
488 };
489
490 pinctrl_pwm3: pwm3grp {
491 fsl,pins = <
492 MX8MM_IOMUXC_SPDIF_TX_
493 >;
494 };
495
496 pinctrl_pwm4: pwm4grp {
497 fsl,pins = <
498 MX8MM_IOMUXC_SAI3_MCLK
499 >;
500 };
501
502 pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgr
503 fsl,pins = <
504 MX8MM_IOMUXC_SAI5_RXC_
505 >;
506 };
507
508 pinctrl_sai1: sai1grp {
509 fsl,pins = <
510 /* wm8960 */
511 MX8MM_IOMUXC_SAI1_MCLK
512 MX8MM_IOMUXC_SAI1_TXFS
513 MX8MM_IOMUXC_SAI1_TXC_
514 MX8MM_IOMUXC_SAI1_TXD0
515 MX8MM_IOMUXC_SAI1_RXD0
516 >;
517 };
518
519 pinctrl_sai2: sai2grp {
520 fsl,pins = <
521 /* Bluetooth PCM */
522 MX8MM_IOMUXC_SAI2_TXFS
523 MX8MM_IOMUXC_SAI2_TXC_
524 MX8MM_IOMUXC_SAI2_TXD0
525 MX8MM_IOMUXC_SAI2_RXD0
526 >;
527 };
528
529 pinctrl_sound_wm8960: sound-wm8960grp
530 fsl,pins = <
531 MX8MM_IOMUXC_GPIO1_IO1
532 MX8MM_IOMUXC_SAI3_RXFS
533 >;
534 };
535
536 pinctrl_uart1: uart1grp {
537 fsl,pins = <
538 MX8MM_IOMUXC_UART1_RXD
539 MX8MM_IOMUXC_UART1_TXD
540 MX8MM_IOMUXC_UART3_RXD
541 MX8MM_IOMUXC_UART3_TXD
542 >;
543 };
544
545 pinctrl_uart2: uart2grp {
546 fsl,pins = <
547 MX8MM_IOMUXC_UART2_RXD
548 MX8MM_IOMUXC_UART2_TXD
549 >;
550 };
551
552 pinctrl_uart3: uart3grp {
553 fsl,pins = <
554 MX8MM_IOMUXC_ECSPI1_SC
555 MX8MM_IOMUXC_ECSPI1_MO
556 MX8MM_IOMUXC_ECSPI1_SS
557 MX8MM_IOMUXC_ECSPI1_MI
558 >;
559 };
560
561 pinctrl_uart4: uart4grp {
562 fsl,pins = <
563 MX8MM_IOMUXC_UART4_RXD
564 MX8MM_IOMUXC_UART4_TXD
565 >;
566 };
567
568 pinctrl_usbotg1: usbotg1grp {
569 fsl,pins = <
570 MX8MM_IOMUXC_GPIO1_IO1
571 MX8MM_IOMUXC_GPIO1_IO1
572 >;
573 };
574
575 pinctrl_usbotg2: usbotg2grp {
576 fsl,pins = <
577 MX8MM_IOMUXC_GPIO1_IO1
578 MX8MM_IOMUXC_GPIO1_IO1
579 >;
580 };
581
582 pinctrl_usdhc1: usdhc1grp {
583 fsl,pins = <
584 MX8MM_IOMUXC_SD1_CLK_U
585 MX8MM_IOMUXC_SD1_CMD_U
586 MX8MM_IOMUXC_SD1_DATA0
587 MX8MM_IOMUXC_SD1_DATA1
588 MX8MM_IOMUXC_SD1_DATA2
589 MX8MM_IOMUXC_SD1_DATA3
590 MX8MM_IOMUXC_SD1_DATA4
591 MX8MM_IOMUXC_SD1_DATA5
592 MX8MM_IOMUXC_SD1_DATA6
593 MX8MM_IOMUXC_SD1_DATA7
594 MX8MM_IOMUXC_SD1_RESET
595 >;
596 };
597
598 pinctrl_usdhc1_100mhz: usdhc1-100mhz-g
599 fsl,pins = <
600 MX8MM_IOMUXC_SD1_CLK_U
601 MX8MM_IOMUXC_SD1_CMD_U
602 MX8MM_IOMUXC_SD1_DATA0
603 MX8MM_IOMUXC_SD1_DATA1
604 MX8MM_IOMUXC_SD1_DATA2
605 MX8MM_IOMUXC_SD1_DATA3
606 MX8MM_IOMUXC_SD1_DATA4
607 MX8MM_IOMUXC_SD1_DATA5
608 MX8MM_IOMUXC_SD1_DATA6
609 MX8MM_IOMUXC_SD1_DATA7
610 >;
611 };
612
613 pinctrl_usdhc1_200mhz: usdhc1-200mhz-g
614 fsl,pins = <
615 MX8MM_IOMUXC_SD1_CLK_U
616 MX8MM_IOMUXC_SD1_CMD_U
617 MX8MM_IOMUXC_SD1_DATA0
618 MX8MM_IOMUXC_SD1_DATA1
619 MX8MM_IOMUXC_SD1_DATA2
620 MX8MM_IOMUXC_SD1_DATA3
621 MX8MM_IOMUXC_SD1_DATA4
622 MX8MM_IOMUXC_SD1_DATA5
623 MX8MM_IOMUXC_SD1_DATA6
624 MX8MM_IOMUXC_SD1_DATA7
625 >;
626 };
627
628 pinctrl_usdhc2: usdhc2grp {
629 fsl,pins = <
630 MX8MM_IOMUXC_SD2_CLK_U
631 MX8MM_IOMUXC_SD2_CMD_U
632 MX8MM_IOMUXC_SD2_DATA0
633 MX8MM_IOMUXC_SD2_DATA1
634 MX8MM_IOMUXC_SD2_DATA2
635 MX8MM_IOMUXC_SD2_DATA3
636 MX8MM_IOMUXC_SD2_CD_B_
637 >;
638 };
639
640 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g
641 fsl,pins = <
642 MX8MM_IOMUXC_SD2_CLK_U
643 MX8MM_IOMUXC_SD2_CMD_U
644 MX8MM_IOMUXC_SD2_DATA0
645 MX8MM_IOMUXC_SD2_DATA1
646 MX8MM_IOMUXC_SD2_DATA2
647 MX8MM_IOMUXC_SD2_DATA3
648 >;
649 };
650
651 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g
652 fsl,pins = <
653 MX8MM_IOMUXC_SD2_CLK_U
654 MX8MM_IOMUXC_SD2_CMD_U
655 MX8MM_IOMUXC_SD2_DATA0
656 MX8MM_IOMUXC_SD2_DATA1
657 MX8MM_IOMUXC_SD2_DATA2
658 MX8MM_IOMUXC_SD2_DATA3
659 >;
660 };
661
662 pinctrl_usdhc3: usdhc3grp {
663 fsl,pins = <
664 MX8MM_IOMUXC_NAND_WE_B
665 MX8MM_IOMUXC_NAND_WP_B
666 MX8MM_IOMUXC_NAND_DATA
667 MX8MM_IOMUXC_NAND_DATA
668 MX8MM_IOMUXC_NAND_DATA
669 MX8MM_IOMUXC_NAND_DATA
670 MX8MM_IOMUXC_GPIO1_IO0
671 >;
672 };
673
674 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g
675 fsl,pins = <
676 MX8MM_IOMUXC_NAND_WE_B
677 MX8MM_IOMUXC_NAND_WP_B
678 MX8MM_IOMUXC_NAND_DATA
679 MX8MM_IOMUXC_NAND_DATA
680 MX8MM_IOMUXC_NAND_DATA
681 MX8MM_IOMUXC_NAND_DATA
682 >;
683 };
684
685 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g
686 fsl,pins = <
687 MX8MM_IOMUXC_NAND_WE_B
688 MX8MM_IOMUXC_NAND_WP_B
689 MX8MM_IOMUXC_NAND_DATA
690 MX8MM_IOMUXC_NAND_DATA
691 MX8MM_IOMUXC_NAND_DATA
692 MX8MM_IOMUXC_NAND_DATA
693 >;
694 };
695
696 pinctrl_wdog: wdoggrp {
697 fsl,pins = <
698 MX8MM_IOMUXC_GPIO1_IO0
699 >;
700 };
701 };
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