1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for Boundary Devices i.MX8 3 * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board.
4 * Adrien Grassein <adrien.grassein@gmail.com.c 4 * Adrien Grassein <adrien.grassein@gmail.com.com>
5 */ 5 */
6 /dts-v1/; 6 /dts-v1/;
7 #include "imx8mm.dtsi" 7 #include "imx8mm.dtsi"
8 8
9 / { 9 / {
10 model = "Boundary Devices i.MX8MMini N 10 model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
11 compatible = "boundary,imx8mm-nitrogen 11 compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
12 12
13 reg_vref_1v8: regulator-vref-1v8 { 13 reg_vref_1v8: regulator-vref-1v8 {
14 compatible = "regulator-fixed" 14 compatible = "regulator-fixed";
15 regulator-name = "vref-1v8"; 15 regulator-name = "vref-1v8";
16 regulator-min-microvolt = <180 16 regulator-min-microvolt = <1800000>;
17 regulator-max-microvolt = <180 17 regulator-max-microvolt = <1800000>;
18 }; 18 };
19 19
20 reg_vref_3v3: regulator-vref-3v3 { 20 reg_vref_3v3: regulator-vref-3v3 {
21 compatible = "regulator-fixed" 21 compatible = "regulator-fixed";
22 regulator-name = "vref-3v3"; 22 regulator-name = "vref-3v3";
23 regulator-min-microvolt = <330 23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <330 24 regulator-max-microvolt = <3300000>;
25 }; 25 };
26 26
27 reg_wlan_vmmc: regulator-wlan-vmmc { 27 reg_wlan_vmmc: regulator-wlan-vmmc {
28 compatible = "regulator-fixed" 28 compatible = "regulator-fixed";
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_wlan 30 pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
31 regulator-name = "reg_wlan_vmm 31 regulator-name = "reg_wlan_vmmc";
32 regulator-min-microvolt = <330 32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <330 33 regulator-max-microvolt = <3300000>;
34 gpio = <&gpio3 20 GPIO_ACTIVE_ 34 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
35 enable-active-high; 35 enable-active-high;
36 }; 36 };
37 37
38 sound-wm8960 { 38 sound-wm8960 {
39 audio-cpu = <&sai1>; 39 audio-cpu = <&sai1>;
40 audio-codec = <&wm8960>; 40 audio-codec = <&wm8960>;
41 audio-routing = 41 audio-routing =
42 "Headphone Jack", "HP_ 42 "Headphone Jack", "HP_L",
43 "Headphone Jack", "HP_ 43 "Headphone Jack", "HP_R",
44 "Ext Spk", "SPK_LP", 44 "Ext Spk", "SPK_LP",
45 "Ext Spk", "SPK_LN", 45 "Ext Spk", "SPK_LN",
46 "Ext Spk", "SPK_RP", 46 "Ext Spk", "SPK_RP",
47 "Ext Spk", "SPK_RN", 47 "Ext Spk", "SPK_RN",
48 "RINPUT1", "Mic Jack", 48 "RINPUT1", "Mic Jack",
49 "Mic Jack", "MICB"; 49 "Mic Jack", "MICB";
50 compatible = "fsl,imx-audio-wm 50 compatible = "fsl,imx-audio-wm8960";
51 /* JD2: hp detect high for hea 51 /* JD2: hp detect high for headphone*/
52 hp-det-gpios = <&gpio4 28 GPIO 52 hp-det-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
53 /* Jack is not stuffed */ 53 /* Jack is not stuffed */
54 mic-det-gpios = <&gpio1 10 GPI 54 mic-det-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
55 model = "wm8960-audio"; 55 model = "wm8960-audio";
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_sound_wm 57 pinctrl-0 = <&pinctrl_sound_wm8960>;
58 }; 58 };
59 }; 59 };
60 60
61 &A53_0 { 61 &A53_0 {
62 cpu-supply = <®_buck3>; 62 cpu-supply = <®_buck3>;
63 }; 63 };
64 64
65 &A53_1 { 65 &A53_1 {
66 cpu-supply = <®_buck3>; 66 cpu-supply = <®_buck3>;
67 }; 67 };
68 68
69 &A53_2 { 69 &A53_2 {
70 cpu-supply = <®_buck3>; 70 cpu-supply = <®_buck3>;
71 }; 71 };
72 72
73 &A53_3 { 73 &A53_3 {
74 cpu-supply = <®_buck3>; 74 cpu-supply = <®_buck3>;
75 }; 75 };
76 76
77 /* J15 */ 77 /* J15 */
78 &ecspi2 { 78 &ecspi2 {
79 assigned-clocks = <&clk IMX8MM_CLK_ECS 79 assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
80 assigned-clock-parents = <&clk IMX8MM_ 80 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
81 assigned-clock-rates = <40000000>; 81 assigned-clock-rates = <40000000>;
82 pinctrl-names = "default"; 82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi2>; 83 pinctrl-0 = <&pinctrl_ecspi2>;
84 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 84 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
85 status = "okay"; 85 status = "okay";
86 }; 86 };
87 87
88 &fec1 { 88 &fec1 {
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_fec1>; 90 pinctrl-0 = <&pinctrl_fec1>;
91 phy-mode = "rgmii-id"; 91 phy-mode = "rgmii-id";
92 phy-handle = <ðphy0>; 92 phy-handle = <ðphy0>;
93 fsl,magic-packet; 93 fsl,magic-packet;
94 status = "okay"; 94 status = "okay";
95 95
96 mdio { 96 mdio {
97 #address-cells = <1>; 97 #address-cells = <1>;
98 #size-cells = <0>; 98 #size-cells = <0>;
99 99
100 ethphy0: ethernet-phy@4 { 100 ethphy0: ethernet-phy@4 {
101 compatible = "ethernet 101 compatible = "ethernet-phy-ieee802.3-c22";
102 reg = <4>; 102 reg = <4>;
103 interrupts-extended = 103 interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>;
104 }; 104 };
105 }; 105 };
106 }; 106 };
107 107
108 &flexspi { 108 &flexspi {
109 pinctrl-names = "default"; 109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_flexspi>; 110 pinctrl-0 = <&pinctrl_flexspi>;
111 status = "okay"; 111 status = "okay";
112 }; 112 };
113 113
114 &i2c1 { 114 &i2c1 {
115 clock-frequency = <100000>; 115 clock-frequency = <100000>;
116 pinctrl-names = "default"; 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>; 117 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay"; 118 status = "okay";
119 119
120 pmic@8 { 120 pmic@8 {
121 compatible = "nxp,pf8121a"; 121 compatible = "nxp,pf8121a";
122 reg = <0x8>; 122 reg = <0x8>;
123 123
124 regulators { 124 regulators {
125 reg_ldo1: ldo1 { 125 reg_ldo1: ldo1 {
126 regulator-min- 126 regulator-min-microvolt = <1500000>;
127 regulator-max- 127 regulator-max-microvolt = <5000000>;
128 regulator-boot 128 regulator-boot-on;
129 regulator-alwa 129 regulator-always-on;
130 }; 130 };
131 131
132 reg_ldo2: ldo2 { 132 reg_ldo2: ldo2 {
133 regulator-min- 133 regulator-min-microvolt = <1500000>;
134 regulator-max- 134 regulator-max-microvolt = <5000000>;
135 regulator-boot 135 regulator-boot-on;
136 regulator-alwa 136 regulator-always-on;
137 }; 137 };
138 138
139 reg_ldo3: ldo3 { 139 reg_ldo3: ldo3 {
140 regulator-min- 140 regulator-min-microvolt = <1500000>;
141 regulator-max- 141 regulator-max-microvolt = <5000000>;
142 regulator-boot 142 regulator-boot-on;
143 regulator-alwa 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_ldo4: ldo4 { 146 reg_ldo4: ldo4 {
147 regulator-min- 147 regulator-min-microvolt = <1500000>;
148 regulator-max- 148 regulator-max-microvolt = <5000000>;
149 regulator-boot 149 regulator-boot-on;
150 regulator-alwa 150 regulator-always-on;
151 }; 151 };
152 152
153 reg_buck1: buck1 { 153 reg_buck1: buck1 {
154 regulator-min- 154 regulator-min-microvolt = <400000>;
155 regulator-max- 155 regulator-max-microvolt = <1800000>;
156 regulator-boot 156 regulator-boot-on;
157 regulator-alwa 157 regulator-always-on;
158 }; 158 };
159 159
160 reg_buck2: buck2 { 160 reg_buck2: buck2 {
161 regulator-min- 161 regulator-min-microvolt = <400000>;
162 regulator-max- 162 regulator-max-microvolt = <1800000>;
163 regulator-boot 163 regulator-boot-on;
164 regulator-alwa 164 regulator-always-on;
165 }; 165 };
166 166
167 reg_buck3: buck3 { 167 reg_buck3: buck3 {
168 regulator-min- 168 regulator-min-microvolt = <400000>;
169 regulator-max- 169 regulator-max-microvolt = <1800000>;
170 regulator-boot 170 regulator-boot-on;
171 regulator-alwa 171 regulator-always-on;
172 }; 172 };
173 173
174 reg_buck4: buck4 { 174 reg_buck4: buck4 {
175 regulator-min- 175 regulator-min-microvolt = <400000>;
176 regulator-max- 176 regulator-max-microvolt = <1800000>;
177 regulator-boot 177 regulator-boot-on;
178 regulator-alwa 178 regulator-always-on;
179 }; 179 };
180 180
181 reg_buck5: buck5 { 181 reg_buck5: buck5 {
182 regulator-min- 182 regulator-min-microvolt = <400000>;
183 regulator-max- 183 regulator-max-microvolt = <1800000>;
184 regulator-boot 184 regulator-boot-on;
185 regulator-alwa 185 regulator-always-on;
186 }; 186 };
187 187
188 reg_buck6: buck6 { 188 reg_buck6: buck6 {
189 regulator-min- 189 regulator-min-microvolt = <400000>;
190 regulator-max- 190 regulator-max-microvolt = <1800000>;
191 regulator-boot 191 regulator-boot-on;
192 regulator-alwa 192 regulator-always-on;
193 }; 193 };
194 194
195 reg_buck7: buck7 { 195 reg_buck7: buck7 {
196 regulator-min- 196 regulator-min-microvolt = <3300000>;
197 regulator-max- 197 regulator-max-microvolt = <3300000>;
198 regulator-boot 198 regulator-boot-on;
199 regulator-alwa 199 regulator-always-on;
200 }; 200 };
201 201
202 reg_vsnvs: vsnvs { 202 reg_vsnvs: vsnvs {
203 regulator-min- 203 regulator-min-microvolt = <1800000>;
204 regulator-max- 204 regulator-max-microvolt = <3300000>;
205 regulator-boot 205 regulator-boot-on;
206 }; 206 };
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 210
211 &i2c3 { 211 &i2c3 {
212 clock-frequency = <100000>; 212 clock-frequency = <100000>;
213 pinctrl-names = "default"; 213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c3>; 214 pinctrl-0 = <&pinctrl_i2c3>;
215 status = "okay"; 215 status = "okay";
216 216
217 i2c-mux@70 { 217 i2c-mux@70 {
218 compatible = "nxp,pca9540"; 218 compatible = "nxp,pca9540";
219 reg = <0x70>; 219 reg = <0x70>;
220 #address-cells = <1>; 220 #address-cells = <1>;
221 #size-cells = <0>; 221 #size-cells = <0>;
222 222
223 i2c@0 { !! 223 i2c3@0 {
224 reg = <0>; 224 reg = <0>;
225 #address-cells = <1>; 225 #address-cells = <1>;
226 #size-cells = <0>; 226 #size-cells = <0>;
227 227
228 rtc@68 { 228 rtc@68 {
229 compatible = " 229 compatible = "microcrystal,rv4162";
230 reg = <0x68>; 230 reg = <0x68>;
231 pinctrl-names 231 pinctrl-names = "default";
232 pinctrl-0 = <& 232 pinctrl-0 = <&pinctrl_i2c3a_rv4162>;
233 interrupts-ext 233 interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>;
234 wakeup-source; 234 wakeup-source;
235 }; 235 };
236 }; 236 };
237 }; 237 };
238 }; 238 };
239 239
240 &i2c4 { 240 &i2c4 {
241 clock-frequency = <100000>; 241 clock-frequency = <100000>;
242 pinctrl-names = "default"; 242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c4>; 243 pinctrl-0 = <&pinctrl_i2c4>;
244 status = "okay"; 244 status = "okay";
245 245
246 wm8960: codec@1a { 246 wm8960: codec@1a {
247 compatible = "wlf,wm8960"; 247 compatible = "wlf,wm8960";
248 reg = <0x1a>; 248 reg = <0x1a>;
249 clocks = <&clk IMX8MM_CLK_SAI1 249 clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
250 clock-names = "mclk"; 250 clock-names = "mclk";
251 wlf,shared-lrclk; 251 wlf,shared-lrclk;
252 #sound-dai-cells = <0>; 252 #sound-dai-cells = <0>;
253 }; 253 };
254 }; 254 };
255 255
256 &pwm1 { 256 &pwm1 {
257 pinctrl-names = "default"; 257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_pwm1>; 258 pinctrl-0 = <&pinctrl_pwm1>;
259 status = "okay"; 259 status = "okay";
260 }; 260 };
261 261
262 &pwm2 { 262 &pwm2 {
263 assigned-clocks = <&clk IMX8MM_CLK_PWM 263 assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
264 assigned-clock-parents = <&clk IMX8MM_ 264 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
265 assigned-clock-rates = <40000000>; 265 assigned-clock-rates = <40000000>;
266 pinctrl-names = "default"; 266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_pwm2>; 267 pinctrl-0 = <&pinctrl_pwm2>;
268 status = "okay"; 268 status = "okay";
269 }; 269 };
270 270
271 &pwm3 { 271 &pwm3 {
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_pwm3>; 273 pinctrl-0 = <&pinctrl_pwm3>;
274 status = "okay"; 274 status = "okay";
275 }; 275 };
276 276
277 &pwm4 { 277 &pwm4 {
278 pinctrl-names = "default"; 278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_pwm4>; 279 pinctrl-0 = <&pinctrl_pwm4>;
280 status = "okay"; 280 status = "okay";
281 }; 281 };
282 282
283 &sai1 { 283 &sai1 {
284 pinctrl-names = "default"; 284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_sai1>; 285 pinctrl-0 = <&pinctrl_sai1>;
286 status = "okay"; 286 status = "okay";
287 }; 287 };
288 288
289 &sai2 { 289 &sai2 {
290 pinctrl-names = "default"; 290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_sai2>; 291 pinctrl-0 = <&pinctrl_sai2>;
292 status = "okay"; 292 status = "okay";
293 }; 293 };
294 294
295 /* BT */ 295 /* BT */
296 &uart1 { 296 &uart1 {
297 pinctrl-names = "default"; 297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_uart1>; 298 pinctrl-0 = <&pinctrl_uart1>;
299 uart-has-rtscts; 299 uart-has-rtscts;
300 status = "okay"; 300 status = "okay";
301 }; 301 };
302 302
303 /* console */ 303 /* console */
304 &uart2 { 304 &uart2 {
305 pinctrl-names = "default"; 305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_uart2>; 306 pinctrl-0 = <&pinctrl_uart2>;
307 status = "okay"; 307 status = "okay";
308 }; 308 };
309 309
310 /* J15 */ 310 /* J15 */
311 &uart3 { 311 &uart3 {
312 pinctrl-names = "default"; 312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart3>; 313 pinctrl-0 = <&pinctrl_uart3>;
314 uart-has-rtscts; 314 uart-has-rtscts;
315 status = "okay"; 315 status = "okay";
316 }; 316 };
317 317
318 /* J9 */ 318 /* J9 */
319 &uart4 { 319 &uart4 {
320 pinctrl-names = "default"; 320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart4>; 321 pinctrl-0 = <&pinctrl_uart4>;
322 status = "okay"; 322 status = "okay";
323 }; 323 };
324 324
325 /* eMMC */ 325 /* eMMC */
326 &usdhc1 { 326 &usdhc1 {
327 bus-width = <8>; 327 bus-width = <8>;
328 sdhci-caps-mask = <0x80000000 0x0>; 328 sdhci-caps-mask = <0x80000000 0x0>;
329 non-removable; 329 non-removable;
330 pinctrl-names = "default", "state_100m 330 pinctrl-names = "default", "state_100mhz", "state_200mhz";
331 pinctrl-0 = <&pinctrl_usdhc1>; 331 pinctrl-0 = <&pinctrl_usdhc1>;
332 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 332 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
333 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 333 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
334 vmmc-supply = <®_vref_3v3>; 334 vmmc-supply = <®_vref_3v3>;
335 vqmmc-supply = <®_vref_1v8>; 335 vqmmc-supply = <®_vref_1v8>;
336 status = "okay"; 336 status = "okay";
337 }; 337 };
338 338
339 /* sdcard */ 339 /* sdcard */
340 &usdhc2 { 340 &usdhc2 {
341 bus-width = <4>; 341 bus-width = <4>;
342 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 342 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
343 pinctrl-names = "default", "state_100m 343 pinctrl-names = "default", "state_100mhz", "state_200mhz";
344 pinctrl-0 = <&pinctrl_usdhc2>; 344 pinctrl-0 = <&pinctrl_usdhc2>;
345 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 345 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
346 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 346 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
347 vqmmc-supply = <®_ldo2>; 347 vqmmc-supply = <®_ldo2>;
348 status = "okay"; 348 status = "okay";
349 }; 349 };
350 350
351 /* wlan */ 351 /* wlan */
352 &usdhc3 { 352 &usdhc3 {
353 bus-width = <4>; 353 bus-width = <4>;
354 sdhci-caps-mask = <0x2 0x0>; 354 sdhci-caps-mask = <0x2 0x0>;
355 non-removable; 355 non-removable;
356 pinctrl-names = "default", "state_100m 356 pinctrl-names = "default", "state_100mhz", "state_200mhz";
357 pinctrl-0 = <&pinctrl_usdhc3>; 357 pinctrl-0 = <&pinctrl_usdhc3>;
358 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 358 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
359 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 359 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
360 vmmc-supply = <®_wlan_vmmc>; 360 vmmc-supply = <®_wlan_vmmc>;
361 vqmmc-supply = <®_vref_1v8>; 361 vqmmc-supply = <®_vref_1v8>;
362 status = "okay"; 362 status = "okay";
363 }; 363 };
364 364
365 /* USB OTG port */ 365 /* USB OTG port */
366 &usbotg1 { 366 &usbotg1 {
367 dr_mode = "otg"; 367 dr_mode = "otg";
368 over-current-active-low; 368 over-current-active-low;
369 pinctrl-names = "default"; 369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_usbotg1>; 370 pinctrl-0 = <&pinctrl_usbotg1>;
371 power-active-high; 371 power-active-high;
372 status = "okay"; 372 status = "okay";
373 }; 373 };
374 374
375 /* USB Host port */ 375 /* USB Host port */
376 &usbotg2 { 376 &usbotg2 {
377 dr_mode = "host"; 377 dr_mode = "host";
378 over-current-active-low; 378 over-current-active-low;
379 pinctrl-names = "default"; 379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_usbotg2>; 380 pinctrl-0 = <&pinctrl_usbotg2>;
381 power-active-high; 381 power-active-high;
382 /* 382 /*
383 * FIXME: having USB2 enabled hangs th 383 * FIXME: having USB2 enabled hangs the boot just after:
384 *[ 1.655941] ci_hdrc ci_hdrc.1: EH 384 *[ 1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller
385 *[ 1.660880] ci_hdrc ci_hdrc.1: ne 385 *[ 1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2
386 *[ 1.681505] ci_hdrc ci_hdrc.1: US 386 *[ 1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
387 *[ 1.687730] hub 2-0:1.0: USB hub 387 *[ 1.687730] hub 2-0:1.0: USB hub found
388 *[ 1.691528] hub 2-0:1.0: 1 port d 388 *[ 1.691528] hub 2-0:1.0: 1 port detected
389 */ 389 */
390 status = "disabled"; 390 status = "disabled";
391 }; 391 };
392 392
393 &wdog1 { 393 &wdog1 {
394 pinctrl-names = "default"; 394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_wdog>; 395 pinctrl-0 = <&pinctrl_wdog>;
396 fsl,ext-reset-output; 396 fsl,ext-reset-output;
397 status = "okay"; 397 status = "okay";
398 }; 398 };
399 399
400 &iomuxc { 400 &iomuxc {
401 pinctrl-names = "default"; 401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_hog>; 402 pinctrl-0 = <&pinctrl_hog>;
403 403
404 pinctrl_ecspi2: ecspi2grp { 404 pinctrl_ecspi2: ecspi2grp {
405 fsl,pins = < 405 fsl,pins = <
406 MX8MM_IOMUXC_ECSPI2_SS 406 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
407 MX8MM_IOMUXC_ECSPI2_MI 407 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
408 MX8MM_IOMUXC_ECSPI2_SC 408 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
409 MX8MM_IOMUXC_ECSPI2_MO 409 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
410 >; 410 >;
411 }; 411 };
412 412
413 pinctrl_fec1: fec1grp { 413 pinctrl_fec1: fec1grp {
414 fsl,pins = < 414 fsl,pins = <
415 MX8MM_IOMUXC_ENET_MDC_ 415 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
416 MX8MM_IOMUXC_ENET_MDIO 416 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
417 MX8MM_IOMUXC_ENET_TD3_ 417 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
418 MX8MM_IOMUXC_ENET_TD2_ 418 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
419 MX8MM_IOMUXC_ENET_TD1_ 419 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
420 MX8MM_IOMUXC_ENET_TD0_ 420 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
421 MX8MM_IOMUXC_ENET_RD3_ 421 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
422 MX8MM_IOMUXC_ENET_RD2_ 422 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
423 MX8MM_IOMUXC_ENET_RD1_ 423 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
424 MX8MM_IOMUXC_ENET_RD0_ 424 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
425 MX8MM_IOMUXC_ENET_TXC_ 425 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
426 MX8MM_IOMUXC_ENET_RXC_ 426 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
427 MX8MM_IOMUXC_ENET_RX_C 427 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
428 MX8MM_IOMUXC_ENET_TX_C 428 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
429 MX8MM_IOMUXC_NAND_READ 429 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159
430 >; 430 >;
431 }; 431 };
432 432
433 pinctrl_flexspi: flexspigrp { 433 pinctrl_flexspi: flexspigrp {
434 fsl,pins = < 434 fsl,pins = <
435 MX8MM_IOMUXC_NAND_ALE_ 435 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
436 MX8MM_IOMUXC_NAND_CE0_ 436 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
437 MX8MM_IOMUXC_NAND_DATA 437 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
438 MX8MM_IOMUXC_NAND_DATA 438 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
439 MX8MM_IOMUXC_NAND_DATA 439 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
440 MX8MM_IOMUXC_NAND_DATA 440 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
441 >; 441 >;
442 }; 442 };
443 443
444 pinctrl_hog: hoggrp { 444 pinctrl_hog: hoggrp {
445 fsl,pins = < 445 fsl,pins = <
446 MX8MM_IOMUXC_GPIO1_IO0 446 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
447 MX8MM_IOMUXC_GPIO1_IO0 447 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09
448 >; 448 >;
449 }; 449 };
450 450
451 pinctrl_i2c1: i2c1grp { 451 pinctrl_i2c1: i2c1grp {
452 fsl,pins = < 452 fsl,pins = <
453 MX8MM_IOMUXC_I2C1_SCL_ 453 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
454 MX8MM_IOMUXC_I2C1_SDA_ 454 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
455 >; 455 >;
456 }; 456 };
457 457
458 pinctrl_i2c3: i2c3grp { 458 pinctrl_i2c3: i2c3grp {
459 fsl,pins = < 459 fsl,pins = <
460 MX8MM_IOMUXC_I2C3_SCL_ 460 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
461 MX8MM_IOMUXC_I2C3_SDA_ 461 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
462 >; 462 >;
463 }; 463 };
464 464
465 pinctrl_i2c4: i2c4grp { 465 pinctrl_i2c4: i2c4grp {
466 fsl,pins = < 466 fsl,pins = <
467 MX8MM_IOMUXC_I2C4_SCL_ 467 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
468 MX8MM_IOMUXC_I2C4_SDA_ 468 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
469 >; 469 >;
470 }; 470 };
471 471
472 pinctrl_i2c3a_rv4162: i2c3a-rv4162grp 472 pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {
473 fsl,pins = < 473 fsl,pins = <
474 MX8MM_IOMUXC_SAI2_RXC_ 474 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
475 >; 475 >;
476 }; 476 };
477 477
478 pinctrl_pwm1: pwm1grp { 478 pinctrl_pwm1: pwm1grp {
479 fsl,pins = < 479 fsl,pins = <
480 MX8MM_IOMUXC_SPDIF_EXT 480 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
481 >; 481 >;
482 }; 482 };
483 483
484 pinctrl_pwm2: pwm2grp { 484 pinctrl_pwm2: pwm2grp {
485 fsl,pins = < 485 fsl,pins = <
486 MX8MM_IOMUXC_SPDIF_RX_ 486 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
487 >; 487 >;
488 }; 488 };
489 489
490 pinctrl_pwm3: pwm3grp { 490 pinctrl_pwm3: pwm3grp {
491 fsl,pins = < 491 fsl,pins = <
492 MX8MM_IOMUXC_SPDIF_TX_ 492 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
493 >; 493 >;
494 }; 494 };
495 495
496 pinctrl_pwm4: pwm4grp { 496 pinctrl_pwm4: pwm4grp {
497 fsl,pins = < 497 fsl,pins = <
498 MX8MM_IOMUXC_SAI3_MCLK 498 MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
499 >; 499 >;
500 }; 500 };
501 501
502 pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgr 502 pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
503 fsl,pins = < 503 fsl,pins = <
504 MX8MM_IOMUXC_SAI5_RXC_ 504 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
505 >; 505 >;
506 }; 506 };
507 507
508 pinctrl_sai1: sai1grp { 508 pinctrl_sai1: sai1grp {
509 fsl,pins = < 509 fsl,pins = <
510 /* wm8960 */ 510 /* wm8960 */
511 MX8MM_IOMUXC_SAI1_MCLK 511 MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
512 MX8MM_IOMUXC_SAI1_TXFS 512 MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
513 MX8MM_IOMUXC_SAI1_TXC_ 513 MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
514 MX8MM_IOMUXC_SAI1_TXD0 514 MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
515 MX8MM_IOMUXC_SAI1_RXD0 515 MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
516 >; 516 >;
517 }; 517 };
518 518
519 pinctrl_sai2: sai2grp { 519 pinctrl_sai2: sai2grp {
520 fsl,pins = < 520 fsl,pins = <
521 /* Bluetooth PCM */ 521 /* Bluetooth PCM */
522 MX8MM_IOMUXC_SAI2_TXFS 522 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
523 MX8MM_IOMUXC_SAI2_TXC_ 523 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
524 MX8MM_IOMUXC_SAI2_TXD0 524 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
525 MX8MM_IOMUXC_SAI2_RXD0 525 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
526 >; 526 >;
527 }; 527 };
528 528
529 pinctrl_sound_wm8960: sound-wm8960grp 529 pinctrl_sound_wm8960: sound-wm8960grp {
530 fsl,pins = < 530 fsl,pins = <
531 MX8MM_IOMUXC_GPIO1_IO1 531 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x80
532 MX8MM_IOMUXC_SAI3_RXFS 532 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x80
533 >; 533 >;
534 }; 534 };
535 535
536 pinctrl_uart1: uart1grp { 536 pinctrl_uart1: uart1grp {
537 fsl,pins = < 537 fsl,pins = <
538 MX8MM_IOMUXC_UART1_RXD 538 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
539 MX8MM_IOMUXC_UART1_TXD 539 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
540 MX8MM_IOMUXC_UART3_RXD 540 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
541 MX8MM_IOMUXC_UART3_TXD 541 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
542 >; 542 >;
543 }; 543 };
544 544
545 pinctrl_uart2: uart2grp { 545 pinctrl_uart2: uart2grp {
546 fsl,pins = < 546 fsl,pins = <
547 MX8MM_IOMUXC_UART2_RXD 547 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
548 MX8MM_IOMUXC_UART2_TXD 548 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
549 >; 549 >;
550 }; 550 };
551 551
552 pinctrl_uart3: uart3grp { 552 pinctrl_uart3: uart3grp {
553 fsl,pins = < 553 fsl,pins = <
554 MX8MM_IOMUXC_ECSPI1_SC 554 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
555 MX8MM_IOMUXC_ECSPI1_MO 555 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
556 MX8MM_IOMUXC_ECSPI1_SS 556 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
557 MX8MM_IOMUXC_ECSPI1_MI 557 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
558 >; 558 >;
559 }; 559 };
560 560
561 pinctrl_uart4: uart4grp { 561 pinctrl_uart4: uart4grp {
562 fsl,pins = < 562 fsl,pins = <
563 MX8MM_IOMUXC_UART4_RXD 563 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
564 MX8MM_IOMUXC_UART4_TXD 564 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
565 >; 565 >;
566 }; 566 };
567 567
568 pinctrl_usbotg1: usbotg1grp { 568 pinctrl_usbotg1: usbotg1grp {
569 fsl,pins = < 569 fsl,pins = <
570 MX8MM_IOMUXC_GPIO1_IO1 570 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16
571 MX8MM_IOMUXC_GPIO1_IO1 571 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156
572 >; 572 >;
573 }; 573 };
574 574
575 pinctrl_usbotg2: usbotg2grp { 575 pinctrl_usbotg2: usbotg2grp {
576 fsl,pins = < 576 fsl,pins = <
577 MX8MM_IOMUXC_GPIO1_IO1 577 MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
578 MX8MM_IOMUXC_GPIO1_IO1 578 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x15
579 >; 579 >;
580 }; 580 };
581 581
582 pinctrl_usdhc1: usdhc1grp { 582 pinctrl_usdhc1: usdhc1grp {
583 fsl,pins = < 583 fsl,pins = <
584 MX8MM_IOMUXC_SD1_CLK_U 584 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
585 MX8MM_IOMUXC_SD1_CMD_U 585 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
586 MX8MM_IOMUXC_SD1_DATA0 586 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
587 MX8MM_IOMUXC_SD1_DATA1 587 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
588 MX8MM_IOMUXC_SD1_DATA2 588 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
589 MX8MM_IOMUXC_SD1_DATA3 589 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
590 MX8MM_IOMUXC_SD1_DATA4 590 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
591 MX8MM_IOMUXC_SD1_DATA5 591 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
592 MX8MM_IOMUXC_SD1_DATA6 592 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
593 MX8MM_IOMUXC_SD1_DATA7 593 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
594 MX8MM_IOMUXC_SD1_RESET 594 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141
595 >; 595 >;
596 }; 596 };
597 597
598 pinctrl_usdhc1_100mhz: usdhc1-100mhz-g 598 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
599 fsl,pins = < 599 fsl,pins = <
600 MX8MM_IOMUXC_SD1_CLK_U 600 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
601 MX8MM_IOMUXC_SD1_CMD_U 601 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
602 MX8MM_IOMUXC_SD1_DATA0 602 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
603 MX8MM_IOMUXC_SD1_DATA1 603 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
604 MX8MM_IOMUXC_SD1_DATA2 604 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
605 MX8MM_IOMUXC_SD1_DATA3 605 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
606 MX8MM_IOMUXC_SD1_DATA4 606 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
607 MX8MM_IOMUXC_SD1_DATA5 607 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
608 MX8MM_IOMUXC_SD1_DATA6 608 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
609 MX8MM_IOMUXC_SD1_DATA7 609 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
610 >; 610 >;
611 }; 611 };
612 612
613 pinctrl_usdhc1_200mhz: usdhc1-200mhz-g 613 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
614 fsl,pins = < 614 fsl,pins = <
615 MX8MM_IOMUXC_SD1_CLK_U 615 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
616 MX8MM_IOMUXC_SD1_CMD_U 616 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
617 MX8MM_IOMUXC_SD1_DATA0 617 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
618 MX8MM_IOMUXC_SD1_DATA1 618 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
619 MX8MM_IOMUXC_SD1_DATA2 619 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
620 MX8MM_IOMUXC_SD1_DATA3 620 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
621 MX8MM_IOMUXC_SD1_DATA4 621 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
622 MX8MM_IOMUXC_SD1_DATA5 622 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
623 MX8MM_IOMUXC_SD1_DATA6 623 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
624 MX8MM_IOMUXC_SD1_DATA7 624 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
625 >; 625 >;
626 }; 626 };
627 627
628 pinctrl_usdhc2: usdhc2grp { 628 pinctrl_usdhc2: usdhc2grp {
629 fsl,pins = < 629 fsl,pins = <
630 MX8MM_IOMUXC_SD2_CLK_U 630 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
631 MX8MM_IOMUXC_SD2_CMD_U 631 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
632 MX8MM_IOMUXC_SD2_DATA0 632 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
633 MX8MM_IOMUXC_SD2_DATA1 633 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
634 MX8MM_IOMUXC_SD2_DATA2 634 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
635 MX8MM_IOMUXC_SD2_DATA3 635 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
636 MX8MM_IOMUXC_SD2_CD_B_ 636 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
637 >; 637 >;
638 }; 638 };
639 639
640 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g 640 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
641 fsl,pins = < 641 fsl,pins = <
642 MX8MM_IOMUXC_SD2_CLK_U 642 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
643 MX8MM_IOMUXC_SD2_CMD_U 643 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
644 MX8MM_IOMUXC_SD2_DATA0 644 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
645 MX8MM_IOMUXC_SD2_DATA1 645 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
646 MX8MM_IOMUXC_SD2_DATA2 646 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
647 MX8MM_IOMUXC_SD2_DATA3 647 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
648 >; 648 >;
649 }; 649 };
650 650
651 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g 651 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
652 fsl,pins = < 652 fsl,pins = <
653 MX8MM_IOMUXC_SD2_CLK_U 653 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
654 MX8MM_IOMUXC_SD2_CMD_U 654 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
655 MX8MM_IOMUXC_SD2_DATA0 655 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
656 MX8MM_IOMUXC_SD2_DATA1 656 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
657 MX8MM_IOMUXC_SD2_DATA2 657 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
658 MX8MM_IOMUXC_SD2_DATA3 658 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
659 >; 659 >;
660 }; 660 };
661 661
662 pinctrl_usdhc3: usdhc3grp { 662 pinctrl_usdhc3: usdhc3grp {
663 fsl,pins = < 663 fsl,pins = <
664 MX8MM_IOMUXC_NAND_WE_B 664 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
665 MX8MM_IOMUXC_NAND_WP_B 665 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
666 MX8MM_IOMUXC_NAND_DATA 666 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
667 MX8MM_IOMUXC_NAND_DATA 667 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
668 MX8MM_IOMUXC_NAND_DATA 668 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
669 MX8MM_IOMUXC_NAND_DATA 669 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
670 MX8MM_IOMUXC_GPIO1_IO0 670 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
671 >; 671 >;
672 }; 672 };
673 673
674 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g 674 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
675 fsl,pins = < 675 fsl,pins = <
676 MX8MM_IOMUXC_NAND_WE_B 676 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
677 MX8MM_IOMUXC_NAND_WP_B 677 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
678 MX8MM_IOMUXC_NAND_DATA 678 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
679 MX8MM_IOMUXC_NAND_DATA 679 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
680 MX8MM_IOMUXC_NAND_DATA 680 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
681 MX8MM_IOMUXC_NAND_DATA 681 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
682 >; 682 >;
683 }; 683 };
684 684
685 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g 685 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
686 fsl,pins = < 686 fsl,pins = <
687 MX8MM_IOMUXC_NAND_WE_B 687 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
688 MX8MM_IOMUXC_NAND_WP_B 688 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
689 MX8MM_IOMUXC_NAND_DATA 689 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
690 MX8MM_IOMUXC_NAND_DATA 690 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
691 MX8MM_IOMUXC_NAND_DATA 691 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
692 MX8MM_IOMUXC_NAND_DATA 692 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
693 >; 693 >;
694 }; 694 };
695 695
696 pinctrl_wdog: wdoggrp { 696 pinctrl_wdog: wdoggrp {
697 fsl,pins = < 697 fsl,pins = <
698 MX8MM_IOMUXC_GPIO1_IO0 698 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
699 >; 699 >;
700 }; 700 };
701 }; 701 };
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