1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 2
3 &gpu_2d { 3 &gpu_2d {
4 assigned-clocks = <&clk IMX8MM_CLK_GPU 4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
5 <&clk IMX8MM_GPU_PLL 5 <&clk IMX8MM_GPU_PLL_OUT>;
6 assigned-clock-parents = <&clk IMX8MM_ 6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <100000000 7 assigned-clock-rates = <0>, <1000000000>;
8 }; 8 };
9 9
10 &gpu_3d { 10 &gpu_3d {
11 assigned-clocks = <&clk IMX8MM_CLK_GPU 11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
12 <&clk IMX8MM_GPU_PLL 12 <&clk IMX8MM_GPU_PLL_OUT>;
13 assigned-clock-parents = <&clk IMX8MM_ 13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <100000000 14 assigned-clock-rates = <0>, <1000000000>;
15 }; 15 };
16 16
17 &vpu_blk_ctrl { 17 &vpu_blk_ctrl {
18 assigned-clocks = <&clk IMX8MM_CLK_VPU 18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
19 <&clk IMX8MM_CLK_VPU 19 <&clk IMX8MM_CLK_VPU_G2>,
20 <&clk IMX8MM_CLK_VPU 20 <&clk IMX8MM_CLK_VPU_H1>,
21 <&clk IMX8MM_VPU_PLL 21 <&clk IMX8MM_VPU_PLL_OUT>;
22 assigned-clock-parents = <&clk IMX8MM_ 22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
23 <&clk IMX8MM_ 23 <&clk IMX8MM_VPU_PLL_OUT>,
24 <&clk IMX8MM_ 24 <&clk IMX8MM_SYS_PLL3_OUT>;
25 assigned-clock-rates = <750000000>, 25 assigned-clock-rates = <750000000>,
26 <700000000>, 26 <700000000>,
27 <750000000>, 27 <750000000>,
28 <700000000>; 28 <700000000>;
29 }; 29 };
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