1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/interrupt-controller/irq
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi"
13
14 / {
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM
16 compatible = "phytec,imx8mm-phyboard-p
17 "phytec,imx8mm-phycore-so
18
19 chosen {
20 stdout-path = &uart3;
21 };
22
23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_3
27 #clock-cells = <0>;
28 };
29
30 can_osc_40m: can-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_
34 #clock-cells = <0>;
35 };
36
37 fan {
38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_
40 gpio-fan,speed-map = <0 0
41 13000 1>
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>;
51
52 led-0 {
53 color = <LED_COLOR_ID_
54 function = LED_FUNCTIO
55 gpios = <&gpio1 1 GPIO
56 linux,default-trigger
57 };
58
59 led-1 {
60 color = <LED_COLOR_ID_
61 function = LED_FUNCTIO
62 gpios = <&gpio1 15 GPI
63 linux,default-trigger
64 };
65
66 led-2 {
67 color = <LED_COLOR_ID_
68 function = LED_FUNCTIO
69 gpios = <&gpio1 14 GPI
70 linux,default-trigger
71 };
72 };
73
74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simpl
76 post-power-on-delay-ms = <100>
77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_A
79 };
80
81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed"
83 gpio = <&gpio1 9 GPIO_ACTIVE_L
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <330
87 regulator-min-microvolt = <330
88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>;
90 };
91
92 reg_usb_otg1_vbus: regulator-usb-otg1
93 compatible = "regulator-fixed"
94 gpio = <&gpio1 12 GPIO_ACTIVE_
95 enable-active-high;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1p
98 regulator-name = "usb_otg1_vbu
99 regulator-max-microvolt = <500
100 regulator-min-microvolt = <500
101 };
102
103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed"
105 gpio = <&gpio2 19 GPIO_ACTIVE_
106 enable-active-high;
107 off-on-delay-us = <20000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdh
110 regulator-max-microvolt = <330
111 regulator-min-microvolt = <330
112 regulator-name = "VSD_3V3";
113 };
114
115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed"
117 regulator-max-microvolt = <330
118 regulator-min-microvolt = <330
119 regulator-name = "VCC_3V3";
120 };
121 };
122
123 /* SPI - CAN MCP251XFD */
124 &ecspi1 {
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>;
128 status = "okay";
129
130 can0: can@0 {
131 compatible = "microchip,mcp251
132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int>
137 reg = <0>;
138 spi-max-frequency = <20000000>
139 xceiver-supply = <®_can_en>
140 };
141 };
142
143 /* TPM */
144 &ecspi2 {
145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_ecspi2>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "okay";
151
152 tpm: tpm@0 {
153 compatible = "infineon,slb9670
154 interrupt-parent = <&gpio2>;
155 interrupts = <11 IRQ_TYPE_LEVE
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_tpm>;
158 reg = <0>;
159 spi-max-frequency = <43000000>
160 };
161 };
162
163 &gpio1 {
164 gpio-line-names = "", "LED_RED", "WDOG
165 "", "", "", "RESET_ETHPHY",
166 "CAN_nINT", "CAN_EN", "nENABLE
167 "USB_OTG_VBUS_EN", "", "LED_GR
168 };
169
170 &gpio2 {
171 gpio-line-names = "", "", "", "",
172 "", "", "BT_REG_ON", "WL_REG_O
173 "BT_DEV_WAKE", "BT_HOST_WAKE",
174 "X_SD2_CD_B", "", "", "",
175 "", "", "", "SD2_RESET_B";
176 };
177
178 &gpio4 {
179 gpio-line-names = "", "", "", "",
180 "", "", "", "",
181 "FAN", "miniPCIe_nPERST", "",
182 "COEX1", "COEX2";
183 };
184
185 &gpio5 {
186 gpio-line-names = "", "", "", "",
187 "", "", "", "",
188 "", "ECSPI1_SS0";
189 };
190
191 &i2c4 {
192 clock-frequency = <400000>;
193 pinctrl-names = "default", "gpio";
194 pinctrl-0 = <&pinctrl_i2c4>;
195 pinctrl-1 = <&pinctrl_i2c4_gpio>;
196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI
197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI
198 };
199
200 /* PCIe */
201 &pcie0 {
202 assigned-clocks = <&clk IMX8MM_CLK_PCI
203 <&clk IMX8MM_CLK_PCI
204 assigned-clock-parents = <&clk IMX8MM_
205 <&clk IMX8MM_
206 assigned-clock-rates = <10000000>, <25
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_pcie>;
209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW
210 status = "okay";
211 };
212
213 &pcie_phy {
214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
215 fsl,clkreq-unsupported;
216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
217 fsl,tx-deemph-gen1 = <0x2d>;
218 fsl,tx-deemph-gen2 = <0xf>;
219 status = "okay";
220 };
221
222 &rv3028 {
223 aux-voltage-chargeable = <1>;
224 trickle-resistor-ohms = <3000>;
225 };
226
227 &snvs_pwrkey {
228 status = "okay";
229 };
230
231 /* UART - RS232/RS485 */
232 &uart1 {
233 assigned-clocks = <&clk IMX8MM_CLK_UAR
234 assigned-clock-parents = <&clk IMX8MM_
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>;
237 uart-has-rtscts;
238 status = "okay";
239 };
240
241 /* UART - Sterling-LWB Bluetooth */
242 &uart2 {
243 assigned-clocks = <&clk IMX8MM_CLK_UAR
244 assigned-clock-parents = <&clk IMX8MM_
245 fsl,dte-mode;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2_bt>;
248 uart-has-rtscts;
249 status = "okay";
250
251 bluetooth {
252 compatible = "brcm,bcm43438-bt
253 clocks = <&bt_osc_32k>;
254 clock-names = "lpo";
255 device-wakeup-gpios = <&gpio2
256 interrupt-names = "host-wakeup
257 interrupt-parent = <&gpio2>;
258 interrupts = <9 IRQ_TYPE_EDGE_
259 max-speed = <2000000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_bt>;
262 shutdown-gpios = <&gpio2 6 GPI
263 vddio-supply = <®_vcc_3v3>;
264 };
265 };
266
267 /* UART - console */
268 &uart3 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart3>;
271 status = "okay";
272 };
273
274 /* USB */
275 &usbotg1 {
276 adp-disable;
277 dr_mode = "otg";
278 over-current-active-low;
279 samsung,picophy-pre-emp-curr-control =
280 samsung,picophy-dc-vol-level-adjust =
281 srp-disable;
282 vbus-supply = <®_usb_otg1_vbus>;
283 status = "okay";
284 };
285
286 &usbotg2 {
287 disable-over-current;
288 dr_mode = "host";
289 samsung,picophy-pre-emp-curr-control =
290 samsung,picophy-dc-vol-level-adjust =
291 status = "okay";
292 };
293
294 /* SDIO - Sterling-LWB Wifi */
295 &usdhc1 {
296 assigned-clocks = <&clk IMX8MM_CLK_USD
297 assigned-clock-rates = <200000000>;
298 bus-width = <4>;
299 mmc-pwrseq = <&usdhc1_pwrseq>;
300 non-removable;
301 no-1-8-v;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct
304 #address-cells = <1>;
305 #size-cells = <0>;
306 status = "okay";
307
308 brcmf: wifi@1 {
309 compatible = "brcm,bcm4329-fma
310 reg = <1>;
311 };
312 };
313
314 /* SD-Card */
315 &usdhc2 {
316 assigned-clocks = <&clk IMX8MM_CLK_USD
317 assigned-clock-rates = <200000000>;
318 bus-width = <4>;
319 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
320 disable-wp;
321 pinctrl-names = "default", "state_100m
322 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
323 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
324 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
325 vmmc-supply = <®_usdhc2_vmmc>;
326 vqmmc-supply = <®_nvcc_sd2>;
327 status = "okay";
328 };
329
330 &iomuxc {
331 pinctrl_bt: btgrp {
332 fsl,pins = <
333 MX8MM_IOMUXC_SD1_DATA4
334 MX8MM_IOMUXC_SD1_DATA6
335 MX8MM_IOMUXC_SD1_DATA7
336 >;
337 };
338
339 pinctrl_can_en: can-engrp {
340 fsl,pins = <
341 MX8MM_IOMUXC_GPIO1_IO0
342 >;
343 };
344
345 pinctrl_can_int: can-intgrp {
346 fsl,pins = <
347 MX8MM_IOMUXC_GPIO1_IO0
348 >;
349 };
350
351 pinctrl_ecspi1: ecspi1grp {
352 fsl,pins = <
353 MX8MM_IOMUXC_ECSPI1_MI
354 MX8MM_IOMUXC_ECSPI1_MO
355 MX8MM_IOMUXC_ECSPI1_SC
356 MX8MM_IOMUXC_ECSPI1_SS
357 >;
358 };
359
360 pinctrl_ecspi2: ecspi2grp {
361 fsl,pins = <
362 MX8MM_IOMUXC_ECSPI2_MI
363 MX8MM_IOMUXC_ECSPI2_MO
364 MX8MM_IOMUXC_ECSPI2_SC
365 MX8MM_IOMUXC_ECSPI2_SS
366 >;
367 };
368
369 pinctrl_fan: fan0grp {
370 fsl,pins = <
371 MX8MM_IOMUXC_SAI1_RXD6
372 >;
373 };
374
375 pinctrl_i2c4: i2c4grp {
376 fsl,pins = <
377 MX8MM_IOMUXC_I2C4_SCL_
378 MX8MM_IOMUXC_I2C4_SDA_
379 >;
380 };
381
382 pinctrl_i2c4_gpio: i2c4gpiogrp {
383 fsl,pins = <
384 MX8MM_IOMUXC_I2C4_SCL_
385 MX8MM_IOMUXC_I2C4_SDA_
386 >;
387 };
388
389 pinctrl_leds: leds1grp {
390 fsl,pins = <
391 MX8MM_IOMUXC_GPIO1_IO0
392 MX8MM_IOMUXC_GPIO1_IO1
393 MX8MM_IOMUXC_GPIO1_IO1
394 >;
395 };
396
397 pinctrl_pcie: pciegrp {
398 fsl,pins = <
399 MX8MM_IOMUXC_SAI1_RXD7
400 MX8MM_IOMUXC_SAI1_TXD0
401 MX8MM_IOMUXC_SAI1_TXD7
402 >;
403 };
404
405 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc
406 fsl,pins = <
407 MX8MM_IOMUXC_SD2_RESET
408 >;
409 };
410
411 pinctrl_tpm: tpmgrp {
412 fsl,pins = <
413 MX8MM_IOMUXC_SD1_STROB
414 >;
415 };
416
417 pinctrl_uart1: uart1grp {
418 fsl,pins = <
419 MX8MM_IOMUXC_SAI2_RXC_
420 MX8MM_IOMUXC_SAI2_RXD0
421 MX8MM_IOMUXC_SAI2_RXFS
422 MX8MM_IOMUXC_SAI2_TXFS
423 >;
424 };
425
426 pinctrl_uart2_bt: uart2btgrp {
427 fsl,pins = <
428 MX8MM_IOMUXC_SAI3_RXC_
429 MX8MM_IOMUXC_SAI3_RXD_
430 MX8MM_IOMUXC_SAI3_TXC_
431 MX8MM_IOMUXC_SAI3_TXFS
432 >;
433 };
434
435 pinctrl_uart3: uart3grp {
436 fsl,pins = <
437 MX8MM_IOMUXC_UART3_RXD
438 MX8MM_IOMUXC_UART3_TXD
439 >;
440 };
441
442 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
443 fsl,pins = <
444 MX8MM_IOMUXC_GPIO1_IO1
445 >;
446 };
447
448 pinctrl_usdhc1: usdhc1grp {
449 fsl,pins = <
450 MX8MM_IOMUXC_SD1_CLK_U
451 MX8MM_IOMUXC_SD1_CMD_U
452 MX8MM_IOMUXC_SD1_DATA0
453 MX8MM_IOMUXC_SD1_DATA1
454 MX8MM_IOMUXC_SD1_DATA2
455 MX8MM_IOMUXC_SD1_DATA3
456 >;
457 };
458
459 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
460 fsl,pins = <
461 MX8MM_IOMUXC_SD2_CD_B_
462 >;
463 };
464
465 pinctrl_usdhc2: usdhc2grp {
466 fsl,pins = <
467 MX8MM_IOMUXC_GPIO1_IO0
468 MX8MM_IOMUXC_SD2_CLK_U
469 MX8MM_IOMUXC_SD2_CMD_U
470 MX8MM_IOMUXC_SD2_DATA0
471 MX8MM_IOMUXC_SD2_DATA1
472 MX8MM_IOMUXC_SD2_DATA2
473 MX8MM_IOMUXC_SD2_DATA3
474 >;
475 };
476
477 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
478 fsl,pins = <
479 MX8MM_IOMUXC_GPIO1_IO0
480 MX8MM_IOMUXC_SD2_CLK_U
481 MX8MM_IOMUXC_SD2_CMD_U
482 MX8MM_IOMUXC_SD2_DATA0
483 MX8MM_IOMUXC_SD2_DATA1
484 MX8MM_IOMUXC_SD2_DATA2
485 MX8MM_IOMUXC_SD2_DATA3
486 >;
487 };
488
489 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
490 fsl,pins = <
491 MX8MM_IOMUXC_GPIO1_IO0
492 MX8MM_IOMUXC_SD2_CLK_U
493 MX8MM_IOMUXC_SD2_CMD_U
494 MX8MM_IOMUXC_SD2_DATA0
495 MX8MM_IOMUXC_SD2_DATA1
496 MX8MM_IOMUXC_SD2_DATA2
497 MX8MM_IOMUXC_SD2_DATA3
498 >;
499 };
500
501 pinctrl_wlan: wlangrp {
502 fsl,pins = <
503 MX8MM_IOMUXC_SD1_DATA5
504 >;
505 };
506 };
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