1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de> 4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi" 12 #include "imx8mm-phycore-som.dtsi"
13 13
14 / { 14 / {
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM 15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-p 16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-so 17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart3; 20 stdout-path = &uart3;
21 }; 21 };
22 22
23 bt_osc_32k: bt-lp-clock { 23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 clock-frequency = <32768>; 25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_3 26 clock-output-names = "bt_osc_32k";
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 29
30 can_osc_40m: can-clock { 30 can_osc_40m: can-clock {
31 compatible = "fixed-clock"; 31 compatible = "fixed-clock";
32 clock-frequency = <40000000>; 32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_ 33 clock-output-names = "can_osc_40m";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 }; 35 };
36 36
37 fan { 37 fan {
38 compatible = "gpio-fan"; 38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_ 39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
40 gpio-fan,speed-map = <0 0 40 gpio-fan,speed-map = <0 0
41 13000 1> 41 13000 1>;
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>; 43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>; 44 #cooling-cells = <2>;
45 }; 45 };
46 46
47 leds { 47 leds {
48 compatible = "gpio-leds"; 48 compatible = "gpio-leds";
49 pinctrl-names = "default"; 49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>; 50 pinctrl-0 = <&pinctrl_leds>;
51 51
52 led-0 { 52 led-0 {
53 color = <LED_COLOR_ID_ 53 color = <LED_COLOR_ID_RED>;
54 function = LED_FUNCTIO 54 function = LED_FUNCTION_DISK;
55 gpios = <&gpio1 1 GPIO 55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger 56 linux,default-trigger = "mmc2";
57 }; 57 };
58 58
59 led-1 { 59 led-1 {
60 color = <LED_COLOR_ID_ 60 color = <LED_COLOR_ID_BLUE>;
61 function = LED_FUNCTIO 61 function = LED_FUNCTION_DISK;
62 gpios = <&gpio1 15 GPI 62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger 63 linux,default-trigger = "mmc1";
64 }; 64 };
65 65
66 led-2 { 66 led-2 {
67 color = <LED_COLOR_ID_ 67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTIO 68 function = LED_FUNCTION_CPU;
69 gpios = <&gpio1 14 GPI 69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger 70 linux,default-trigger = "heartbeat";
71 }; 71 };
72 }; 72 };
73 73
74 usdhc1_pwrseq: pwr-seq { 74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simpl 75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100> 76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>; 77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_A 78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
79 }; 79 };
80 80
81 reg_can_en: regulator-can-en { 81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed" 82 compatible = "regulator-fixed";
83 gpio = <&gpio1 9 GPIO_ACTIVE_L 83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default"; 84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>; 85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <330 86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <330 87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN"; 88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>; 89 startup-delay-us = <20>;
90 }; 90 };
91 91
92 reg_usb_otg1_vbus: regulator-usb-otg1 92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed" 93 compatible = "regulator-fixed";
94 gpio = <&gpio1 12 GPIO_ACTIVE_ 94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
95 enable-active-high; 95 enable-active-high;
96 pinctrl-names = "default"; 96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1p 97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbu 98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <500 99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <500 100 regulator-min-microvolt = <5000000>;
101 }; 101 };
102 102
103 reg_usdhc2_vmmc: regulator-usdhc2 { 103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed" 104 compatible = "regulator-fixed";
105 gpio = <&gpio2 19 GPIO_ACTIVE_ 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
106 enable-active-high; 106 enable-active-high;
107 off-on-delay-us = <20000>; 107 off-on-delay-us = <20000>;
108 pinctrl-names = "default"; 108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdh 109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <330 110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <330 111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3"; 112 regulator-name = "VSD_3V3";
113 }; 113 };
114 114
115 reg_vcc_3v3: regulator-vcc-3v3 { 115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed" 116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <330 117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <330 118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3"; 119 regulator-name = "VCC_3V3";
120 }; 120 };
121 }; 121 };
122 122
123 /* SPI - CAN MCP251XFD */ 123 /* SPI - CAN MCP251XFD */
124 &ecspi1 { 124 &ecspi1 {
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default"; 126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>; 127 pinctrl-0 = <&pinctrl_ecspi1>;
128 status = "okay"; 128 status = "okay";
129 129
130 can0: can@0 { 130 can0: can@0 {
131 compatible = "microchip,mcp251 131 compatible = "microchip,mcp251xfd";
132 clocks = <&can_osc_40m>; 132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>; 133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL 134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
135 pinctrl-names = "default"; 135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int> 136 pinctrl-0 = <&pinctrl_can_int>;
137 reg = <0>; 137 reg = <0>;
138 spi-max-frequency = <20000000> 138 spi-max-frequency = <20000000>;
139 xceiver-supply = <®_can_en> 139 xceiver-supply = <®_can_en>;
140 }; 140 };
141 }; 141 };
142 142
143 /* TPM */ <<
144 &ecspi2 { <<
145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> <<
146 pinctrl-names = "default"; <<
147 pinctrl-0 = <&pinctrl_ecspi2>; <<
148 #address-cells = <1>; <<
149 #size-cells = <0>; <<
150 status = "okay"; <<
151 <<
152 tpm: tpm@0 { <<
153 compatible = "infineon,slb9670 <<
154 interrupt-parent = <&gpio2>; <<
155 interrupts = <11 IRQ_TYPE_LEVE <<
156 pinctrl-names = "default"; <<
157 pinctrl-0 = <&pinctrl_tpm>; <<
158 reg = <0>; <<
159 spi-max-frequency = <43000000> <<
160 }; <<
161 }; <<
162 <<
163 &gpio1 { 143 &gpio1 {
164 gpio-line-names = "", "LED_RED", "WDOG 144 gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
165 "", "", "", "RESET_ETHPHY", 145 "", "", "", "RESET_ETHPHY",
166 "CAN_nINT", "CAN_EN", "nENABLE 146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
167 "USB_OTG_VBUS_EN", "", "LED_GR 147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
168 }; 148 };
169 149
170 &gpio2 { 150 &gpio2 {
171 gpio-line-names = "", "", "", "", 151 gpio-line-names = "", "", "", "",
172 "", "", "BT_REG_ON", "WL_REG_O 152 "", "", "BT_REG_ON", "WL_REG_ON",
173 "BT_DEV_WAKE", "BT_HOST_WAKE", 153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
174 "X_SD2_CD_B", "", "", "", 154 "X_SD2_CD_B", "", "", "",
175 "", "", "", "SD2_RESET_B"; 155 "", "", "", "SD2_RESET_B";
176 }; 156 };
177 157
178 &gpio4 { 158 &gpio4 {
179 gpio-line-names = "", "", "", "", 159 gpio-line-names = "", "", "", "",
180 "", "", "", "", 160 "", "", "", "",
181 "FAN", "miniPCIe_nPERST", "", 161 "FAN", "miniPCIe_nPERST", "", "",
182 "COEX1", "COEX2"; 162 "COEX1", "COEX2";
183 }; 163 };
184 164
185 &gpio5 { 165 &gpio5 {
186 gpio-line-names = "", "", "", "", 166 gpio-line-names = "", "", "", "",
187 "", "", "", "", 167 "", "", "", "",
188 "", "ECSPI1_SS0"; 168 "", "ECSPI1_SS0";
189 }; 169 };
190 170
191 &i2c4 { <<
192 clock-frequency = <400000>; <<
193 pinctrl-names = "default", "gpio"; <<
194 pinctrl-0 = <&pinctrl_i2c4>; <<
195 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
198 }; <<
199 <<
200 /* PCIe */ 171 /* PCIe */
201 &pcie0 { 172 &pcie0 {
202 assigned-clocks = <&clk IMX8MM_CLK_PCI 173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
203 <&clk IMX8MM_CLK_PCI 174 <&clk IMX8MM_CLK_PCIE1_CTRL>;
204 assigned-clock-parents = <&clk IMX8MM_ 175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
205 <&clk IMX8MM_ 176 <&clk IMX8MM_SYS_PLL2_250M>;
206 assigned-clock-rates = <10000000>, <25 177 assigned-clock-rates = <10000000>, <250000000>;
>> 178 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
>> 179 <&clk IMX8MM_CLK_PCIE1_PHY>;
>> 180 clock-names = "pcie", "pcie_aux", "pcie_bus";
207 pinctrl-names = "default"; 181 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_pcie>; 182 pinctrl-0 = <&pinctrl_pcie>;
209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW 183 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 184 status = "okay";
211 }; 185 };
212 186
213 &pcie_phy { 187 &pcie_phy {
214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 188 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
215 fsl,clkreq-unsupported; 189 fsl,clkreq-unsupported;
216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 190 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
217 fsl,tx-deemph-gen1 = <0x2d>; 191 fsl,tx-deemph-gen1 = <0x2d>;
218 fsl,tx-deemph-gen2 = <0xf>; 192 fsl,tx-deemph-gen2 = <0xf>;
219 status = "okay"; 193 status = "okay";
220 }; 194 };
221 195
222 &rv3028 { 196 &rv3028 {
223 aux-voltage-chargeable = <1>; <<
224 trickle-resistor-ohms = <3000>; 197 trickle-resistor-ohms = <3000>;
225 }; 198 };
226 199
227 &snvs_pwrkey { 200 &snvs_pwrkey {
228 status = "okay"; 201 status = "okay";
229 }; 202 };
230 203
231 /* UART - RS232/RS485 */ 204 /* UART - RS232/RS485 */
232 &uart1 { 205 &uart1 {
233 assigned-clocks = <&clk IMX8MM_CLK_UAR 206 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
234 assigned-clock-parents = <&clk IMX8MM_ 207 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
235 pinctrl-names = "default"; 208 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>; 209 pinctrl-0 = <&pinctrl_uart1>;
237 uart-has-rtscts; 210 uart-has-rtscts;
238 status = "okay"; 211 status = "okay";
239 }; 212 };
240 213
241 /* UART - Sterling-LWB Bluetooth */ 214 /* UART - Sterling-LWB Bluetooth */
242 &uart2 { 215 &uart2 {
243 assigned-clocks = <&clk IMX8MM_CLK_UAR 216 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
244 assigned-clock-parents = <&clk IMX8MM_ 217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
245 fsl,dte-mode; 218 fsl,dte-mode;
246 pinctrl-names = "default"; 219 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2_bt>; 220 pinctrl-0 = <&pinctrl_uart2_bt>;
248 uart-has-rtscts; 221 uart-has-rtscts;
249 status = "okay"; 222 status = "okay";
250 223
251 bluetooth { 224 bluetooth {
252 compatible = "brcm,bcm43438-bt 225 compatible = "brcm,bcm43438-bt";
253 clocks = <&bt_osc_32k>; 226 clocks = <&bt_osc_32k>;
254 clock-names = "lpo"; 227 clock-names = "lpo";
255 device-wakeup-gpios = <&gpio2 228 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
256 interrupt-names = "host-wakeup 229 interrupt-names = "host-wakeup";
257 interrupt-parent = <&gpio2>; 230 interrupt-parent = <&gpio2>;
258 interrupts = <9 IRQ_TYPE_EDGE_ 231 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
259 max-speed = <2000000>; 232 max-speed = <2000000>;
260 pinctrl-names = "default"; 233 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_bt>; 234 pinctrl-0 = <&pinctrl_bt>;
262 shutdown-gpios = <&gpio2 6 GPI 235 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
263 vddio-supply = <®_vcc_3v3>; 236 vddio-supply = <®_vcc_3v3>;
264 }; 237 };
265 }; 238 };
266 239
267 /* UART - console */ 240 /* UART - console */
268 &uart3 { 241 &uart3 {
269 pinctrl-names = "default"; 242 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart3>; 243 pinctrl-0 = <&pinctrl_uart3>;
271 status = "okay"; 244 status = "okay";
272 }; 245 };
273 246
274 /* USB */ 247 /* USB */
275 &usbotg1 { 248 &usbotg1 {
276 adp-disable; 249 adp-disable;
277 dr_mode = "otg"; 250 dr_mode = "otg";
278 over-current-active-low; 251 over-current-active-low;
279 samsung,picophy-pre-emp-curr-control = 252 samsung,picophy-pre-emp-curr-control = <3>;
280 samsung,picophy-dc-vol-level-adjust = 253 samsung,picophy-dc-vol-level-adjust = <7>;
281 srp-disable; 254 srp-disable;
282 vbus-supply = <®_usb_otg1_vbus>; 255 vbus-supply = <®_usb_otg1_vbus>;
283 status = "okay"; 256 status = "okay";
284 }; 257 };
285 258
286 &usbotg2 { 259 &usbotg2 {
287 disable-over-current; 260 disable-over-current;
288 dr_mode = "host"; 261 dr_mode = "host";
289 samsung,picophy-pre-emp-curr-control = 262 samsung,picophy-pre-emp-curr-control = <3>;
290 samsung,picophy-dc-vol-level-adjust = 263 samsung,picophy-dc-vol-level-adjust = <7>;
291 status = "okay"; 264 status = "okay";
292 }; 265 };
293 266
294 /* SDIO - Sterling-LWB Wifi */ 267 /* SDIO - Sterling-LWB Wifi */
295 &usdhc1 { 268 &usdhc1 {
296 assigned-clocks = <&clk IMX8MM_CLK_USD 269 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
297 assigned-clock-rates = <200000000>; 270 assigned-clock-rates = <200000000>;
298 bus-width = <4>; 271 bus-width = <4>;
299 mmc-pwrseq = <&usdhc1_pwrseq>; 272 mmc-pwrseq = <&usdhc1_pwrseq>;
300 non-removable; 273 non-removable;
301 no-1-8-v; 274 no-1-8-v;
302 pinctrl-names = "default"; 275 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct 276 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
304 #address-cells = <1>; 277 #address-cells = <1>;
305 #size-cells = <0>; 278 #size-cells = <0>;
306 status = "okay"; 279 status = "okay";
307 280
308 brcmf: wifi@1 { 281 brcmf: wifi@1 {
309 compatible = "brcm,bcm4329-fma 282 compatible = "brcm,bcm4329-fmac";
310 reg = <1>; 283 reg = <1>;
311 }; 284 };
312 }; 285 };
313 286
314 /* SD-Card */ 287 /* SD-Card */
315 &usdhc2 { 288 &usdhc2 {
316 assigned-clocks = <&clk IMX8MM_CLK_USD 289 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
317 assigned-clock-rates = <200000000>; 290 assigned-clock-rates = <200000000>;
318 bus-width = <4>; 291 bus-width = <4>;
319 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 292 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
320 disable-wp; 293 disable-wp;
321 pinctrl-names = "default", "state_100m 294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
322 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 295 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
323 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 296 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
324 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 297 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
325 vmmc-supply = <®_usdhc2_vmmc>; 298 vmmc-supply = <®_usdhc2_vmmc>;
326 vqmmc-supply = <®_nvcc_sd2>; 299 vqmmc-supply = <®_nvcc_sd2>;
327 status = "okay"; 300 status = "okay";
328 }; 301 };
329 302
330 &iomuxc { 303 &iomuxc {
331 pinctrl_bt: btgrp { 304 pinctrl_bt: btgrp {
332 fsl,pins = < 305 fsl,pins = <
333 MX8MM_IOMUXC_SD1_DATA4 306 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
334 MX8MM_IOMUXC_SD1_DATA6 307 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
335 MX8MM_IOMUXC_SD1_DATA7 308 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
336 >; 309 >;
337 }; 310 };
338 311
339 pinctrl_can_en: can-engrp { 312 pinctrl_can_en: can-engrp {
340 fsl,pins = < 313 fsl,pins = <
341 MX8MM_IOMUXC_GPIO1_IO0 314 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
342 >; 315 >;
343 }; 316 };
344 317
345 pinctrl_can_int: can-intgrp { 318 pinctrl_can_int: can-intgrp {
346 fsl,pins = < 319 fsl,pins = <
347 MX8MM_IOMUXC_GPIO1_IO0 320 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
348 >; 321 >;
349 }; 322 };
350 323
351 pinctrl_ecspi1: ecspi1grp { 324 pinctrl_ecspi1: ecspi1grp {
352 fsl,pins = < 325 fsl,pins = <
353 MX8MM_IOMUXC_ECSPI1_MI 326 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
354 MX8MM_IOMUXC_ECSPI1_MO 327 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
355 MX8MM_IOMUXC_ECSPI1_SC 328 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
356 MX8MM_IOMUXC_ECSPI1_SS 329 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
357 >; 330 >;
358 }; 331 };
359 332
360 pinctrl_ecspi2: ecspi2grp { <<
361 fsl,pins = < <<
362 MX8MM_IOMUXC_ECSPI2_MI <<
363 MX8MM_IOMUXC_ECSPI2_MO <<
364 MX8MM_IOMUXC_ECSPI2_SC <<
365 MX8MM_IOMUXC_ECSPI2_SS <<
366 >; <<
367 }; <<
368 <<
369 pinctrl_fan: fan0grp { 333 pinctrl_fan: fan0grp {
370 fsl,pins = < 334 fsl,pins = <
371 MX8MM_IOMUXC_SAI1_RXD6 335 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
372 >; 336 >;
373 }; 337 };
374 338
375 pinctrl_i2c4: i2c4grp { <<
376 fsl,pins = < <<
377 MX8MM_IOMUXC_I2C4_SCL_ <<
378 MX8MM_IOMUXC_I2C4_SDA_ <<
379 >; <<
380 }; <<
381 <<
382 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
383 fsl,pins = < <<
384 MX8MM_IOMUXC_I2C4_SCL_ <<
385 MX8MM_IOMUXC_I2C4_SDA_ <<
386 >; <<
387 }; <<
388 <<
389 pinctrl_leds: leds1grp { 339 pinctrl_leds: leds1grp {
390 fsl,pins = < 340 fsl,pins = <
391 MX8MM_IOMUXC_GPIO1_IO0 341 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
392 MX8MM_IOMUXC_GPIO1_IO1 342 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
393 MX8MM_IOMUXC_GPIO1_IO1 343 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
394 >; 344 >;
395 }; 345 };
396 346
397 pinctrl_pcie: pciegrp { 347 pinctrl_pcie: pciegrp {
398 fsl,pins = < 348 fsl,pins = <
399 MX8MM_IOMUXC_SAI1_RXD7 349 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
400 MX8MM_IOMUXC_SAI1_TXD0 350 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
401 MX8MM_IOMUXC_SAI1_TXD7 351 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
402 >; 352 >;
403 }; 353 };
404 354
405 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 355 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
406 fsl,pins = < 356 fsl,pins = <
407 MX8MM_IOMUXC_SD2_RESET 357 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
408 >; 358 >;
409 }; 359 };
410 360
411 pinctrl_tpm: tpmgrp { <<
412 fsl,pins = < <<
413 MX8MM_IOMUXC_SD1_STROB <<
414 >; <<
415 }; <<
416 <<
417 pinctrl_uart1: uart1grp { 361 pinctrl_uart1: uart1grp {
418 fsl,pins = < 362 fsl,pins = <
419 MX8MM_IOMUXC_SAI2_RXC_ 363 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
420 MX8MM_IOMUXC_SAI2_RXD0 364 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
421 MX8MM_IOMUXC_SAI2_RXFS 365 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
422 MX8MM_IOMUXC_SAI2_TXFS 366 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
423 >; 367 >;
424 }; 368 };
425 369
426 pinctrl_uart2_bt: uart2btgrp { 370 pinctrl_uart2_bt: uart2btgrp {
427 fsl,pins = < 371 fsl,pins = <
428 MX8MM_IOMUXC_SAI3_RXC_ 372 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
429 MX8MM_IOMUXC_SAI3_RXD_ 373 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
430 MX8MM_IOMUXC_SAI3_TXC_ 374 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
431 MX8MM_IOMUXC_SAI3_TXFS 375 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
432 >; 376 >;
433 }; 377 };
434 378
435 pinctrl_uart3: uart3grp { 379 pinctrl_uart3: uart3grp {
436 fsl,pins = < 380 fsl,pins = <
437 MX8MM_IOMUXC_UART3_RXD !! 381 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
438 MX8MM_IOMUXC_UART3_TXD !! 382 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
439 >; 383 >;
440 }; 384 };
441 385
442 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 386 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
443 fsl,pins = < 387 fsl,pins = <
444 MX8MM_IOMUXC_GPIO1_IO1 388 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
445 >; 389 >;
446 }; 390 };
447 391
448 pinctrl_usdhc1: usdhc1grp { 392 pinctrl_usdhc1: usdhc1grp {
449 fsl,pins = < 393 fsl,pins = <
450 MX8MM_IOMUXC_SD1_CLK_U 394 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
451 MX8MM_IOMUXC_SD1_CMD_U 395 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
452 MX8MM_IOMUXC_SD1_DATA0 396 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
453 MX8MM_IOMUXC_SD1_DATA1 397 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
454 MX8MM_IOMUXC_SD1_DATA2 398 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
455 MX8MM_IOMUXC_SD1_DATA3 399 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
456 >; 400 >;
457 }; 401 };
458 402
459 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 403 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
460 fsl,pins = < 404 fsl,pins = <
461 MX8MM_IOMUXC_SD2_CD_B_ 405 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
462 >; 406 >;
463 }; 407 };
464 408
465 pinctrl_usdhc2: usdhc2grp { 409 pinctrl_usdhc2: usdhc2grp {
466 fsl,pins = < 410 fsl,pins = <
467 MX8MM_IOMUXC_GPIO1_IO0 411 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
468 MX8MM_IOMUXC_SD2_CLK_U 412 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
469 MX8MM_IOMUXC_SD2_CMD_U 413 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
470 MX8MM_IOMUXC_SD2_DATA0 414 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
471 MX8MM_IOMUXC_SD2_DATA1 415 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
472 MX8MM_IOMUXC_SD2_DATA2 416 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
473 MX8MM_IOMUXC_SD2_DATA3 417 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
474 >; 418 >;
475 }; 419 };
476 420
477 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 421 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
478 fsl,pins = < 422 fsl,pins = <
479 MX8MM_IOMUXC_GPIO1_IO0 423 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
480 MX8MM_IOMUXC_SD2_CLK_U 424 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
481 MX8MM_IOMUXC_SD2_CMD_U 425 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
482 MX8MM_IOMUXC_SD2_DATA0 426 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
483 MX8MM_IOMUXC_SD2_DATA1 427 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
484 MX8MM_IOMUXC_SD2_DATA2 428 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
485 MX8MM_IOMUXC_SD2_DATA3 429 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
486 >; 430 >;
487 }; 431 };
488 432
489 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 433 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
490 fsl,pins = < 434 fsl,pins = <
491 MX8MM_IOMUXC_GPIO1_IO0 435 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
492 MX8MM_IOMUXC_SD2_CLK_U 436 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
493 MX8MM_IOMUXC_SD2_CMD_U 437 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
494 MX8MM_IOMUXC_SD2_DATA0 438 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
495 MX8MM_IOMUXC_SD2_DATA1 439 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
496 MX8MM_IOMUXC_SD2_DATA2 440 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
497 MX8MM_IOMUXC_SD2_DATA3 441 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
498 >; 442 >;
499 }; 443 };
500 444
501 pinctrl_wlan: wlangrp { 445 pinctrl_wlan: wlangrp {
502 fsl,pins = < 446 fsl,pins = <
503 MX8MM_IOMUXC_SD1_DATA5 447 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
504 >; 448 >;
505 }; 449 };
506 }; 450 };
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