1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de> 4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi" 12 #include "imx8mm-phycore-som.dtsi"
13 13
14 / { 14 / {
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM 15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-p 16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-so 17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart3; 20 stdout-path = &uart3;
21 }; 21 };
22 22
23 bt_osc_32k: bt-lp-clock { 23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 clock-frequency = <32768>; 25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_3 26 clock-output-names = "bt_osc_32k";
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 29
30 can_osc_40m: can-clock { 30 can_osc_40m: can-clock {
31 compatible = "fixed-clock"; 31 compatible = "fixed-clock";
32 clock-frequency = <40000000>; 32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_ 33 clock-output-names = "can_osc_40m";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 }; 35 };
36 36
37 fan { 37 fan {
38 compatible = "gpio-fan"; 38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_ 39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
40 gpio-fan,speed-map = <0 0 40 gpio-fan,speed-map = <0 0
41 13000 1> 41 13000 1>;
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>; 43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>; 44 #cooling-cells = <2>;
45 }; 45 };
46 46
47 leds { 47 leds {
48 compatible = "gpio-leds"; 48 compatible = "gpio-leds";
49 pinctrl-names = "default"; 49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>; 50 pinctrl-0 = <&pinctrl_leds>;
51 51
52 led-0 { 52 led-0 {
53 color = <LED_COLOR_ID_ 53 color = <LED_COLOR_ID_RED>;
54 function = LED_FUNCTIO 54 function = LED_FUNCTION_DISK;
55 gpios = <&gpio1 1 GPIO 55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger 56 linux,default-trigger = "mmc2";
57 }; 57 };
58 58
59 led-1 { 59 led-1 {
60 color = <LED_COLOR_ID_ 60 color = <LED_COLOR_ID_BLUE>;
61 function = LED_FUNCTIO 61 function = LED_FUNCTION_DISK;
62 gpios = <&gpio1 15 GPI 62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger 63 linux,default-trigger = "mmc1";
64 }; 64 };
65 65
66 led-2 { 66 led-2 {
67 color = <LED_COLOR_ID_ 67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTIO 68 function = LED_FUNCTION_CPU;
69 gpios = <&gpio1 14 GPI 69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger 70 linux,default-trigger = "heartbeat";
71 }; 71 };
72 }; 72 };
73 73
74 usdhc1_pwrseq: pwr-seq { 74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simpl 75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100> 76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>; 77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_A 78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
79 }; 79 };
80 80
81 reg_can_en: regulator-can-en { 81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed" 82 compatible = "regulator-fixed";
83 gpio = <&gpio1 9 GPIO_ACTIVE_L 83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default"; 84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>; 85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <330 86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <330 87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN"; 88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>; 89 startup-delay-us = <20>;
90 }; 90 };
91 91
92 reg_usb_otg1_vbus: regulator-usb-otg1 92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed" 93 compatible = "regulator-fixed";
94 gpio = <&gpio1 12 GPIO_ACTIVE_ 94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
95 enable-active-high; 95 enable-active-high;
96 pinctrl-names = "default"; 96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1p 97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbu 98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <500 99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <500 100 regulator-min-microvolt = <5000000>;
101 }; 101 };
102 102
103 reg_usdhc2_vmmc: regulator-usdhc2 { 103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed" 104 compatible = "regulator-fixed";
105 gpio = <&gpio2 19 GPIO_ACTIVE_ 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
106 enable-active-high; 106 enable-active-high;
107 off-on-delay-us = <20000>; 107 off-on-delay-us = <20000>;
108 pinctrl-names = "default"; 108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdh 109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <330 110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <330 111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3"; 112 regulator-name = "VSD_3V3";
113 }; 113 };
114 114
115 reg_vcc_3v3: regulator-vcc-3v3 { 115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed" 116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <330 117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <330 118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3"; 119 regulator-name = "VCC_3V3";
120 }; 120 };
121 }; 121 };
122 122
123 /* SPI - CAN MCP251XFD */ 123 /* SPI - CAN MCP251XFD */
124 &ecspi1 { 124 &ecspi1 {
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default"; 126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>; 127 pinctrl-0 = <&pinctrl_ecspi1>;
128 status = "okay"; 128 status = "okay";
129 129
130 can0: can@0 { 130 can0: can@0 {
131 compatible = "microchip,mcp251 131 compatible = "microchip,mcp251xfd";
132 clocks = <&can_osc_40m>; 132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>; 133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL 134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
135 pinctrl-names = "default"; 135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int> 136 pinctrl-0 = <&pinctrl_can_int>;
137 reg = <0>; 137 reg = <0>;
138 spi-max-frequency = <20000000> 138 spi-max-frequency = <20000000>;
139 xceiver-supply = <®_can_en> 139 xceiver-supply = <®_can_en>;
140 }; 140 };
141 }; 141 };
142 142
143 /* TPM */ 143 /* TPM */
144 &ecspi2 { 144 &ecspi2 {
145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
146 pinctrl-names = "default"; 146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_ecspi2>; 147 pinctrl-0 = <&pinctrl_ecspi2>;
148 #address-cells = <1>; 148 #address-cells = <1>;
149 #size-cells = <0>; 149 #size-cells = <0>;
150 status = "okay"; 150 status = "okay";
151 151
152 tpm: tpm@0 { 152 tpm: tpm@0 {
153 compatible = "infineon,slb9670 153 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
154 interrupt-parent = <&gpio2>; 154 interrupt-parent = <&gpio2>;
155 interrupts = <11 IRQ_TYPE_LEVE 155 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
156 pinctrl-names = "default"; 156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_tpm>; 157 pinctrl-0 = <&pinctrl_tpm>;
158 reg = <0>; 158 reg = <0>;
159 spi-max-frequency = <43000000> 159 spi-max-frequency = <43000000>;
160 }; 160 };
161 }; 161 };
162 162
163 &gpio1 { 163 &gpio1 {
164 gpio-line-names = "", "LED_RED", "WDOG 164 gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
165 "", "", "", "RESET_ETHPHY", 165 "", "", "", "RESET_ETHPHY",
166 "CAN_nINT", "CAN_EN", "nENABLE 166 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
167 "USB_OTG_VBUS_EN", "", "LED_GR 167 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
168 }; 168 };
169 169
170 &gpio2 { 170 &gpio2 {
171 gpio-line-names = "", "", "", "", 171 gpio-line-names = "", "", "", "",
172 "", "", "BT_REG_ON", "WL_REG_O 172 "", "", "BT_REG_ON", "WL_REG_ON",
173 "BT_DEV_WAKE", "BT_HOST_WAKE", 173 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
174 "X_SD2_CD_B", "", "", "", 174 "X_SD2_CD_B", "", "", "",
175 "", "", "", "SD2_RESET_B"; 175 "", "", "", "SD2_RESET_B";
176 }; 176 };
177 177
178 &gpio4 { 178 &gpio4 {
179 gpio-line-names = "", "", "", "", 179 gpio-line-names = "", "", "", "",
180 "", "", "", "", 180 "", "", "", "",
181 "FAN", "miniPCIe_nPERST", "", 181 "FAN", "miniPCIe_nPERST", "", "",
182 "COEX1", "COEX2"; 182 "COEX1", "COEX2";
183 }; 183 };
184 184
185 &gpio5 { 185 &gpio5 {
186 gpio-line-names = "", "", "", "", 186 gpio-line-names = "", "", "", "",
187 "", "", "", "", 187 "", "", "", "",
188 "", "ECSPI1_SS0"; 188 "", "ECSPI1_SS0";
189 }; 189 };
190 190
191 &i2c4 { 191 &i2c4 {
192 clock-frequency = <400000>; 192 clock-frequency = <400000>;
193 pinctrl-names = "default", "gpio"; 193 pinctrl-names = "default", "gpio";
194 pinctrl-0 = <&pinctrl_i2c4>; 194 pinctrl-0 = <&pinctrl_i2c4>;
195 pinctrl-1 = <&pinctrl_i2c4_gpio>; 195 pinctrl-1 = <&pinctrl_i2c4_gpio>;
196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
198 }; 198 };
199 199
200 /* PCIe */ 200 /* PCIe */
201 &pcie0 { 201 &pcie0 {
202 assigned-clocks = <&clk IMX8MM_CLK_PCI 202 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
203 <&clk IMX8MM_CLK_PCI 203 <&clk IMX8MM_CLK_PCIE1_CTRL>;
204 assigned-clock-parents = <&clk IMX8MM_ 204 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
205 <&clk IMX8MM_ 205 <&clk IMX8MM_SYS_PLL2_250M>;
206 assigned-clock-rates = <10000000>, <25 206 assigned-clock-rates = <10000000>, <250000000>;
207 pinctrl-names = "default"; 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_pcie>; 208 pinctrl-0 = <&pinctrl_pcie>;
209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW 209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 210 status = "okay";
211 }; 211 };
212 212
213 &pcie_phy { 213 &pcie_phy {
214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
215 fsl,clkreq-unsupported; 215 fsl,clkreq-unsupported;
216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
217 fsl,tx-deemph-gen1 = <0x2d>; 217 fsl,tx-deemph-gen1 = <0x2d>;
218 fsl,tx-deemph-gen2 = <0xf>; 218 fsl,tx-deemph-gen2 = <0xf>;
219 status = "okay"; 219 status = "okay";
220 }; 220 };
221 221
222 &rv3028 { 222 &rv3028 {
223 aux-voltage-chargeable = <1>; <<
224 trickle-resistor-ohms = <3000>; 223 trickle-resistor-ohms = <3000>;
225 }; 224 };
226 225
227 &snvs_pwrkey { 226 &snvs_pwrkey {
228 status = "okay"; 227 status = "okay";
229 }; 228 };
230 229
231 /* UART - RS232/RS485 */ 230 /* UART - RS232/RS485 */
232 &uart1 { 231 &uart1 {
233 assigned-clocks = <&clk IMX8MM_CLK_UAR 232 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
234 assigned-clock-parents = <&clk IMX8MM_ 233 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
235 pinctrl-names = "default"; 234 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>; 235 pinctrl-0 = <&pinctrl_uart1>;
237 uart-has-rtscts; 236 uart-has-rtscts;
238 status = "okay"; 237 status = "okay";
239 }; 238 };
240 239
241 /* UART - Sterling-LWB Bluetooth */ 240 /* UART - Sterling-LWB Bluetooth */
242 &uart2 { 241 &uart2 {
243 assigned-clocks = <&clk IMX8MM_CLK_UAR 242 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
244 assigned-clock-parents = <&clk IMX8MM_ 243 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
245 fsl,dte-mode; 244 fsl,dte-mode;
246 pinctrl-names = "default"; 245 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2_bt>; 246 pinctrl-0 = <&pinctrl_uart2_bt>;
248 uart-has-rtscts; 247 uart-has-rtscts;
249 status = "okay"; 248 status = "okay";
250 249
251 bluetooth { 250 bluetooth {
252 compatible = "brcm,bcm43438-bt 251 compatible = "brcm,bcm43438-bt";
253 clocks = <&bt_osc_32k>; 252 clocks = <&bt_osc_32k>;
254 clock-names = "lpo"; 253 clock-names = "lpo";
255 device-wakeup-gpios = <&gpio2 254 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
256 interrupt-names = "host-wakeup 255 interrupt-names = "host-wakeup";
257 interrupt-parent = <&gpio2>; 256 interrupt-parent = <&gpio2>;
258 interrupts = <9 IRQ_TYPE_EDGE_ 257 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
259 max-speed = <2000000>; 258 max-speed = <2000000>;
260 pinctrl-names = "default"; 259 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_bt>; 260 pinctrl-0 = <&pinctrl_bt>;
262 shutdown-gpios = <&gpio2 6 GPI 261 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
263 vddio-supply = <®_vcc_3v3>; 262 vddio-supply = <®_vcc_3v3>;
264 }; 263 };
265 }; 264 };
266 265
267 /* UART - console */ 266 /* UART - console */
268 &uart3 { 267 &uart3 {
269 pinctrl-names = "default"; 268 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart3>; 269 pinctrl-0 = <&pinctrl_uart3>;
271 status = "okay"; 270 status = "okay";
272 }; 271 };
273 272
274 /* USB */ 273 /* USB */
275 &usbotg1 { 274 &usbotg1 {
276 adp-disable; 275 adp-disable;
277 dr_mode = "otg"; 276 dr_mode = "otg";
278 over-current-active-low; 277 over-current-active-low;
279 samsung,picophy-pre-emp-curr-control = 278 samsung,picophy-pre-emp-curr-control = <3>;
280 samsung,picophy-dc-vol-level-adjust = 279 samsung,picophy-dc-vol-level-adjust = <7>;
281 srp-disable; 280 srp-disable;
282 vbus-supply = <®_usb_otg1_vbus>; 281 vbus-supply = <®_usb_otg1_vbus>;
283 status = "okay"; 282 status = "okay";
284 }; 283 };
285 284
286 &usbotg2 { 285 &usbotg2 {
287 disable-over-current; 286 disable-over-current;
288 dr_mode = "host"; 287 dr_mode = "host";
289 samsung,picophy-pre-emp-curr-control = 288 samsung,picophy-pre-emp-curr-control = <3>;
290 samsung,picophy-dc-vol-level-adjust = 289 samsung,picophy-dc-vol-level-adjust = <7>;
291 status = "okay"; 290 status = "okay";
292 }; 291 };
293 292
294 /* SDIO - Sterling-LWB Wifi */ 293 /* SDIO - Sterling-LWB Wifi */
295 &usdhc1 { 294 &usdhc1 {
296 assigned-clocks = <&clk IMX8MM_CLK_USD 295 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
297 assigned-clock-rates = <200000000>; 296 assigned-clock-rates = <200000000>;
298 bus-width = <4>; 297 bus-width = <4>;
299 mmc-pwrseq = <&usdhc1_pwrseq>; 298 mmc-pwrseq = <&usdhc1_pwrseq>;
300 non-removable; 299 non-removable;
301 no-1-8-v; 300 no-1-8-v;
302 pinctrl-names = "default"; 301 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct 302 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
304 #address-cells = <1>; 303 #address-cells = <1>;
305 #size-cells = <0>; 304 #size-cells = <0>;
306 status = "okay"; 305 status = "okay";
307 306
308 brcmf: wifi@1 { 307 brcmf: wifi@1 {
309 compatible = "brcm,bcm4329-fma 308 compatible = "brcm,bcm4329-fmac";
310 reg = <1>; 309 reg = <1>;
311 }; 310 };
312 }; 311 };
313 312
314 /* SD-Card */ 313 /* SD-Card */
315 &usdhc2 { 314 &usdhc2 {
316 assigned-clocks = <&clk IMX8MM_CLK_USD 315 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
317 assigned-clock-rates = <200000000>; 316 assigned-clock-rates = <200000000>;
318 bus-width = <4>; 317 bus-width = <4>;
319 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 318 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
320 disable-wp; 319 disable-wp;
321 pinctrl-names = "default", "state_100m 320 pinctrl-names = "default", "state_100mhz", "state_200mhz";
322 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
323 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 322 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
324 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 323 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
325 vmmc-supply = <®_usdhc2_vmmc>; 324 vmmc-supply = <®_usdhc2_vmmc>;
326 vqmmc-supply = <®_nvcc_sd2>; 325 vqmmc-supply = <®_nvcc_sd2>;
327 status = "okay"; 326 status = "okay";
328 }; 327 };
329 328
330 &iomuxc { 329 &iomuxc {
331 pinctrl_bt: btgrp { 330 pinctrl_bt: btgrp {
332 fsl,pins = < 331 fsl,pins = <
333 MX8MM_IOMUXC_SD1_DATA4 332 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
334 MX8MM_IOMUXC_SD1_DATA6 333 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
335 MX8MM_IOMUXC_SD1_DATA7 334 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
336 >; 335 >;
337 }; 336 };
338 337
339 pinctrl_can_en: can-engrp { 338 pinctrl_can_en: can-engrp {
340 fsl,pins = < 339 fsl,pins = <
341 MX8MM_IOMUXC_GPIO1_IO0 340 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
342 >; 341 >;
343 }; 342 };
344 343
345 pinctrl_can_int: can-intgrp { 344 pinctrl_can_int: can-intgrp {
346 fsl,pins = < 345 fsl,pins = <
347 MX8MM_IOMUXC_GPIO1_IO0 346 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
348 >; 347 >;
349 }; 348 };
350 349
351 pinctrl_ecspi1: ecspi1grp { 350 pinctrl_ecspi1: ecspi1grp {
352 fsl,pins = < 351 fsl,pins = <
353 MX8MM_IOMUXC_ECSPI1_MI 352 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
354 MX8MM_IOMUXC_ECSPI1_MO 353 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
355 MX8MM_IOMUXC_ECSPI1_SC 354 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
356 MX8MM_IOMUXC_ECSPI1_SS 355 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
357 >; 356 >;
358 }; 357 };
359 358
360 pinctrl_ecspi2: ecspi2grp { 359 pinctrl_ecspi2: ecspi2grp {
361 fsl,pins = < 360 fsl,pins = <
362 MX8MM_IOMUXC_ECSPI2_MI 361 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x80
363 MX8MM_IOMUXC_ECSPI2_MO 362 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x80
364 MX8MM_IOMUXC_ECSPI2_SC 363 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x80
365 MX8MM_IOMUXC_ECSPI2_SS 364 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
366 >; 365 >;
367 }; 366 };
368 367
369 pinctrl_fan: fan0grp { 368 pinctrl_fan: fan0grp {
370 fsl,pins = < 369 fsl,pins = <
371 MX8MM_IOMUXC_SAI1_RXD6 370 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
372 >; 371 >;
373 }; 372 };
374 373
375 pinctrl_i2c4: i2c4grp { 374 pinctrl_i2c4: i2c4grp {
376 fsl,pins = < 375 fsl,pins = <
377 MX8MM_IOMUXC_I2C4_SCL_ 376 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
378 MX8MM_IOMUXC_I2C4_SDA_ 377 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
379 >; 378 >;
380 }; 379 };
381 380
382 pinctrl_i2c4_gpio: i2c4gpiogrp { 381 pinctrl_i2c4_gpio: i2c4gpiogrp {
383 fsl,pins = < 382 fsl,pins = <
384 MX8MM_IOMUXC_I2C4_SCL_ 383 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e2
385 MX8MM_IOMUXC_I2C4_SDA_ 384 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e2
386 >; 385 >;
387 }; 386 };
388 387
389 pinctrl_leds: leds1grp { 388 pinctrl_leds: leds1grp {
390 fsl,pins = < 389 fsl,pins = <
391 MX8MM_IOMUXC_GPIO1_IO0 390 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
392 MX8MM_IOMUXC_GPIO1_IO1 391 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
393 MX8MM_IOMUXC_GPIO1_IO1 392 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
394 >; 393 >;
395 }; 394 };
396 395
397 pinctrl_pcie: pciegrp { 396 pinctrl_pcie: pciegrp {
398 fsl,pins = < 397 fsl,pins = <
399 MX8MM_IOMUXC_SAI1_RXD7 398 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
400 MX8MM_IOMUXC_SAI1_TXD0 399 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
401 MX8MM_IOMUXC_SAI1_TXD7 400 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
402 >; 401 >;
403 }; 402 };
404 403
405 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 404 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
406 fsl,pins = < 405 fsl,pins = <
407 MX8MM_IOMUXC_SD2_RESET 406 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
408 >; 407 >;
409 }; 408 };
410 409
411 pinctrl_tpm: tpmgrp { 410 pinctrl_tpm: tpmgrp {
412 fsl,pins = < 411 fsl,pins = <
413 MX8MM_IOMUXC_SD1_STROB 412 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
414 >; 413 >;
415 }; 414 };
416 415
417 pinctrl_uart1: uart1grp { 416 pinctrl_uart1: uart1grp {
418 fsl,pins = < 417 fsl,pins = <
419 MX8MM_IOMUXC_SAI2_RXC_ 418 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
420 MX8MM_IOMUXC_SAI2_RXD0 419 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
421 MX8MM_IOMUXC_SAI2_RXFS 420 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
422 MX8MM_IOMUXC_SAI2_TXFS 421 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
423 >; 422 >;
424 }; 423 };
425 424
426 pinctrl_uart2_bt: uart2btgrp { 425 pinctrl_uart2_bt: uart2btgrp {
427 fsl,pins = < 426 fsl,pins = <
428 MX8MM_IOMUXC_SAI3_RXC_ 427 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
429 MX8MM_IOMUXC_SAI3_RXD_ 428 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
430 MX8MM_IOMUXC_SAI3_TXC_ 429 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
431 MX8MM_IOMUXC_SAI3_TXFS 430 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
432 >; 431 >;
433 }; 432 };
434 433
435 pinctrl_uart3: uart3grp { 434 pinctrl_uart3: uart3grp {
436 fsl,pins = < 435 fsl,pins = <
437 MX8MM_IOMUXC_UART3_RXD 436 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
438 MX8MM_IOMUXC_UART3_TXD 437 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
439 >; 438 >;
440 }; 439 };
441 440
442 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 441 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
443 fsl,pins = < 442 fsl,pins = <
444 MX8MM_IOMUXC_GPIO1_IO1 443 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
445 >; 444 >;
446 }; 445 };
447 446
448 pinctrl_usdhc1: usdhc1grp { 447 pinctrl_usdhc1: usdhc1grp {
449 fsl,pins = < 448 fsl,pins = <
450 MX8MM_IOMUXC_SD1_CLK_U 449 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
451 MX8MM_IOMUXC_SD1_CMD_U 450 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
452 MX8MM_IOMUXC_SD1_DATA0 451 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
453 MX8MM_IOMUXC_SD1_DATA1 452 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
454 MX8MM_IOMUXC_SD1_DATA2 453 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
455 MX8MM_IOMUXC_SD1_DATA3 454 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
456 >; 455 >;
457 }; 456 };
458 457
459 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 458 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
460 fsl,pins = < 459 fsl,pins = <
461 MX8MM_IOMUXC_SD2_CD_B_ 460 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
462 >; 461 >;
463 }; 462 };
464 463
465 pinctrl_usdhc2: usdhc2grp { 464 pinctrl_usdhc2: usdhc2grp {
466 fsl,pins = < 465 fsl,pins = <
467 MX8MM_IOMUXC_GPIO1_IO0 466 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
468 MX8MM_IOMUXC_SD2_CLK_U 467 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
469 MX8MM_IOMUXC_SD2_CMD_U 468 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
470 MX8MM_IOMUXC_SD2_DATA0 469 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
471 MX8MM_IOMUXC_SD2_DATA1 470 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
472 MX8MM_IOMUXC_SD2_DATA2 471 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
473 MX8MM_IOMUXC_SD2_DATA3 472 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
474 >; 473 >;
475 }; 474 };
476 475
477 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 476 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
478 fsl,pins = < 477 fsl,pins = <
479 MX8MM_IOMUXC_GPIO1_IO0 478 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
480 MX8MM_IOMUXC_SD2_CLK_U 479 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
481 MX8MM_IOMUXC_SD2_CMD_U 480 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
482 MX8MM_IOMUXC_SD2_DATA0 481 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
483 MX8MM_IOMUXC_SD2_DATA1 482 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
484 MX8MM_IOMUXC_SD2_DATA2 483 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
485 MX8MM_IOMUXC_SD2_DATA3 484 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
486 >; 485 >;
487 }; 486 };
488 487
489 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 488 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
490 fsl,pins = < 489 fsl,pins = <
491 MX8MM_IOMUXC_GPIO1_IO0 490 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
492 MX8MM_IOMUXC_SD2_CLK_U 491 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
493 MX8MM_IOMUXC_SD2_CMD_U 492 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
494 MX8MM_IOMUXC_SD2_DATA0 493 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
495 MX8MM_IOMUXC_SD2_DATA1 494 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
496 MX8MM_IOMUXC_SD2_DATA2 495 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
497 MX8MM_IOMUXC_SD2_DATA3 496 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
498 >; 497 >;
499 }; 498 };
500 499
501 pinctrl_wlan: wlangrp { 500 pinctrl_wlan: wlangrp {
502 fsl,pins = < 501 fsl,pins = <
503 MX8MM_IOMUXC_SD1_DATA5 502 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
504 >; 503 >;
505 }; 504 };
506 }; 505 };
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