1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
4 * Author: Jens Lang <j.lang@phytec.de> 4 * Author: Jens Lang <j.lang@phytec.de>
5 * 5 *
6 * Tauri-L 2 x RS232: 6 * Tauri-L 2 x RS232:
7 * - GPIO3_20 uart4_rs485_en needs to be driv 7 * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)
8 */ 8 */
9 9
10 #include <dt-bindings/clock/imx8mm-clock.h> 10 #include <dt-bindings/clock/imx8mm-clock.h>
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include "imx8mm-pinfunc.h" 12 #include "imx8mm-pinfunc.h"
13 13
14 /dts-v1/; 14 /dts-v1/;
15 /plugin/; 15 /plugin/;
16 16
>> 17 &{/} {
>> 18 compatible = "phytec,imx8mm-phygate-tauri-l";
>> 19
>> 20 };
>> 21
17 &gpio3 { 22 &gpio3 {
18 pinctrl-names = "default"; 23 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio3_hog>; 24 pinctrl-0 = <&pinctrl_gpio3_hog>;
20 25
21 uart4-rs485-en-hog { !! 26 uart4_rs485_en {
22 gpio-hog; 27 gpio-hog;
23 gpios = <20 GPIO_ACTIVE_HIGH>; 28 gpios = <20 GPIO_ACTIVE_HIGH>;
24 output-low; 29 output-low;
25 line-name = "uart4_rs485_en"; 30 line-name = "uart4_rs485_en";
26 }; 31 };
27 }; 32 };
28 33
29 /* UART2 - RS232 */ 34 /* UART2 - RS232 */
30 &uart2 { 35 &uart2 {
31 pinctrl-names = "default"; 36 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_uart2>; 37 pinctrl-0 = <&pinctrl_uart2>;
33 assigned-clocks = <&clk IMX8MM_CLK_UAR 38 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
34 assigned-clock-parents = <&clk IMX8MM_ 39 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
35 status = "okay"; 40 status = "okay";
36 }; 41 };
37 42
38 /* UART4 - RS232 */ 43 /* UART4 - RS232 */
39 &uart4 { 44 &uart4 {
40 pinctrl-names = "default"; 45 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_uart4>; 46 pinctrl-0 = <&pinctrl_uart4>;
42 assigned-clocks = <&clk IMX8MM_CLK_UAR 47 assigned-clocks = <&clk IMX8MM_CLK_UART4>;
43 assigned-clock-parents = <&clk IMX8MM_ 48 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
44 status = "okay"; 49 status = "okay";
45 }; 50 };
46 51
47 &iomuxc { 52 &iomuxc {
48 pinctrl_gpio3_hog: gpio3hoggrp { 53 pinctrl_gpio3_hog: gpio3hoggrp {
49 fsl,pins = < 54 fsl,pins = <
50 MX8MM_IOMUXC_SAI5_RXC_ 55 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
51 >; 56 >;
52 }; 57 };
53 58
54 pinctrl_uart2: uart2grp { 59 pinctrl_uart2: uart2grp {
55 fsl,pins = < 60 fsl,pins = <
56 MX8MM_IOMUXC_UART2_RXD 61 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
57 MX8MM_IOMUXC_UART2_TXD 62 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
58 >; 63 >;
59 }; 64 };
60 65
61 pinctrl_uart4: uart4grp { 66 pinctrl_uart4: uart4grp {
62 fsl,pins = < 67 fsl,pins = <
63 MX8MM_IOMUXC_UART4_RXD 68 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
64 MX8MM_IOMUXC_UART4_TXD 69 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
65 >; 70 >;
66 }; 71 };
67 }; 72 };
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