1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Author: Jens Lang <j.lang@phytec.de> 4 * Author: Jens Lang <j.lang@phytec.de>
5 * 5 *
6 * Tauri-L RS232 with RTS/CTS hardware flow co 6 * Tauri-L RS232 with RTS/CTS hardware flow control:
7 * - UART4_TX becomes RTS 7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS 8 * - UART4_RX becomes CTS
9 */ 9 */
10 10
11 #include <dt-bindings/clock/imx8mm-clock.h> 11 #include <dt-bindings/clock/imx8mm-clock.h>
12 #include "imx8mm-pinfunc.h" 12 #include "imx8mm-pinfunc.h"
13 13
14 /dts-v1/; 14 /dts-v1/;
15 /plugin/; 15 /plugin/;
16 16
>> 17
>> 18 &{/} {
>> 19 compatible = "phytec,imx8mm-phygate-tauri-l";
>> 20
>> 21 };
>> 22
17 &uart2 { 23 &uart2 {
18 pinctrl-names = "default"; 24 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_uart2>; 25 pinctrl-0 = <&pinctrl_uart2>;
20 assigned-clocks = <&clk IMX8MM_CLK_UAR 26 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
21 assigned-clock-parents = <&clk IMX8MM_ 27 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
22 uart-has-rtscts; 28 uart-has-rtscts;
23 status = "okay"; 29 status = "okay";
24 }; 30 };
25 31
26 &iomuxc { 32 &iomuxc {
27 pinctrl_uart2: uart2grp { 33 pinctrl_uart2: uart2grp {
28 fsl,pins = < 34 fsl,pins = <
29 MX8MM_IOMUXC_UART2_RXD 35 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
30 MX8MM_IOMUXC_UART2_TXD 36 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
31 MX8MM_IOMUXC_UART4_RXD 37 MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00
32 MX8MM_IOMUXC_UART4_TXD 38 MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00
33 >; 39 >;
34 }; 40 };
35 }; 41 };
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