1 // SPDX-License-Identifier: (GPL-2.0-or-later
2 /*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9
10 #include "imx8mm-tqma8mqml.dtsi"
11 #include "mba8mx.dtsi"
12
13 / {
14 model = "TQ-Systems GmbH i.MX8MM TQMa8
15 compatible = "tq,imx8mm-tqma8mqml-mba8
16 chassis-type = "embedded";
17
18 aliases {
19 eeprom0 = &eeprom3;
20 mmc0 = &usdhc3;
21 mmc1 = &usdhc2;
22 mmc2 = &usdhc1;
23 rtc0 = &pcf85063;
24 rtc1 = &snvs_rtc;
25 };
26
27 reg_usdhc2_vmmc: regulator-vmmc {
28 compatible = "regulator-fixed"
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_usdh
31 regulator-name = "VSD_3V3";
32 regulator-min-microvolt = <330
33 regulator-max-microvolt = <330
34 gpio = <&gpio2 19 GPIO_ACTIVE_
35 enable-active-high;
36 startup-delay-us = <100>;
37 off-on-delay-us = <12000>;
38 };
39
40 connector {
41 compatible = "gpio-usb-b-conne
42 type = "micro";
43 label = "X19";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usb1_con
46 id-gpios = <&gpio1 10 GPIO_ACT
47
48 ports {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 port@0 {
53 reg = <0>;
54 usb_dr_connect
55 remote
56 };
57 };
58 };
59 };
60 };
61
62 &i2c1 {
63 expander2: gpio@27 {
64 compatible = "nxp,pca9555";
65 reg = <0x27>;
66 gpio-controller;
67 #gpio-cells = <2>;
68 vcc-supply = <®_vcc_3v3>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_expander
71 interrupt-parent = <&gpio1>;
72 interrupts = <9 IRQ_TYPE_EDGE_
73 interrupt-controller;
74 #interrupt-cells = <2>;
75 };
76 };
77
78 &pcie_phy {
79 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
80 fsl,clkreq-unsupported;
81 clocks = <&pcieclk 2>;
82 clock-names = "ref";
83 status = "okay";
84 };
85
86 /* PCIe slot on X36 */
87 &pcie0 {
88 reset-gpio = <&expander0 14 GPIO_ACTIV
89 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
90 <&clk IMX8MM_CLK_PCIE1_AUX>;
91 assigned-clocks = <&clk IMX8MM_CLK_PCI
92 <&clk IMX8MM_CLK_PCI
93 assigned-clock-rates = <10000000>, <25
94 assigned-clock-parents = <&clk IMX8MM_
95 <&clk IMX8MM_
96 status = "okay";
97 };
98
99 &sai3 {
100 assigned-clocks = <&clk IMX8MM_CLK_SAI
101 assigned-clock-parents = <&clk IMX8MM_
102 clock-names = "bus", "mclk0", "mclk1",
103 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <
104 <&clk IMX8MM_CLK_SAI3_ROOT>, <
105 <&clk IMX8MM_CLK_DUMMY>, <&clk
106 <&clk IMX8MM_AUDIO_PLL2_OUT>;
107 };
108
109 &tlv320aic3x04 {
110 clock-names = "mclk";
111 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
112 };
113
114 &uart1 {
115 assigned-clocks = <&clk IMX8MM_CLK_UAR
116 assigned-clock-parents = <&clk IMX8MM_
117 };
118
119 &uart2 {
120 assigned-clocks = <&clk IMX8MM_CLK_UAR
121 assigned-clock-parents = <&clk IMX8MM_
122 };
123
124 &usbotg1 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_usbotg1>;
127 dr_mode = "otg";
128 srp-disable;
129 hnp-disable;
130 adp-disable;
131 power-active-high;
132 over-current-active-low;
133 usb-role-switch;
134 status = "okay";
135
136 port {
137 usb1_drd_sw: endpoint {
138 remote-endpoint = <&us
139 };
140 };
141 };
142
143 &usbotg2 {
144 dr_mode = "host";
145 disable-over-current;
146 vbus-supply = <®_hub_vbus>;
147 status = "okay";
148 };
149
150 &iomuxc {
151 pinctrl_ecspi1: ecspi1grp {
152 fsl,pins = <MX8MM_IOMUXC_ECSPI
153 <MX8MM_IOMUXC_ECSPI
154 <MX8MM_IOMUXC_ECSPI
155 <MX8MM_IOMUXC_ECSPI
156 };
157
158 pinctrl_ecspi2: ecspi2grp {
159 fsl,pins = <MX8MM_IOMUXC_ECSPI
160 <MX8MM_IOMUXC_ECSPI
161 <MX8MM_IOMUXC_ECSPI
162 <MX8MM_IOMUXC_ECSPI
163 };
164
165 pinctrl_expander: expandergrp {
166 fsl,pins = <MX8MM_IOMUXC_GPIO1
167 };
168
169 pinctrl_fec1: fec1grp {
170 fsl,pins = <MX8MM_IOMUXC_ENET_
171 <MX8MM_IOMUXC_ENET_
172 <MX8MM_IOMUXC_ENET_
173 <MX8MM_IOMUXC_ENET_
174 <MX8MM_IOMUXC_ENET_
175 <MX8MM_IOMUXC_ENET_
176 <MX8MM_IOMUXC_ENET_
177 <MX8MM_IOMUXC_ENET_
178 <MX8MM_IOMUXC_ENET_
179 <MX8MM_IOMUXC_ENET_
180 <MX8MM_IOMUXC_ENET_
181 <MX8MM_IOMUXC_ENET_
182 <MX8MM_IOMUXC_ENET_
183 <MX8MM_IOMUXC_ENET_
184 };
185
186 pinctrl_gpiobutton: gpiobuttongrp {
187 fsl,pins = <MX8MM_IOMUXC_GPIO1
188 <MX8MM_IOMUXC_GPIO1
189 <MX8MM_IOMUXC_SD1_C
190 };
191
192 pinctrl_gpioled: gpioledgrp {
193 fsl,pins = <MX8MM_IOMUXC_GPIO1
194 <MX8MM_IOMUXC_NAND_
195 };
196
197 pinctrl_i2c2: i2c2grp {
198 fsl,pins = <MX8MM_IOMUXC_I2C2_
199 <MX8MM_IOMUXC_I2C2_
200 };
201
202 pinctrl_i2c2_gpio: i2c2gpiogrp {
203 fsl,pins = <MX8MM_IOMUXC_I2C2_
204 <MX8MM_IOMUXC_I2C2_
205 };
206
207 pinctrl_i2c3: i2c3grp {
208 fsl,pins = <MX8MM_IOMUXC_I2C3_
209 <MX8MM_IOMUXC_I2C3_
210 };
211
212 pinctrl_i2c3_gpio: i2c3gpiogrp {
213 fsl,pins = <MX8MM_IOMUXC_I2C3_
214 <MX8MM_IOMUXC_I2C3_
215 };
216
217 pinctrl_pwm3: pwm3grp {
218 fsl,pins = <MX8MM_IOMUXC_GPIO1
219 };
220
221 pinctrl_pwm4: pwm4grp {
222 fsl,pins = <MX8MM_IOMUXC_GPIO1
223 };
224
225 pinctrl_sai3: sai3grp {
226 fsl,pins = <MX8MM_IOMUXC_SAI3_
227 <MX8MM_IOMUXC_SAI3_
228 <MX8MM_IOMUXC_SAI3_
229 <MX8MM_IOMUXC_SAI3_
230 <MX8MM_IOMUXC_SAI3_
231 <MX8MM_IOMUXC_SAI3_
232 <MX8MM_IOMUXC_SAI3_
233 };
234
235 pinctrl_uart1: uart1grp {
236 fsl,pins = <MX8MM_IOMUXC_UART1
237 <MX8MM_IOMUXC_UART1
238 };
239
240 pinctrl_uart2: uart2grp {
241 fsl,pins = <MX8MM_IOMUXC_UART2
242 <MX8MM_IOMUXC_UART2
243 };
244
245 pinctrl_uart3: uart3grp {
246 fsl,pins = <MX8MM_IOMUXC_UART3
247 <MX8MM_IOMUXC_UART3
248 };
249
250 pinctrl_uart4: uart4grp {
251 fsl,pins = <MX8MM_IOMUXC_UART4
252 <MX8MM_IOMUXC_UART4
253 };
254
255 pinctrl_usbotg1: usbotg1grp {
256 fsl,pins = <MX8MM_IOMUXC_GPIO1
257 <MX8MM_IOMUXC_GPIO1
258 };
259
260 pinctrl_usb1_connector: usb1-connector
261 fsl,pins = <MX8MM_IOMUXC_GPIO1
262 };
263
264 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp
265 fsl,pins = <MX8MM_IOMUXC_SD2_C
266 };
267
268 pinctrl_usdhc2: usdhc2grp {
269 fsl,pins = <MX8MM_IOMUXC_SD2_C
270 <MX8MM_IOMUXC_SD2_C
271 <MX8MM_IOMUXC_SD2_D
272 <MX8MM_IOMUXC_SD2_D
273 <MX8MM_IOMUXC_SD2_D
274 <MX8MM_IOMUXC_SD2_D
275 <MX8MM_IOMUXC_GPIO1
276 };
277
278 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
279 fsl,pins = <MX8MM_IOMUXC_SD2_C
280 <MX8MM_IOMUXC_SD2_C
281 <MX8MM_IOMUXC_SD2_D
282 <MX8MM_IOMUXC_SD2_D
283 <MX8MM_IOMUXC_SD2_D
284 <MX8MM_IOMUXC_SD2_D
285 <MX8MM_IOMUXC_GPIO1
286 };
287
288 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
289 fsl,pins = <MX8MM_IOMUXC_SD2_C
290 <MX8MM_IOMUXC_SD2_C
291 <MX8MM_IOMUXC_SD2_D
292 <MX8MM_IOMUXC_SD2_D
293 <MX8MM_IOMUXC_SD2_D
294 <MX8MM_IOMUXC_SD2_D
295 <MX8MM_IOMUXC_GPIO1
296 };
297 };
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