1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 //
3 // Copyright 2018 CompuLab
4
5 /dts-v1/;
6
7 #include "imx8mm.dtsi"
8 #include <dt-bindings/leds/common.h>
9
10 / {
11 aliases {
12 rtc0 = &rtc_i2c;
13 rtc1 = &snvs_rtc;
14 mmc0 = &usdhc3;
15 };
16
17 chosen {
18 stdout-path = &uart3;
19 };
20
21 backlight {
22 compatible = "pwm-backlight";
23 pwms = <&pwm2 0 3000000 0>;
24 brightness-levels = <0 255>;
25 num-interpolated-steps = <255>
26 default-brightness-level = <22
27 status = "okay";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_led
34
35 heartbeat-led {
36 function = LED_FUNCTIO
37 gpios = <&gpio1 12 GPI
38 linux,default-trigger
39 };
40 };
41
42 pmic_osc: clock-pmic {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32768>;
46 clock-output-names = "pmic_osc
47 };
48
49 wlreg_on: regulator-wlreg-on {
50 compatible = "regulator-fixed"
51 regulator-min-microvolt = <330
52 regulator-max-microvolt = <330
53 regulator-name = "wlreg_on";
54 gpio = <&gpio2 10 GPIO_ACTIVE_
55 startup-delay-us = <100>;
56 enable-active-high;
57 regulator-always-on;
58 status = "okay";
59 };
60
61 reg_usdhc2_vmmc: regulator-usdhc2-vmmc
62 compatible = "regulator-fixed"
63 regulator-name = "VSD_3V3";
64 regulator-min-microvolt = <330
65 regulator-max-microvolt = <330
66 gpio = <&gpio2 19 GPIO_ACTIVE_
67 enable-active-high;
68 startup-delay-us = <100>;
69 off-on-delay-us = <12000>;
70 };
71
72 regulator-usdhc3rst {
73 compatible = "regulator-fixed"
74 regulator-name = "usdhc3_rst";
75 regulator-min-microvolt = <330
76 regulator-max-microvolt = <330
77 gpio = <&gpio3 16 GPIO_ACTIVE_
78 regulator-always-on;
79 enable-active-high;
80 };
81
82 regulator-fec1rst {
83 compatible = "regulator-fixed"
84 regulator-name = "fec1_rst";
85 regulator-min-microvolt = <330
86 regulator-max-microvolt = <330
87 gpio = <&gpio1 10 GPIO_ACTIVE_
88 regulator-always-on;
89 enable-active-high;
90 startup-delay-us = <500>;
91 regulator-boot-on;
92 };
93 };
94
95 &A53_0 {
96 arm-supply = <&buck2>;
97 };
98
99 &cpu_alert0 {
100 temperature = <105000>;
101 };
102
103 &cpu_crit0 {
104 temperature = <115000>;
105 };
106
107 &fec1 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_fec1>;
110 phy-mode = "rgmii-id";
111 phy-handle = <ðphy0>;
112 fsl,magic-packet;
113 status = "okay";
114
115 mdio {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 ethphy0: ethernet-phy@0 {
120 compatible = "ethernet
121 reg = <0>;
122 };
123 };
124 };
125
126 &i2c2 {
127 clock-frequency = <400000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c2>;
130 status = "okay";
131
132 pmic@4b {
133 reg = <0x4b>;
134 compatible = "rohm,bd71837";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_pmic>;
137 #clock-cells = <0>;
138 clocks = <&pmic_osc>;
139 clock-names = "osc";
140 clock-output-names = "pmic_clk
141 interrupt-parent = <&gpio1>;
142 interrupts = <3 IRQ_TYPE_LEVEL
143 rohm,reset-snvs-powered;
144
145 regulators {
146 buck1: BUCK1 {
147 regulator-name
148 regulator-min-
149 regulator-max-
150 regulator-boot
151 regulator-alwa
152 regulator-ramp
153 };
154
155 buck2: BUCK2 {
156 regulator-name
157 regulator-min-
158 regulator-max-
159 regulator-boot
160 regulator-alwa
161 regulator-ramp
162 rohm,dvs-run-v
163 rohm,dvs-idle-
164 };
165
166 buck3: BUCK3 {
167 regulator-name
168 regulator-min-
169 regulator-max-
170 regulator-boot
171 regulator-alwa
172 };
173
174 buck4: BUCK4 {
175 regulator-name
176 regulator-min-
177 regulator-max-
178 regulator-boot
179 regulator-alwa
180 };
181
182 buck5: BUCK5 {
183 regulator-name
184 regulator-min-
185 regulator-max-
186 regulator-boot
187 regulator-alwa
188 };
189
190 buck6: BUCK6 {
191 regulator-name
192 regulator-min-
193 regulator-max-
194 regulator-boot
195 regulator-alwa
196 };
197
198 buck7: BUCK7 {
199 regulator-name
200 regulator-min-
201 regulator-max-
202 regulator-boot
203 regulator-alwa
204 };
205
206 buck8: BUCK8 {
207 regulator-name
208 regulator-min-
209 regulator-max-
210 regulator-boot
211 regulator-alwa
212 };
213
214 ldo1: LDO1 {
215 regulator-name
216 regulator-min-
217 regulator-max-
218 regulator-boot
219 regulator-alwa
220 };
221
222 ldo2: LDO2 {
223 regulator-name
224 regulator-min-
225 regulator-max-
226 regulator-boot
227 regulator-alwa
228 };
229
230 ldo3: LDO3 {
231 regulator-name
232 regulator-min-
233 regulator-max-
234 regulator-boot
235 regulator-alwa
236 };
237
238 ldo4: LDO4 {
239 regulator-name
240 regulator-min-
241 regulator-max-
242 regulator-boot
243 regulator-alwa
244 };
245
246 ldo5: LDO5 {
247 regulator-name
248 regulator-min-
249 regulator-max-
250 };
251
252 ldo6: LDO6 {
253 regulator-name
254 regulator-min-
255 regulator-max-
256 regulator-boot
257 regulator-alwa
258 };
259
260 ldo7: LDO7 {
261 regulator-name
262 regulator-min-
263 regulator-max-
264 };
265 };
266 };
267
268 eeprom@50 {
269 compatible = "atmel,24c08";
270 reg = <0x50>;
271 pagesize = <16>;
272 };
273
274 rtc_i2c: rtc@69 {
275 compatible = "abracon,ab1805";
276 reg = <0x69>;
277 };
278 };
279
280 &i2c3 {
281 clock-frequency = <100000>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_i2c3>;
284 status = "disabled";
285 };
286
287 &pwm2 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_pwm_backlight>;
290 status = "okay";
291 };
292
293 &sai2 {
294 #sound-dai-cells = <0>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_sai2>;
297 assigned-clocks = <&clk IMX8MM_CLK_SAI
298 assigned-clock-parents = <&clk IMX8MM_
299 assigned-clock-rates = <49152000>;
300 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <
301 <&clk IMX8MM_CLK_SAI2_ROOT>, <
302 <&clk IMX8MM_CLK_DUMMY>, <&clk
303 <&clk IMX8MM_AUDIO_PLL2_OUT>;
304 clock-names = "bus", "mclk0", "mclk1",
305 fsl,sai-asynchronous;
306 status = "okay";
307 };
308
309 &snvs {
310 status = "okay";
311 };
312
313 &snvs_pwrkey {
314 status = "okay";
315 };
316
317 &uart1 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_uart1>;
320 assigned-clocks = <&clk IMX8MM_CLK_UAR
321 assigned-clock-parents = <&clk IMX8MM_
322 status = "disabled";
323 };
324
325 &uart2 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_uart2>;
328 assigned-clocks = <&clk IMX8MM_CLK_UAR
329 assigned-clock-parents = <&clk IMX8MM_
330 status = "disabled";
331 };
332
333 &uart3 { /* console */
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_uart3>;
336 status = "okay";
337 };
338
339 &uart4 { /* bluetooth */
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_uart4>;
342 assigned-clocks = <&clk IMX8MM_CLK_UAR
343 assigned-clock-parents = <&clk IMX8MM_
344 uart-has-rtscts;
345 status = "disabled";
346
347 bluetooth {
348 compatible = "brcm,bcm4330-bt"
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_bt>;
351 max-speed = <3000000>;
352 device-wakeup-gpios = <&gpio2
353 host-wakeup-gpios = <&gpio2 8
354 shutdown-gpios = <&gpio2 6 GPI
355 };
356 };
357
358 &usbotg1 {
359 dr_mode = "otg";
360 hnp-disable;
361 srp-disable;
362 disable-over-current;
363 status = "disabled";
364 };
365
366 &usbotg2 {
367 dr_mode = "host";
368 hnp-disable;
369 srp-disable;
370 disable-over-current;
371 status = "disabled";
372 };
373
374 &usdhc1 {
375 pinctrl-names = "default", "state_100m
376 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct
377 pinctrl-1 = <&pinctrl_usdhc1_100mhz>,
378 pinctrl-2 = <&pinctrl_usdhc1_200mhz>,
379 bus-width = <4>;
380 non-removable;
381 };
382
383 &usdhc2 {
384 pinctrl-names = "default", "state_100m
385 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
386 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
387 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
388 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
389 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH
390 no-1-8-v;
391 bus-width = <4>;
392 vmmc-supply = <®_usdhc2_vmmc>;
393 status = "okay";
394 };
395
396 &usdhc3 {
397 pinctrl-names = "default", "state_100m
398 pinctrl-0 = <&pinctrl_usdhc3>;
399 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
400 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
401 bus-width = <8>;
402 non-removable;
403 no-1-8-v;
404 status = "okay";
405 };
406
407 &wdog1 {
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_wdog>;
410 fsl,ext-reset-output;
411 status = "okay";
412 };
413
414 &iomuxc {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_hog_1>;
417
418 pinctrl_hog: hoggrp {
419 fsl,pins = <
420 MX8MM_IOMUXC_GPIO1_IO1
421 MX8MM_IOMUXC_NAND_READ
422 >;
423 };
424
425 pinctrl_bt: bt0grp {
426 fsl,pins = <
427 MX8MM_IOMUXC_SD1_DATA4
428 MX8MM_IOMUXC_SD1_DATA5
429 MX8MM_IOMUXC_SD1_DATA6
430 >;
431 };
432
433 pinctrl_fec1: fec1grp {
434 fsl,pins = <
435 MX8MM_IOMUXC_ENET_MDC_
436 MX8MM_IOMUXC_ENET_MDIO
437 MX8MM_IOMUXC_ENET_TD3_
438 MX8MM_IOMUXC_ENET_TD2_
439 MX8MM_IOMUXC_ENET_TD1_
440 MX8MM_IOMUXC_ENET_TD0_
441 MX8MM_IOMUXC_ENET_RD3_
442 MX8MM_IOMUXC_ENET_RD2_
443 MX8MM_IOMUXC_ENET_RD1_
444 MX8MM_IOMUXC_ENET_RD0_
445 MX8MM_IOMUXC_ENET_TXC_
446 MX8MM_IOMUXC_ENET_RXC_
447 MX8MM_IOMUXC_ENET_RX_C
448 MX8MM_IOMUXC_ENET_TX_C
449 >;
450 };
451
452 pinctrl_gpio_led: gpioledgrp {
453 fsl,pins = <
454 MX8MM_IOMUXC_GPIO1_IO1
455 >;
456 };
457
458 pinctrl_i2c1: i2c1grp {
459 fsl,pins = <
460 MX8MM_IOMUXC_I2C1_SCL_
461 MX8MM_IOMUXC_I2C1_SDA_
462 >;
463 };
464
465 pinctrl_i2c2: i2c2grp {
466 fsl,pins = <
467 MX8MM_IOMUXC_I2C2_SCL_
468 MX8MM_IOMUXC_I2C2_SDA_
469 >;
470 };
471
472 pinctrl_i2c3: i2c3grp {
473 fsl,pins = <
474 MX8MM_IOMUXC_I2C3_SCL_
475 MX8MM_IOMUXC_I2C3_SDA_
476 >;
477 };
478
479 pinctrl_i2c4: i2c4grp {
480 fsl,pins = <
481 MX8MM_IOMUXC_I2C4_SCL_
482 MX8MM_IOMUXC_I2C4_SDA_
483 >;
484 };
485
486 pinctrl_pmic: pmicgrp {
487 fsl,pins = <
488 MX8MM_IOMUXC_GPIO1_IO0
489 >;
490 };
491
492 pinctrl_pwm_backlight: pwmbacklightgrp
493 fsl,pins = <
494 MX8MM_IOMUXC_GPIO1_IO1
495 >;
496 };
497
498
499 pinctrl_sai2: sai2grp {
500 fsl,pins = <
501 MX8MM_IOMUXC_SAI2_MCLK
502 MX8MM_IOMUXC_SAI2_TXFS
503 MX8MM_IOMUXC_SAI2_RXFS
504 MX8MM_IOMUXC_SAI2_TXC_
505 MX8MM_IOMUXC_SAI2_TXD0
506 MX8MM_IOMUXC_SAI2_RXD0
507 >;
508 };
509
510 pinctrl_uart1: uart1grp {
511 fsl,pins = <
512 MX8MM_IOMUXC_UART1_RXD
513 MX8MM_IOMUXC_UART1_TXD
514 >;
515 };
516
517 pinctrl_uart2: uart2grp {
518 fsl,pins = <
519 MX8MM_IOMUXC_UART2_RXD
520 MX8MM_IOMUXC_UART2_TXD
521 >;
522 };
523
524 pinctrl_uart3: uart3grp {
525 fsl,pins = <
526 MX8MM_IOMUXC_UART3_RXD
527 MX8MM_IOMUXC_UART3_TXD
528 >;
529 };
530
531 pinctrl_uart4: uart4grp {
532 fsl,pins = <
533 MX8MM_IOMUXC_ECSPI2_MI
534 MX8MM_IOMUXC_ECSPI2_MO
535 MX8MM_IOMUXC_ECSPI2_SS
536 MX8MM_IOMUXC_ECSPI2_SC
537 >;
538 };
539
540 pinctrl_usdhc1_gpio: usdhc1grpgpiogrp
541 fsl,pins = <
542 MX8MM_IOMUXC_SD1_RESET
543 >;
544 };
545
546 pinctrl_usdhc1: usdhc1grp {
547 fsl,pins = <
548 MX8MM_IOMUXC_SD1_CLK_U
549 MX8MM_IOMUXC_SD1_CMD_U
550 MX8MM_IOMUXC_SD1_DATA0
551 MX8MM_IOMUXC_SD1_DATA1
552 MX8MM_IOMUXC_SD1_DATA2
553 MX8MM_IOMUXC_SD1_DATA3
554 MX8MM_IOMUXC_GPIO1_IO0
555 >;
556 };
557
558 pinctrl_usdhc1_100mhz: usdhc1grp100mhz
559 fsl,pins = <
560 MX8MM_IOMUXC_SD1_CLK_U
561 MX8MM_IOMUXC_SD1_CMD_U
562 MX8MM_IOMUXC_SD1_DATA0
563 MX8MM_IOMUXC_SD1_DATA1
564 MX8MM_IOMUXC_SD1_DATA2
565 MX8MM_IOMUXC_SD1_DATA3
566 MX8MM_IOMUXC_GPIO1_IO0
567 >;
568 };
569
570 pinctrl_usdhc1_200mhz: usdhc1grp200mhz
571 fsl,pins = <
572 MX8MM_IOMUXC_SD1_CLK_U
573 MX8MM_IOMUXC_SD1_CMD_U
574 MX8MM_IOMUXC_SD1_DATA0
575 MX8MM_IOMUXC_SD1_DATA1
576 MX8MM_IOMUXC_SD1_DATA2
577 MX8MM_IOMUXC_SD1_DATA3
578 MX8MM_IOMUXC_GPIO1_IO0
579 >;
580 };
581
582 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp
583 fsl,pins = <
584 MX8MM_IOMUXC_SD2_RESET
585 MX8MM_IOMUXC_SD2_CD_B_
586 MX8MM_IOMUXC_SD2_WP_GP
587 >;
588 };
589
590 pinctrl_usdhc2: usdhc2grp {
591 fsl,pins = <
592 MX8MM_IOMUXC_SD2_CLK_U
593 MX8MM_IOMUXC_SD2_CMD_U
594 MX8MM_IOMUXC_SD2_DATA0
595 MX8MM_IOMUXC_SD2_DATA1
596 MX8MM_IOMUXC_SD2_DATA2
597 MX8MM_IOMUXC_SD2_DATA3
598 MX8MM_IOMUXC_GPIO1_IO0
599 >;
600 };
601
602 pinctrl_usdhc2_100mhz: usdhc2grp100mhz
603 fsl,pins = <
604 MX8MM_IOMUXC_SD2_CLK_U
605 MX8MM_IOMUXC_SD2_CMD_U
606 MX8MM_IOMUXC_SD2_DATA0
607 MX8MM_IOMUXC_SD2_DATA1
608 MX8MM_IOMUXC_SD2_DATA2
609 MX8MM_IOMUXC_SD2_DATA3
610 MX8MM_IOMUXC_GPIO1_IO0
611 >;
612 };
613
614 pinctrl_usdhc2_200mhz: usdhc2grp200mhz
615 fsl,pins = <
616 MX8MM_IOMUXC_SD2_CLK_U
617 MX8MM_IOMUXC_SD2_CMD_U
618 MX8MM_IOMUXC_SD2_DATA0
619 MX8MM_IOMUXC_SD2_DATA1
620 MX8MM_IOMUXC_SD2_DATA2
621 MX8MM_IOMUXC_SD2_DATA3
622 MX8MM_IOMUXC_GPIO1_IO0
623 >;
624 };
625
626 pinctrl_usdhc3: usdhc3grp {
627 fsl,pins = <
628 MX8MM_IOMUXC_NAND_WE_B
629 MX8MM_IOMUXC_NAND_WP_B
630 MX8MM_IOMUXC_NAND_DATA
631 MX8MM_IOMUXC_NAND_DATA
632 MX8MM_IOMUXC_NAND_DATA
633 MX8MM_IOMUXC_NAND_DATA
634 MX8MM_IOMUXC_NAND_RE_B
635 MX8MM_IOMUXC_NAND_CE2_
636 MX8MM_IOMUXC_NAND_CE3_
637 MX8MM_IOMUXC_NAND_CLE_
638 MX8MM_IOMUXC_NAND_CE1_
639 >;
640 };
641
642 pinctrl_usdhc3_100mhz: usdhc3grp100mhz
643 fsl,pins = <
644 MX8MM_IOMUXC_NAND_WE_B
645 MX8MM_IOMUXC_NAND_WP_B
646 MX8MM_IOMUXC_NAND_DATA
647 MX8MM_IOMUXC_NAND_DATA
648 MX8MM_IOMUXC_NAND_DATA
649 MX8MM_IOMUXC_NAND_DATA
650 MX8MM_IOMUXC_NAND_RE_B
651 MX8MM_IOMUXC_NAND_CE2_
652 MX8MM_IOMUXC_NAND_CE3_
653 MX8MM_IOMUXC_NAND_CLE_
654 MX8MM_IOMUXC_NAND_CE1_
655 >;
656 };
657
658 pinctrl_usdhc3_200mhz: usdhc3grp200mhz
659 fsl,pins = <
660 MX8MM_IOMUXC_NAND_WE_B
661 MX8MM_IOMUXC_NAND_WP_B
662 MX8MM_IOMUXC_NAND_DATA
663 MX8MM_IOMUXC_NAND_DATA
664 MX8MM_IOMUXC_NAND_DATA
665 MX8MM_IOMUXC_NAND_DATA
666 MX8MM_IOMUXC_NAND_RE_B
667 MX8MM_IOMUXC_NAND_CE2_
668 MX8MM_IOMUXC_NAND_CE3_
669 MX8MM_IOMUXC_NAND_CLE_
670 MX8MM_IOMUXC_NAND_CE1_
671 >;
672 };
673
674 pinctrl_wdog: wdoggrp {
675 fsl,pins = <
676 MX8MM_IOMUXC_GPIO1_IO0
677 >;
678 };
679 };
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