1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk 4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
5 */ 5 */
6 6
7 #include "imx8mm.dtsi" 7 #include "imx8mm.dtsi"
8 8
9 / { 9 / {
10 model = "Variscite VAR-SOM-MX8MM modul 10 model = "Variscite VAR-SOM-MX8MM module";
>> 11 compatible = "variscite,var-som-mx8mm", "fsl,imx8mm";
11 12
12 chosen { 13 chosen {
13 stdout-path = &uart4; 14 stdout-path = &uart4;
14 }; 15 };
15 16
16 memory@40000000 { 17 memory@40000000 {
17 device_type = "memory"; 18 device_type = "memory";
18 reg = <0x0 0x40000000 0 0x8000 19 reg = <0x0 0x40000000 0 0x80000000>;
19 }; 20 };
20 21
21 reg_eth_phy: regulator-eth-phy { 22 reg_eth_phy: regulator-eth-phy {
22 compatible = "regulator-fixed" 23 compatible = "regulator-fixed";
23 pinctrl-names = "default"; 24 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_reg_eth_ 25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
25 regulator-name = "eth_phy_pwr" 26 regulator-name = "eth_phy_pwr";
26 regulator-min-microvolt = <330 27 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <330 28 regulator-max-microvolt = <3300000>;
28 gpio = <&gpio2 9 GPIO_ACTIVE_H 29 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
29 enable-active-high; 30 enable-active-high;
30 }; 31 };
31 }; 32 };
32 33
33 &A53_0 { 34 &A53_0 {
34 cpu-supply = <&buck2_reg>; 35 cpu-supply = <&buck2_reg>;
35 }; 36 };
36 37
37 &A53_1 { 38 &A53_1 {
38 cpu-supply = <&buck2_reg>; 39 cpu-supply = <&buck2_reg>;
39 }; 40 };
40 41
41 &A53_2 { 42 &A53_2 {
42 cpu-supply = <&buck2_reg>; 43 cpu-supply = <&buck2_reg>;
43 }; 44 };
44 45
45 &A53_3 { 46 &A53_3 {
46 cpu-supply = <&buck2_reg>; 47 cpu-supply = <&buck2_reg>;
47 }; 48 };
48 49
49 &ddrc { 50 &ddrc {
50 operating-points-v2 = <&ddrc_opp_table 51 operating-points-v2 = <&ddrc_opp_table>;
51 52
52 ddrc_opp_table: opp-table { 53 ddrc_opp_table: opp-table {
53 compatible = "operating-points 54 compatible = "operating-points-v2";
54 55
55 opp-25000000 { !! 56 opp-25M {
56 opp-hz = /bits/ 64 <25 57 opp-hz = /bits/ 64 <25000000>;
57 }; 58 };
58 59
59 opp-100000000 { !! 60 opp-100M {
60 opp-hz = /bits/ 64 <10 61 opp-hz = /bits/ 64 <100000000>;
61 }; 62 };
62 63
63 opp-750000000 { !! 64 opp-750M {
64 opp-hz = /bits/ 64 <75 65 opp-hz = /bits/ 64 <750000000>;
65 }; 66 };
66 }; 67 };
67 }; 68 };
68 69
69 &ecspi1 { 70 &ecspi1 {
70 pinctrl-names = "default"; 71 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ecspi1>; 72 pinctrl-0 = <&pinctrl_ecspi1>;
72 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW> 73 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
73 <&gpio1 0 GPIO_ACTIVE_LOW> 74 <&gpio1 0 GPIO_ACTIVE_LOW>;
74 /delete-property/ dmas; 75 /delete-property/ dmas;
75 /delete-property/ dma-names; 76 /delete-property/ dma-names;
76 status = "okay"; 77 status = "okay";
77 78
78 /* Resistive touch controller */ 79 /* Resistive touch controller */
79 touchscreen@0 { 80 touchscreen@0 {
80 reg = <0>; 81 reg = <0>;
81 compatible = "ti,ads7846"; 82 compatible = "ti,ads7846";
82 pinctrl-names = "default"; 83 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_restouch 84 pinctrl-0 = <&pinctrl_restouch>;
84 interrupt-parent = <&gpio1>; 85 interrupt-parent = <&gpio1>;
85 interrupts = <3 IRQ_TYPE_EDGE_ 86 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
86 87
87 spi-max-frequency = <1500000>; 88 spi-max-frequency = <1500000>;
88 pendown-gpio = <&gpio1 3 GPIO_ 89 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
89 90
90 ti,x-min = /bits/ 16 <125>; 91 ti,x-min = /bits/ 16 <125>;
91 touchscreen-size-x = <4008>; 92 touchscreen-size-x = <4008>;
92 ti,y-min = /bits/ 16 <282>; 93 ti,y-min = /bits/ 16 <282>;
93 touchscreen-size-y = <3864>; 94 touchscreen-size-y = <3864>;
94 ti,x-plate-ohms = /bits/ 16 <1 95 ti,x-plate-ohms = /bits/ 16 <180>;
95 touchscreen-max-pressure = <25 96 touchscreen-max-pressure = <255>;
96 touchscreen-average-samples = 97 touchscreen-average-samples = <10>;
97 ti,debounce-tol = /bits/ 16 <3 98 ti,debounce-tol = /bits/ 16 <3>;
98 ti,debounce-rep = /bits/ 16 <1 99 ti,debounce-rep = /bits/ 16 <1>;
99 ti,settle-delay-usec = /bits/ 100 ti,settle-delay-usec = /bits/ 16 <150>;
100 ti,keep-vref-on; 101 ti,keep-vref-on;
101 wakeup-source; 102 wakeup-source;
102 }; 103 };
103 }; 104 };
104 105
105 &fec1 { 106 &fec1 {
106 pinctrl-names = "default"; 107 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_fec1>; 108 pinctrl-0 = <&pinctrl_fec1>;
108 phy-mode = "rgmii"; 109 phy-mode = "rgmii";
109 phy-handle = <ðphy>; 110 phy-handle = <ðphy>;
110 phy-supply = <®_eth_phy>; 111 phy-supply = <®_eth_phy>;
111 fsl,magic-packet; 112 fsl,magic-packet;
112 status = "okay"; 113 status = "okay";
113 114
114 mdio { 115 mdio {
115 #address-cells = <1>; 116 #address-cells = <1>;
116 #size-cells = <0>; 117 #size-cells = <0>;
117 118
118 ethphy: ethernet-phy@4 { 119 ethphy: ethernet-phy@4 {
119 compatible = "ethernet 120 compatible = "ethernet-phy-ieee802.3-c22";
120 reg = <4>; 121 reg = <4>;
121 reset-gpios = <&gpio1 122 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
122 reset-assert-us = <100 123 reset-assert-us = <10000>;
123 reset-deassert-us = <1 124 reset-deassert-us = <10000>;
124 }; 125 };
125 }; 126 };
126 }; 127 };
127 128
128 &i2c1 { 129 &i2c1 {
129 clock-frequency = <400000>; 130 clock-frequency = <400000>;
130 pinctrl-names = "default"; 131 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_i2c1>; 132 pinctrl-0 = <&pinctrl_i2c1>;
132 status = "okay"; 133 status = "okay";
133 134
134 pmic@4b { 135 pmic@4b {
135 compatible = "rohm,bd71847"; 136 compatible = "rohm,bd71847";
136 reg = <0x4b>; 137 reg = <0x4b>;
137 pinctrl-names = "default"; 138 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_pmic>; 139 pinctrl-0 = <&pinctrl_pmic>;
139 interrupt-parent = <&gpio2>; 140 interrupt-parent = <&gpio2>;
140 interrupts = <8 IRQ_TYPE_LEVEL 141 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
141 rohm,reset-snvs-powered; 142 rohm,reset-snvs-powered;
142 143
143 #clock-cells = <0>; 144 #clock-cells = <0>;
144 clocks = <&osc_32k>; !! 145 clocks = <&osc_32k 0>;
145 clock-output-names = "clk-32k- 146 clock-output-names = "clk-32k-out";
146 147
147 regulators { 148 regulators {
148 buck1_reg: BUCK1 { 149 buck1_reg: BUCK1 {
149 regulator-name 150 regulator-name = "buck1";
150 regulator-min- 151 regulator-min-microvolt = <700000>;
151 regulator-max- 152 regulator-max-microvolt = <1300000>;
152 regulator-boot 153 regulator-boot-on;
153 regulator-alwa 154 regulator-always-on;
154 regulator-ramp 155 regulator-ramp-delay = <1250>;
155 }; 156 };
156 157
157 buck2_reg: BUCK2 { 158 buck2_reg: BUCK2 {
158 regulator-name 159 regulator-name = "buck2";
159 regulator-min- 160 regulator-min-microvolt = <700000>;
160 regulator-max- 161 regulator-max-microvolt = <1300000>;
161 regulator-boot 162 regulator-boot-on;
162 regulator-alwa 163 regulator-always-on;
163 regulator-ramp 164 regulator-ramp-delay = <1250>;
164 rohm,dvs-run-v 165 rohm,dvs-run-voltage = <1000000>;
165 rohm,dvs-idle- 166 rohm,dvs-idle-voltage = <900000>;
166 }; 167 };
167 168
168 buck3_reg: BUCK3 { 169 buck3_reg: BUCK3 {
169 regulator-name 170 regulator-name = "buck3";
170 regulator-min- 171 regulator-min-microvolt = <700000>;
171 regulator-max- 172 regulator-max-microvolt = <1350000>;
172 regulator-boot 173 regulator-boot-on;
173 regulator-alwa 174 regulator-always-on;
174 }; 175 };
175 176
176 buck4_reg: BUCK4 { 177 buck4_reg: BUCK4 {
177 regulator-name 178 regulator-name = "buck4";
178 regulator-min- 179 regulator-min-microvolt = <3000000>;
179 regulator-max- 180 regulator-max-microvolt = <3300000>;
180 regulator-boot 181 regulator-boot-on;
181 regulator-alwa 182 regulator-always-on;
182 }; 183 };
183 184
184 buck5_reg: BUCK5 { 185 buck5_reg: BUCK5 {
185 regulator-name 186 regulator-name = "buck5";
186 regulator-min- 187 regulator-min-microvolt = <1605000>;
187 regulator-max- 188 regulator-max-microvolt = <1995000>;
188 regulator-boot 189 regulator-boot-on;
189 regulator-alwa 190 regulator-always-on;
190 }; 191 };
191 192
192 buck6_reg: BUCK6 { 193 buck6_reg: BUCK6 {
193 regulator-name 194 regulator-name = "buck6";
194 regulator-min- 195 regulator-min-microvolt = <800000>;
195 regulator-max- 196 regulator-max-microvolt = <1400000>;
196 regulator-boot 197 regulator-boot-on;
197 regulator-alwa 198 regulator-always-on;
198 }; 199 };
199 200
200 ldo1_reg: LDO1 { 201 ldo1_reg: LDO1 {
201 regulator-name 202 regulator-name = "ldo1";
202 regulator-min- 203 regulator-min-microvolt = <1600000>;
203 regulator-max- 204 regulator-max-microvolt = <1900000>;
204 regulator-boot 205 regulator-boot-on;
205 regulator-alwa 206 regulator-always-on;
206 }; 207 };
207 208
208 ldo2_reg: LDO2 { 209 ldo2_reg: LDO2 {
209 regulator-name 210 regulator-name = "ldo2";
210 regulator-min- 211 regulator-min-microvolt = <800000>;
211 regulator-max- 212 regulator-max-microvolt = <900000>;
212 regulator-boot 213 regulator-boot-on;
213 regulator-alwa 214 regulator-always-on;
214 }; 215 };
215 216
216 ldo3_reg: LDO3 { 217 ldo3_reg: LDO3 {
217 regulator-name 218 regulator-name = "ldo3";
218 regulator-min- 219 regulator-min-microvolt = <1800000>;
219 regulator-max- 220 regulator-max-microvolt = <3300000>;
220 regulator-boot 221 regulator-boot-on;
221 regulator-alwa 222 regulator-always-on;
222 }; 223 };
223 224
224 ldo4_reg: LDO4 { 225 ldo4_reg: LDO4 {
225 regulator-name 226 regulator-name = "ldo4";
226 regulator-min- 227 regulator-min-microvolt = <900000>;
227 regulator-max- 228 regulator-max-microvolt = <1800000>;
228 regulator-boot 229 regulator-boot-on;
229 regulator-alwa 230 regulator-always-on;
230 }; 231 };
231 232
232 ldo5_reg: LDO5 { 233 ldo5_reg: LDO5 {
>> 234 regulator-compatible = "ldo5";
233 regulator-min- 235 regulator-min-microvolt = <1800000>;
234 regulator-max- 236 regulator-max-microvolt = <1800000>;
235 regulator-alwa 237 regulator-always-on;
236 }; 238 };
237 239
238 ldo6_reg: LDO6 { 240 ldo6_reg: LDO6 {
239 regulator-name 241 regulator-name = "ldo6";
240 regulator-min- 242 regulator-min-microvolt = <900000>;
241 regulator-max- 243 regulator-max-microvolt = <1800000>;
242 regulator-boot 244 regulator-boot-on;
243 regulator-alwa 245 regulator-always-on;
244 }; 246 };
245 }; 247 };
246 }; 248 };
247 }; 249 };
248 250
249 &i2c3 { 251 &i2c3 {
250 clock-frequency = <400000>; 252 clock-frequency = <400000>;
251 pinctrl-names = "default"; 253 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>; 254 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay"; 255 status = "okay";
254 256
255 /* TODO: configure audio, as of now ju 257 /* TODO: configure audio, as of now just put a placeholder */
256 wm8904: codec@1a { 258 wm8904: codec@1a {
257 compatible = "wlf,wm8904"; 259 compatible = "wlf,wm8904";
258 reg = <0x1a>; 260 reg = <0x1a>;
259 status = "disabled"; 261 status = "disabled";
260 }; 262 };
261 }; 263 };
262 264
263 &snvs_pwrkey { 265 &snvs_pwrkey {
264 status = "okay"; 266 status = "okay";
265 }; 267 };
266 268
267 /* Bluetooth */ 269 /* Bluetooth */
268 &uart2 { 270 &uart2 {
269 pinctrl-names = "default"; 271 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>; 272 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MM_CLK_UAR 273 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
272 assigned-clock-parents = <&clk IMX8MM_ 274 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
273 uart-has-rtscts; 275 uart-has-rtscts;
274 status = "okay"; 276 status = "okay";
275 }; 277 };
276 278
277 /* Console */ 279 /* Console */
278 &uart4 { 280 &uart4 {
279 pinctrl-names = "default"; 281 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>; 282 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay"; 283 status = "okay";
282 }; 284 };
283 285
284 &usbotg1 { 286 &usbotg1 {
285 dr_mode = "otg"; 287 dr_mode = "otg";
286 usb-role-switch; 288 usb-role-switch;
287 status = "okay"; 289 status = "okay";
288 }; 290 };
289 291
290 &usbotg2 { 292 &usbotg2 {
291 dr_mode = "otg"; 293 dr_mode = "otg";
292 usb-role-switch; 294 usb-role-switch;
293 status = "okay"; 295 status = "okay";
294 }; 296 };
295 297
296 /* WIFI */ 298 /* WIFI */
297 &usdhc1 { 299 &usdhc1 {
298 #address-cells = <1>; 300 #address-cells = <1>;
299 #size-cells = <0>; 301 #size-cells = <0>;
300 pinctrl-names = "default", "state_100m 302 pinctrl-names = "default", "state_100mhz", "state_200mhz";
301 pinctrl-0 = <&pinctrl_usdhc1>; 303 pinctrl-0 = <&pinctrl_usdhc1>;
302 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 304 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
303 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 305 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
304 bus-width = <4>; 306 bus-width = <4>;
305 non-removable; 307 non-removable;
306 keep-power-in-suspend; 308 keep-power-in-suspend;
307 status = "okay"; 309 status = "okay";
308 310
309 brcmf: bcrmf@1 { 311 brcmf: bcrmf@1 {
310 reg = <1>; 312 reg = <1>;
311 compatible = "brcm,bcm4329-fma 313 compatible = "brcm,bcm4329-fmac";
312 }; 314 };
313 }; 315 };
314 316
315 /* SD */ 317 /* SD */
316 &usdhc2 { 318 &usdhc2 {
317 assigned-clocks = <&clk IMX8MM_CLK_USD 319 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
318 assigned-clock-rates = <200000000>; 320 assigned-clock-rates = <200000000>;
319 pinctrl-names = "default", "state_100m 321 pinctrl-names = "default", "state_100mhz", "state_200mhz";
320 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 322 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
321 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 323 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
322 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 324 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
323 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> 325 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
324 bus-width = <4>; 326 bus-width = <4>;
325 vmmc-supply = <®_usdhc2_vmmc>; 327 vmmc-supply = <®_usdhc2_vmmc>;
326 status = "okay"; 328 status = "okay";
327 }; 329 };
328 330
329 /* eMMC */ 331 /* eMMC */
330 &usdhc3 { 332 &usdhc3 {
331 assigned-clocks = <&clk IMX8MM_CLK_USD 333 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
332 assigned-clock-rates = <400000000>; 334 assigned-clock-rates = <400000000>;
333 pinctrl-names = "default", "state_100m 335 pinctrl-names = "default", "state_100mhz", "state_200mhz";
334 pinctrl-0 = <&pinctrl_usdhc3>; 336 pinctrl-0 = <&pinctrl_usdhc3>;
335 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 337 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
336 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 338 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
337 bus-width = <8>; 339 bus-width = <8>;
338 non-removable; 340 non-removable;
339 status = "okay"; 341 status = "okay";
340 }; 342 };
341 343
342 &wdog1 { 344 &wdog1 {
343 pinctrl-names = "default"; 345 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_wdog>; 346 pinctrl-0 = <&pinctrl_wdog>;
345 fsl,ext-reset-output; 347 fsl,ext-reset-output;
346 status = "okay"; 348 status = "okay";
347 }; 349 };
348 350
349 &iomuxc { 351 &iomuxc {
350 pinctrl_ecspi1: ecspi1grp { 352 pinctrl_ecspi1: ecspi1grp {
351 fsl,pins = < 353 fsl,pins = <
352 MX8MM_IOMUXC_ECSPI1_SC 354 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
353 MX8MM_IOMUXC_ECSPI1_MO 355 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
354 MX8MM_IOMUXC_ECSPI1_MI 356 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
355 MX8MM_IOMUXC_GPIO1_IO1 357 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
356 MX8MM_IOMUXC_GPIO1_IO0 358 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
357 >; 359 >;
358 }; 360 };
359 361
360 pinctrl_fec1: fec1grp { 362 pinctrl_fec1: fec1grp {
361 fsl,pins = < 363 fsl,pins = <
362 MX8MM_IOMUXC_ENET_MDC_ 364 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
363 MX8MM_IOMUXC_ENET_MDIO 365 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
364 MX8MM_IOMUXC_ENET_TD3_ 366 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
365 MX8MM_IOMUXC_ENET_TD2_ 367 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
366 MX8MM_IOMUXC_ENET_TD1_ 368 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
367 MX8MM_IOMUXC_ENET_TD0_ 369 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
368 MX8MM_IOMUXC_ENET_RD3_ 370 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
369 MX8MM_IOMUXC_ENET_RD2_ 371 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
370 MX8MM_IOMUXC_ENET_RD1_ 372 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
371 MX8MM_IOMUXC_ENET_RD0_ 373 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
372 MX8MM_IOMUXC_ENET_TXC_ 374 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
373 MX8MM_IOMUXC_ENET_RXC_ 375 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
374 MX8MM_IOMUXC_ENET_RX_C 376 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
375 MX8MM_IOMUXC_ENET_TX_C 377 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
376 MX8MM_IOMUXC_GPIO1_IO0 378 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
377 >; 379 >;
378 }; 380 };
379 381
380 pinctrl_i2c1: i2c1grp { 382 pinctrl_i2c1: i2c1grp {
381 fsl,pins = < 383 fsl,pins = <
382 MX8MM_IOMUXC_I2C1_SCL_ 384 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
383 MX8MM_IOMUXC_I2C1_SDA_ 385 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
384 >; 386 >;
385 }; 387 };
386 388
387 pinctrl_i2c3: i2c3grp { 389 pinctrl_i2c3: i2c3grp {
388 fsl,pins = < 390 fsl,pins = <
389 MX8MM_IOMUXC_I2C3_SCL_ 391 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
390 MX8MM_IOMUXC_I2C3_SDA_ 392 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
391 >; 393 >;
392 }; 394 };
393 395
394 pinctrl_pmic: pmicirqgrp { 396 pinctrl_pmic: pmicirqgrp {
395 fsl,pins = < 397 fsl,pins = <
396 MX8MM_IOMUXC_SD1_DATA6 398 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
397 >; 399 >;
398 }; 400 };
399 401
400 pinctrl_reg_eth_phy: regethphygrp { 402 pinctrl_reg_eth_phy: regethphygrp {
401 fsl,pins = < 403 fsl,pins = <
402 MX8MM_IOMUXC_SD1_DATA7 404 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
403 >; 405 >;
404 }; 406 };
405 407
406 pinctrl_restouch: restouchgrp { 408 pinctrl_restouch: restouchgrp {
407 fsl,pins = < 409 fsl,pins = <
408 MX8MM_IOMUXC_GPIO1_IO0 410 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
409 >; 411 >;
410 }; 412 };
411 413
412 pinctrl_uart2: uart2grp { 414 pinctrl_uart2: uart2grp {
413 fsl,pins = < 415 fsl,pins = <
414 MX8MM_IOMUXC_SAI3_TXFS 416 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
415 MX8MM_IOMUXC_SAI3_TXC_ 417 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
416 MX8MM_IOMUXC_SAI3_RXC_ 418 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
417 MX8MM_IOMUXC_SAI3_RXD_ 419 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
418 >; 420 >;
419 }; 421 };
420 422
421 pinctrl_uart4: uart4grp { 423 pinctrl_uart4: uart4grp {
422 fsl,pins = < 424 fsl,pins = <
423 MX8MM_IOMUXC_UART4_RXD 425 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
424 MX8MM_IOMUXC_UART4_TXD 426 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
425 >; 427 >;
426 }; 428 };
427 429
428 pinctrl_usdhc1: usdhc1grp { 430 pinctrl_usdhc1: usdhc1grp {
429 fsl,pins = < 431 fsl,pins = <
430 MX8MM_IOMUXC_SD1_CLK_U 432 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
431 MX8MM_IOMUXC_SD1_CMD_U 433 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
432 MX8MM_IOMUXC_SD1_DATA0 434 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
433 MX8MM_IOMUXC_SD1_DATA1 435 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
434 MX8MM_IOMUXC_SD1_DATA2 436 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
435 MX8MM_IOMUXC_SD1_DATA3 437 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
436 >; 438 >;
437 }; 439 };
438 440
439 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 441 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
440 fsl,pins = < 442 fsl,pins = <
441 MX8MM_IOMUXC_SD1_CLK_U 443 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
442 MX8MM_IOMUXC_SD1_CMD_U 444 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
443 MX8MM_IOMUXC_SD1_DATA0 445 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
444 MX8MM_IOMUXC_SD1_DATA1 446 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
445 MX8MM_IOMUXC_SD1_DATA2 447 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
446 MX8MM_IOMUXC_SD1_DATA3 448 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
447 >; 449 >;
448 }; 450 };
449 451
450 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 452 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
451 fsl,pins = < 453 fsl,pins = <
452 MX8MM_IOMUXC_SD1_CLK_U 454 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
453 MX8MM_IOMUXC_SD1_CMD_U 455 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
454 MX8MM_IOMUXC_SD1_DATA0 456 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
455 MX8MM_IOMUXC_SD1_DATA1 457 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
456 MX8MM_IOMUXC_SD1_DATA2 458 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
457 MX8MM_IOMUXC_SD1_DATA3 459 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
458 >; 460 >;
459 }; 461 };
460 462
461 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 463 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
462 fsl,pins = < 464 fsl,pins = <
463 MX8MM_IOMUXC_GPIO1_IO1 465 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
464 >; 466 >;
465 }; 467 };
466 468
467 pinctrl_usdhc2: usdhc2grp { 469 pinctrl_usdhc2: usdhc2grp {
468 fsl,pins = < 470 fsl,pins = <
469 MX8MM_IOMUXC_SD2_CLK_U 471 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
470 MX8MM_IOMUXC_SD2_CMD_U 472 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
471 MX8MM_IOMUXC_SD2_DATA0 473 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
472 MX8MM_IOMUXC_SD2_DATA1 474 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
473 MX8MM_IOMUXC_SD2_DATA2 475 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
474 MX8MM_IOMUXC_SD2_DATA3 476 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
475 MX8MM_IOMUXC_GPIO1_IO0 477 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
476 >; 478 >;
477 }; 479 };
478 480
479 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 481 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
480 fsl,pins = < 482 fsl,pins = <
481 MX8MM_IOMUXC_SD2_CLK_U 483 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
482 MX8MM_IOMUXC_SD2_CMD_U 484 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
483 MX8MM_IOMUXC_SD2_DATA0 485 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
484 MX8MM_IOMUXC_SD2_DATA1 486 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
485 MX8MM_IOMUXC_SD2_DATA2 487 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
486 MX8MM_IOMUXC_SD2_DATA3 488 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
487 MX8MM_IOMUXC_GPIO1_IO0 489 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
488 >; 490 >;
489 }; 491 };
490 492
491 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 493 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
492 fsl,pins = < 494 fsl,pins = <
493 MX8MM_IOMUXC_SD2_CLK_U 495 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
494 MX8MM_IOMUXC_SD2_CMD_U 496 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
495 MX8MM_IOMUXC_SD2_DATA0 497 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
496 MX8MM_IOMUXC_SD2_DATA1 498 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
497 MX8MM_IOMUXC_SD2_DATA2 499 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
498 MX8MM_IOMUXC_SD2_DATA3 500 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
499 MX8MM_IOMUXC_GPIO1_IO0 501 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
500 >; 502 >;
501 }; 503 };
502 504
503 pinctrl_usdhc3: usdhc3grp { 505 pinctrl_usdhc3: usdhc3grp {
504 fsl,pins = < 506 fsl,pins = <
505 MX8MM_IOMUXC_NAND_WE_B 507 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
506 MX8MM_IOMUXC_NAND_WP_B 508 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
507 MX8MM_IOMUXC_NAND_DATA 509 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
508 MX8MM_IOMUXC_NAND_DATA 510 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
509 MX8MM_IOMUXC_NAND_DATA 511 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
510 MX8MM_IOMUXC_NAND_DATA 512 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
511 MX8MM_IOMUXC_NAND_RE_B 513 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
512 MX8MM_IOMUXC_NAND_CE2_ 514 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
513 MX8MM_IOMUXC_NAND_CE3_ 515 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
514 MX8MM_IOMUXC_NAND_CLE_ 516 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
515 MX8MM_IOMUXC_NAND_CE1_ 517 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
516 >; 518 >;
517 }; 519 };
518 520
519 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 521 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
520 fsl,pins = < 522 fsl,pins = <
521 MX8MM_IOMUXC_NAND_WE_B 523 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
522 MX8MM_IOMUXC_NAND_WP_B 524 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
523 MX8MM_IOMUXC_NAND_DATA 525 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
524 MX8MM_IOMUXC_NAND_DATA 526 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
525 MX8MM_IOMUXC_NAND_DATA 527 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
526 MX8MM_IOMUXC_NAND_DATA 528 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
527 MX8MM_IOMUXC_NAND_RE_B 529 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
528 MX8MM_IOMUXC_NAND_CE2_ 530 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
529 MX8MM_IOMUXC_NAND_CE3_ 531 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
530 MX8MM_IOMUXC_NAND_CLE_ 532 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
531 MX8MM_IOMUXC_NAND_CE1_ 533 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
532 >; 534 >;
533 }; 535 };
534 536
535 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 537 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
536 fsl,pins = < 538 fsl,pins = <
537 MX8MM_IOMUXC_NAND_WE_B 539 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
538 MX8MM_IOMUXC_NAND_WP_B 540 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
539 MX8MM_IOMUXC_NAND_DATA 541 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
540 MX8MM_IOMUXC_NAND_DATA 542 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
541 MX8MM_IOMUXC_NAND_DATA 543 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
542 MX8MM_IOMUXC_NAND_DATA 544 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
543 MX8MM_IOMUXC_NAND_RE_B 545 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
544 MX8MM_IOMUXC_NAND_CE2_ 546 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
545 MX8MM_IOMUXC_NAND_CE3_ 547 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
546 MX8MM_IOMUXC_NAND_CLE_ 548 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
547 MX8MM_IOMUXC_NAND_CE1_ 549 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
548 >; 550 >;
549 }; 551 };
550 552
551 pinctrl_wdog: wdoggrp { 553 pinctrl_wdog: wdoggrp {
552 fsl,pins = < 554 fsl,pins = <
553 MX8MM_IOMUXC_GPIO1_IO0 555 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
554 >; 556 >;
555 }; 557 };
556 }; 558 };
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