1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk
5 */
6
7 #include "imx8mm.dtsi"
8
9 / {
10 model = "Variscite VAR-SOM-MX8MM modul
11
12 chosen {
13 stdout-path = &uart4;
14 };
15
16 memory@40000000 {
17 device_type = "memory";
18 reg = <0x0 0x40000000 0 0x8000
19 };
20
21 reg_eth_phy: regulator-eth-phy {
22 compatible = "regulator-fixed"
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_reg_eth_
25 regulator-name = "eth_phy_pwr"
26 regulator-min-microvolt = <330
27 regulator-max-microvolt = <330
28 gpio = <&gpio2 9 GPIO_ACTIVE_H
29 enable-active-high;
30 };
31 };
32
33 &A53_0 {
34 cpu-supply = <&buck2_reg>;
35 };
36
37 &A53_1 {
38 cpu-supply = <&buck2_reg>;
39 };
40
41 &A53_2 {
42 cpu-supply = <&buck2_reg>;
43 };
44
45 &A53_3 {
46 cpu-supply = <&buck2_reg>;
47 };
48
49 &ddrc {
50 operating-points-v2 = <&ddrc_opp_table
51
52 ddrc_opp_table: opp-table {
53 compatible = "operating-points
54
55 opp-25000000 {
56 opp-hz = /bits/ 64 <25
57 };
58
59 opp-100000000 {
60 opp-hz = /bits/ 64 <10
61 };
62
63 opp-750000000 {
64 opp-hz = /bits/ 64 <75
65 };
66 };
67 };
68
69 &ecspi1 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ecspi1>;
72 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>
73 <&gpio1 0 GPIO_ACTIVE_LOW>
74 /delete-property/ dmas;
75 /delete-property/ dma-names;
76 status = "okay";
77
78 /* Resistive touch controller */
79 touchscreen@0 {
80 reg = <0>;
81 compatible = "ti,ads7846";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_restouch
84 interrupt-parent = <&gpio1>;
85 interrupts = <3 IRQ_TYPE_EDGE_
86
87 spi-max-frequency = <1500000>;
88 pendown-gpio = <&gpio1 3 GPIO_
89
90 ti,x-min = /bits/ 16 <125>;
91 touchscreen-size-x = <4008>;
92 ti,y-min = /bits/ 16 <282>;
93 touchscreen-size-y = <3864>;
94 ti,x-plate-ohms = /bits/ 16 <1
95 touchscreen-max-pressure = <25
96 touchscreen-average-samples =
97 ti,debounce-tol = /bits/ 16 <3
98 ti,debounce-rep = /bits/ 16 <1
99 ti,settle-delay-usec = /bits/
100 ti,keep-vref-on;
101 wakeup-source;
102 };
103 };
104
105 &fec1 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_fec1>;
108 phy-mode = "rgmii";
109 phy-handle = <ðphy>;
110 phy-supply = <®_eth_phy>;
111 fsl,magic-packet;
112 status = "okay";
113
114 mdio {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 ethphy: ethernet-phy@4 {
119 compatible = "ethernet
120 reg = <4>;
121 reset-gpios = <&gpio1
122 reset-assert-us = <100
123 reset-deassert-us = <1
124 };
125 };
126 };
127
128 &i2c1 {
129 clock-frequency = <400000>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_i2c1>;
132 status = "okay";
133
134 pmic@4b {
135 compatible = "rohm,bd71847";
136 reg = <0x4b>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_pmic>;
139 interrupt-parent = <&gpio2>;
140 interrupts = <8 IRQ_TYPE_LEVEL
141 rohm,reset-snvs-powered;
142
143 #clock-cells = <0>;
144 clocks = <&osc_32k>;
145 clock-output-names = "clk-32k-
146
147 regulators {
148 buck1_reg: BUCK1 {
149 regulator-name
150 regulator-min-
151 regulator-max-
152 regulator-boot
153 regulator-alwa
154 regulator-ramp
155 };
156
157 buck2_reg: BUCK2 {
158 regulator-name
159 regulator-min-
160 regulator-max-
161 regulator-boot
162 regulator-alwa
163 regulator-ramp
164 rohm,dvs-run-v
165 rohm,dvs-idle-
166 };
167
168 buck3_reg: BUCK3 {
169 regulator-name
170 regulator-min-
171 regulator-max-
172 regulator-boot
173 regulator-alwa
174 };
175
176 buck4_reg: BUCK4 {
177 regulator-name
178 regulator-min-
179 regulator-max-
180 regulator-boot
181 regulator-alwa
182 };
183
184 buck5_reg: BUCK5 {
185 regulator-name
186 regulator-min-
187 regulator-max-
188 regulator-boot
189 regulator-alwa
190 };
191
192 buck6_reg: BUCK6 {
193 regulator-name
194 regulator-min-
195 regulator-max-
196 regulator-boot
197 regulator-alwa
198 };
199
200 ldo1_reg: LDO1 {
201 regulator-name
202 regulator-min-
203 regulator-max-
204 regulator-boot
205 regulator-alwa
206 };
207
208 ldo2_reg: LDO2 {
209 regulator-name
210 regulator-min-
211 regulator-max-
212 regulator-boot
213 regulator-alwa
214 };
215
216 ldo3_reg: LDO3 {
217 regulator-name
218 regulator-min-
219 regulator-max-
220 regulator-boot
221 regulator-alwa
222 };
223
224 ldo4_reg: LDO4 {
225 regulator-name
226 regulator-min-
227 regulator-max-
228 regulator-boot
229 regulator-alwa
230 };
231
232 ldo5_reg: LDO5 {
233 regulator-min-
234 regulator-max-
235 regulator-alwa
236 };
237
238 ldo6_reg: LDO6 {
239 regulator-name
240 regulator-min-
241 regulator-max-
242 regulator-boot
243 regulator-alwa
244 };
245 };
246 };
247 };
248
249 &i2c3 {
250 clock-frequency = <400000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay";
254
255 /* TODO: configure audio, as of now ju
256 wm8904: codec@1a {
257 compatible = "wlf,wm8904";
258 reg = <0x1a>;
259 status = "disabled";
260 };
261 };
262
263 &snvs_pwrkey {
264 status = "okay";
265 };
266
267 /* Bluetooth */
268 &uart2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MM_CLK_UAR
272 assigned-clock-parents = <&clk IMX8MM_
273 uart-has-rtscts;
274 status = "okay";
275 };
276
277 /* Console */
278 &uart4 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay";
282 };
283
284 &usbotg1 {
285 dr_mode = "otg";
286 usb-role-switch;
287 status = "okay";
288 };
289
290 &usbotg2 {
291 dr_mode = "otg";
292 usb-role-switch;
293 status = "okay";
294 };
295
296 /* WIFI */
297 &usdhc1 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 pinctrl-names = "default", "state_100m
301 pinctrl-0 = <&pinctrl_usdhc1>;
302 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
303 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
304 bus-width = <4>;
305 non-removable;
306 keep-power-in-suspend;
307 status = "okay";
308
309 brcmf: bcrmf@1 {
310 reg = <1>;
311 compatible = "brcm,bcm4329-fma
312 };
313 };
314
315 /* SD */
316 &usdhc2 {
317 assigned-clocks = <&clk IMX8MM_CLK_USD
318 assigned-clock-rates = <200000000>;
319 pinctrl-names = "default", "state_100m
320 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
321 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
322 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
323 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>
324 bus-width = <4>;
325 vmmc-supply = <®_usdhc2_vmmc>;
326 status = "okay";
327 };
328
329 /* eMMC */
330 &usdhc3 {
331 assigned-clocks = <&clk IMX8MM_CLK_USD
332 assigned-clock-rates = <400000000>;
333 pinctrl-names = "default", "state_100m
334 pinctrl-0 = <&pinctrl_usdhc3>;
335 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
336 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
337 bus-width = <8>;
338 non-removable;
339 status = "okay";
340 };
341
342 &wdog1 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_wdog>;
345 fsl,ext-reset-output;
346 status = "okay";
347 };
348
349 &iomuxc {
350 pinctrl_ecspi1: ecspi1grp {
351 fsl,pins = <
352 MX8MM_IOMUXC_ECSPI1_SC
353 MX8MM_IOMUXC_ECSPI1_MO
354 MX8MM_IOMUXC_ECSPI1_MI
355 MX8MM_IOMUXC_GPIO1_IO1
356 MX8MM_IOMUXC_GPIO1_IO0
357 >;
358 };
359
360 pinctrl_fec1: fec1grp {
361 fsl,pins = <
362 MX8MM_IOMUXC_ENET_MDC_
363 MX8MM_IOMUXC_ENET_MDIO
364 MX8MM_IOMUXC_ENET_TD3_
365 MX8MM_IOMUXC_ENET_TD2_
366 MX8MM_IOMUXC_ENET_TD1_
367 MX8MM_IOMUXC_ENET_TD0_
368 MX8MM_IOMUXC_ENET_RD3_
369 MX8MM_IOMUXC_ENET_RD2_
370 MX8MM_IOMUXC_ENET_RD1_
371 MX8MM_IOMUXC_ENET_RD0_
372 MX8MM_IOMUXC_ENET_TXC_
373 MX8MM_IOMUXC_ENET_RXC_
374 MX8MM_IOMUXC_ENET_RX_C
375 MX8MM_IOMUXC_ENET_TX_C
376 MX8MM_IOMUXC_GPIO1_IO0
377 >;
378 };
379
380 pinctrl_i2c1: i2c1grp {
381 fsl,pins = <
382 MX8MM_IOMUXC_I2C1_SCL_
383 MX8MM_IOMUXC_I2C1_SDA_
384 >;
385 };
386
387 pinctrl_i2c3: i2c3grp {
388 fsl,pins = <
389 MX8MM_IOMUXC_I2C3_SCL_
390 MX8MM_IOMUXC_I2C3_SDA_
391 >;
392 };
393
394 pinctrl_pmic: pmicirqgrp {
395 fsl,pins = <
396 MX8MM_IOMUXC_SD1_DATA6
397 >;
398 };
399
400 pinctrl_reg_eth_phy: regethphygrp {
401 fsl,pins = <
402 MX8MM_IOMUXC_SD1_DATA7
403 >;
404 };
405
406 pinctrl_restouch: restouchgrp {
407 fsl,pins = <
408 MX8MM_IOMUXC_GPIO1_IO0
409 >;
410 };
411
412 pinctrl_uart2: uart2grp {
413 fsl,pins = <
414 MX8MM_IOMUXC_SAI3_TXFS
415 MX8MM_IOMUXC_SAI3_TXC_
416 MX8MM_IOMUXC_SAI3_RXC_
417 MX8MM_IOMUXC_SAI3_RXD_
418 >;
419 };
420
421 pinctrl_uart4: uart4grp {
422 fsl,pins = <
423 MX8MM_IOMUXC_UART4_RXD
424 MX8MM_IOMUXC_UART4_TXD
425 >;
426 };
427
428 pinctrl_usdhc1: usdhc1grp {
429 fsl,pins = <
430 MX8MM_IOMUXC_SD1_CLK_U
431 MX8MM_IOMUXC_SD1_CMD_U
432 MX8MM_IOMUXC_SD1_DATA0
433 MX8MM_IOMUXC_SD1_DATA1
434 MX8MM_IOMUXC_SD1_DATA2
435 MX8MM_IOMUXC_SD1_DATA3
436 >;
437 };
438
439 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
440 fsl,pins = <
441 MX8MM_IOMUXC_SD1_CLK_U
442 MX8MM_IOMUXC_SD1_CMD_U
443 MX8MM_IOMUXC_SD1_DATA0
444 MX8MM_IOMUXC_SD1_DATA1
445 MX8MM_IOMUXC_SD1_DATA2
446 MX8MM_IOMUXC_SD1_DATA3
447 >;
448 };
449
450 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
451 fsl,pins = <
452 MX8MM_IOMUXC_SD1_CLK_U
453 MX8MM_IOMUXC_SD1_CMD_U
454 MX8MM_IOMUXC_SD1_DATA0
455 MX8MM_IOMUXC_SD1_DATA1
456 MX8MM_IOMUXC_SD1_DATA2
457 MX8MM_IOMUXC_SD1_DATA3
458 >;
459 };
460
461 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
462 fsl,pins = <
463 MX8MM_IOMUXC_GPIO1_IO1
464 >;
465 };
466
467 pinctrl_usdhc2: usdhc2grp {
468 fsl,pins = <
469 MX8MM_IOMUXC_SD2_CLK_U
470 MX8MM_IOMUXC_SD2_CMD_U
471 MX8MM_IOMUXC_SD2_DATA0
472 MX8MM_IOMUXC_SD2_DATA1
473 MX8MM_IOMUXC_SD2_DATA2
474 MX8MM_IOMUXC_SD2_DATA3
475 MX8MM_IOMUXC_GPIO1_IO0
476 >;
477 };
478
479 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
480 fsl,pins = <
481 MX8MM_IOMUXC_SD2_CLK_U
482 MX8MM_IOMUXC_SD2_CMD_U
483 MX8MM_IOMUXC_SD2_DATA0
484 MX8MM_IOMUXC_SD2_DATA1
485 MX8MM_IOMUXC_SD2_DATA2
486 MX8MM_IOMUXC_SD2_DATA3
487 MX8MM_IOMUXC_GPIO1_IO0
488 >;
489 };
490
491 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
492 fsl,pins = <
493 MX8MM_IOMUXC_SD2_CLK_U
494 MX8MM_IOMUXC_SD2_CMD_U
495 MX8MM_IOMUXC_SD2_DATA0
496 MX8MM_IOMUXC_SD2_DATA1
497 MX8MM_IOMUXC_SD2_DATA2
498 MX8MM_IOMUXC_SD2_DATA3
499 MX8MM_IOMUXC_GPIO1_IO0
500 >;
501 };
502
503 pinctrl_usdhc3: usdhc3grp {
504 fsl,pins = <
505 MX8MM_IOMUXC_NAND_WE_B
506 MX8MM_IOMUXC_NAND_WP_B
507 MX8MM_IOMUXC_NAND_DATA
508 MX8MM_IOMUXC_NAND_DATA
509 MX8MM_IOMUXC_NAND_DATA
510 MX8MM_IOMUXC_NAND_DATA
511 MX8MM_IOMUXC_NAND_RE_B
512 MX8MM_IOMUXC_NAND_CE2_
513 MX8MM_IOMUXC_NAND_CE3_
514 MX8MM_IOMUXC_NAND_CLE_
515 MX8MM_IOMUXC_NAND_CE1_
516 >;
517 };
518
519 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr
520 fsl,pins = <
521 MX8MM_IOMUXC_NAND_WE_B
522 MX8MM_IOMUXC_NAND_WP_B
523 MX8MM_IOMUXC_NAND_DATA
524 MX8MM_IOMUXC_NAND_DATA
525 MX8MM_IOMUXC_NAND_DATA
526 MX8MM_IOMUXC_NAND_DATA
527 MX8MM_IOMUXC_NAND_RE_B
528 MX8MM_IOMUXC_NAND_CE2_
529 MX8MM_IOMUXC_NAND_CE3_
530 MX8MM_IOMUXC_NAND_CLE_
531 MX8MM_IOMUXC_NAND_CE1_
532 >;
533 };
534
535 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr
536 fsl,pins = <
537 MX8MM_IOMUXC_NAND_WE_B
538 MX8MM_IOMUXC_NAND_WP_B
539 MX8MM_IOMUXC_NAND_DATA
540 MX8MM_IOMUXC_NAND_DATA
541 MX8MM_IOMUXC_NAND_DATA
542 MX8MM_IOMUXC_NAND_DATA
543 MX8MM_IOMUXC_NAND_RE_B
544 MX8MM_IOMUXC_NAND_CE2_
545 MX8MM_IOMUXC_NAND_CE3_
546 MX8MM_IOMUXC_NAND_CLE_
547 MX8MM_IOMUXC_NAND_CE1_
548 >;
549 };
550
551 pinctrl_wdog: wdoggrp {
552 fsl,pins = <
553 MX8MM_IOMUXC_GPIO1_IO0
554 >;
555 };
556 };
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