1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 Gateworks Corporation 3 * Copyright 2020 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
9 8
10 / { 9 / {
11 aliases { 10 aliases {
12 usb0 = &usbotg1; 11 usb0 = &usbotg1;
13 usb1 = &usbotg2; 12 usb1 = &usbotg2;
14 }; 13 };
15 14
16 led-controller { 15 led-controller {
17 compatible = "gpio-leds"; 16 compatible = "gpio-leds";
18 pinctrl-names = "default"; 17 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_led 18 pinctrl-0 = <&pinctrl_gpio_leds>;
20 19
21 led-0 { 20 led-0 {
22 function = LED_FUNCTIO 21 function = LED_FUNCTION_STATUS;
23 color = <LED_COLOR_ID_ 22 color = <LED_COLOR_ID_GREEN>;
24 gpios = <&gpio5 5 GPIO 23 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
25 default-state = "on"; 24 default-state = "on";
26 linux,default-trigger 25 linux,default-trigger = "heartbeat";
27 }; 26 };
28 27
29 led-1 { 28 led-1 {
30 function = LED_FUNCTIO 29 function = LED_FUNCTION_STATUS;
31 color = <LED_COLOR_ID_ 30 color = <LED_COLOR_ID_RED>;
32 gpios = <&gpio5 4 GPIO 31 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
33 default-state = "off"; 32 default-state = "off";
34 }; 33 };
35 }; 34 };
36 35
37 pcie0_refclk: pcie0-refclk { <<
38 compatible = "fixed-clock"; <<
39 #clock-cells = <0>; <<
40 clock-frequency = <100000000>; <<
41 }; <<
42 <<
43 pps { 36 pps {
44 compatible = "pps-gpio"; 37 compatible = "pps-gpio";
45 pinctrl-names = "default"; 38 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_pps>; 39 pinctrl-0 = <&pinctrl_pps>;
47 gpios = <&gpio1 15 GPIO_ACTIVE 40 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
48 status = "okay"; 41 status = "okay";
49 }; 42 };
>> 43
>> 44 reg_usb_otg1_vbus: regulator-usb-otg1 {
>> 45 pinctrl-names = "default";
>> 46 pinctrl-0 = <&pinctrl_reg_usb1_en>;
>> 47 compatible = "regulator-fixed";
>> 48 regulator-name = "usb_otg1_vbus";
>> 49 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
>> 50 enable-active-high;
>> 51 regulator-min-microvolt = <5000000>;
>> 52 regulator-max-microvolt = <5000000>;
>> 53 };
50 }; 54 };
51 55
>> 56 /* off-board header */
52 &ecspi2 { 57 &ecspi2 {
53 pinctrl-names = "default"; 58 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_spi2>; 59 pinctrl-0 = <&pinctrl_spi2>;
55 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> !! 60 cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
56 <&gpio1 10 GPIO_ACTIVE_LOW> <<
57 status = "okay"; 61 status = "okay";
58 <<
59 tpm@1 { <<
60 compatible = "atmel,attpm20p", <<
61 reg = <0x1>; <<
62 spi-max-frequency = <36000000> <<
63 }; <<
64 }; <<
65 <<
66 &gpio1 { <<
67 gpio-line-names = "", "", "", "", "", <<
68 "", "dio1", "", "", "", "", "" <<
69 "", "", "", "", "", "", "", "" <<
70 "", "", "", "", "", "", "", "" <<
71 }; <<
72 <<
73 &gpio4 { <<
74 gpio-line-names = "", "", "", "dio2", <<
75 "", "", "", "", "", "", "", "" <<
76 "", "", "", "", "", "", "", "" <<
77 "", "", "", "", "", "", "", "" <<
78 }; 62 };
79 63
80 &i2c2 { 64 &i2c2 {
81 clock-frequency = <400000>; 65 clock-frequency = <400000>;
82 pinctrl-names = "default"; 66 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_i2c2>; 67 pinctrl-0 = <&pinctrl_i2c2>;
84 status = "okay"; 68 status = "okay";
85 69
86 accelerometer@19 { 70 accelerometer@19 {
87 pinctrl-names = "default"; 71 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_accel>; 72 pinctrl-0 = <&pinctrl_accel>;
89 compatible = "st,lis2de12"; 73 compatible = "st,lis2de12";
90 reg = <0x19>; 74 reg = <0x19>;
91 st,drdy-int-pin = <1>; 75 st,drdy-int-pin = <1>;
92 interrupt-parent = <&gpio4>; 76 interrupt-parent = <&gpio4>;
93 interrupts = <5 IRQ_TYPE_LEVEL 77 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> 78 interrupt-names = "INT1";
94 }; 79 };
95 }; 80 };
96 81
97 /* off-board header */ 82 /* off-board header */
98 &i2c3 { 83 &i2c3 {
99 clock-frequency = <400000>; 84 clock-frequency = <400000>;
100 pinctrl-names = "default"; 85 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c3>; 86 pinctrl-0 = <&pinctrl_i2c3>;
102 status = "okay"; 87 status = "okay";
103 }; 88 };
104 89
105 &pcie_phy { <<
106 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
107 fsl,clkreq-unsupported; <<
108 clocks = <&pcie0_refclk>; <<
109 clock-names = "ref"; <<
110 status = "okay"; <<
111 }; <<
112 <<
113 &pcie0 { <<
114 pinctrl-names = "default"; <<
115 pinctrl-0 = <&pinctrl_pcie0>; <<
116 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW <<
117 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <<
118 <&clk IMX8MM_CLK_PCIE1_AUX>; <<
119 assigned-clocks = <&clk IMX8MM_CLK_PCI <<
120 <&clk IMX8MM_CLK_PCI <<
121 assigned-clock-rates = <10000000>, <25 <<
122 assigned-clock-parents = <&clk IMX8MM_ <<
123 <&clk IMX8MM_ <<
124 status = "okay"; <<
125 }; <<
126 <<
127 /* GPS */ 90 /* GPS */
128 &uart1 { 91 &uart1 {
129 pinctrl-names = "default"; 92 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart1>; 93 pinctrl-0 = <&pinctrl_uart1>;
131 status = "okay"; 94 status = "okay";
132 }; 95 };
133 96
134 /* off-board header */ 97 /* off-board header */
135 &uart3 { 98 &uart3 {
136 pinctrl-names = "default"; 99 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart3>; 100 pinctrl-0 = <&pinctrl_uart3>;
138 status = "okay"; 101 status = "okay";
139 }; 102 };
140 103
141 &usbotg1 { 104 &usbotg1 {
142 pinctrl-names = "default"; <<
143 pinctrl-0 = <&pinctrl_usbotg1>; <<
144 dr_mode = "otg"; 105 dr_mode = "otg";
145 over-current-active-low; !! 106 vbus-supply = <®_usb_otg1_vbus>;
146 status = "okay"; 107 status = "okay";
147 }; 108 };
148 109
149 &usbotg2 { 110 &usbotg2 {
150 dr_mode = "host"; 111 dr_mode = "host";
151 disable-over-current; <<
152 status = "okay"; 112 status = "okay";
153 }; 113 };
154 114
155 &iomuxc { 115 &iomuxc {
156 pinctrl-names = "default"; 116 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_hog>; 117 pinctrl-0 = <&pinctrl_hog>;
158 118
159 pinctrl_hog: hoggrp { 119 pinctrl_hog: hoggrp {
160 fsl,pins = < 120 fsl,pins = <
161 MX8MM_IOMUXC_SPDIF_TX_ 121 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
162 MX8MM_IOMUXC_GPIO1_IO0 122 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
163 MX8MM_IOMUXC_SAI1_RXD5 123 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
164 MX8MM_IOMUXC_GPIO1_IO0 124 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
165 MX8MM_IOMUXC_GPIO1_IO0 125 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
166 MX8MM_IOMUXC_SAI1_RXD1 126 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
167 MX8MM_IOMUXC_SAI1_RXD2 127 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
168 >; 128 >;
169 }; 129 };
170 130
171 pinctrl_accel: accelgrp { 131 pinctrl_accel: accelgrp {
172 fsl,pins = < 132 fsl,pins = <
173 MX8MM_IOMUXC_SAI1_RXD3 133 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
174 >; 134 >;
175 }; 135 };
176 136
177 pinctrl_gpio_leds: gpioledgrp { 137 pinctrl_gpio_leds: gpioledgrp {
178 fsl,pins = < 138 fsl,pins = <
179 MX8MM_IOMUXC_SPDIF_EXT 139 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
180 MX8MM_IOMUXC_SPDIF_RX_ 140 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
181 >; 141 >;
182 }; 142 };
183 143
184 pinctrl_i2c3: i2c3grp { 144 pinctrl_i2c3: i2c3grp {
185 fsl,pins = < 145 fsl,pins = <
186 MX8MM_IOMUXC_I2C3_SCL_ 146 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
187 MX8MM_IOMUXC_I2C3_SDA_ 147 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
188 >; 148 >;
189 }; 149 };
190 150
191 pinctrl_pcie0: pcie0grp { !! 151 pinctrl_pps: ppsgrp {
192 fsl,pins = < 152 fsl,pins = <
193 MX8MM_IOMUXC_SAI1_RXD4 !! 153 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
194 >; 154 >;
195 }; 155 };
196 156
197 pinctrl_pps: ppsgrp { !! 157 pinctrl_reg_usb1_en: regusb1grp {
198 fsl,pins = < 158 fsl,pins = <
199 MX8MM_IOMUXC_GPIO1_IO1 !! 159 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>> 160 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
>> 161 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
200 >; 162 >;
201 }; 163 };
202 164
203 pinctrl_spi2: spi2grp { 165 pinctrl_spi2: spi2grp {
204 fsl,pins = < 166 fsl,pins = <
205 MX8MM_IOMUXC_ECSPI2_SC 167 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
206 MX8MM_IOMUXC_ECSPI2_MO 168 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
207 MX8MM_IOMUXC_ECSPI2_MI !! 169 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
208 MX8MM_IOMUXC_ECSPI2_SS 170 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
209 MX8MM_IOMUXC_GPIO1_IO1 <<
210 >; 171 >;
211 }; 172 };
212 173
213 pinctrl_uart1: uart1grp { 174 pinctrl_uart1: uart1grp {
214 fsl,pins = < 175 fsl,pins = <
215 MX8MM_IOMUXC_UART1_RXD 176 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
216 MX8MM_IOMUXC_UART1_TXD 177 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
217 >; 178 >;
218 }; 179 };
219 180
220 pinctrl_uart3: uart3grp { 181 pinctrl_uart3: uart3grp {
221 fsl,pins = < 182 fsl,pins = <
222 MX8MM_IOMUXC_UART3_RXD 183 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
223 MX8MM_IOMUXC_UART3_TXD 184 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
224 >; <<
225 }; <<
226 <<
227 pinctrl_usbotg1: usbotg1grp { <<
228 fsl,pins = < <<
229 MX8MM_IOMUXC_GPIO1_IO1 <<
230 MX8MM_IOMUXC_GPIO1_IO1 <<
231 >; 185 >;
232 }; 186 };
233 }; 187 };
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