1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 Gateworks Corporation 3 * Copyright 2020 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 9
10 / { 10 / {
11 aliases { 11 aliases {
12 usb0 = &usbotg1; 12 usb0 = &usbotg1;
13 usb1 = &usbotg2; 13 usb1 = &usbotg2;
14 }; 14 };
15 15
16 led-controller { 16 led-controller {
17 compatible = "gpio-leds"; 17 compatible = "gpio-leds";
18 pinctrl-names = "default"; 18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_led 19 pinctrl-0 = <&pinctrl_gpio_leds>;
20 20
21 led-0 { 21 led-0 {
22 function = LED_FUNCTIO 22 function = LED_FUNCTION_STATUS;
23 color = <LED_COLOR_ID_ 23 color = <LED_COLOR_ID_GREEN>;
24 gpios = <&gpio5 5 GPIO 24 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
25 default-state = "on"; 25 default-state = "on";
26 linux,default-trigger 26 linux,default-trigger = "heartbeat";
27 }; 27 };
28 28
29 led-1 { 29 led-1 {
30 function = LED_FUNCTIO 30 function = LED_FUNCTION_STATUS;
31 color = <LED_COLOR_ID_ 31 color = <LED_COLOR_ID_RED>;
32 gpios = <&gpio5 4 GPIO 32 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
33 default-state = "off"; 33 default-state = "off";
34 }; 34 };
35 }; 35 };
36 36
37 pcie0_refclk: pcie0-refclk { 37 pcie0_refclk: pcie0-refclk {
38 compatible = "fixed-clock"; 38 compatible = "fixed-clock";
39 #clock-cells = <0>; 39 #clock-cells = <0>;
40 clock-frequency = <100000000>; 40 clock-frequency = <100000000>;
41 }; 41 };
42 42
43 pps { 43 pps {
44 compatible = "pps-gpio"; 44 compatible = "pps-gpio";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_pps>; 46 pinctrl-0 = <&pinctrl_pps>;
47 gpios = <&gpio1 15 GPIO_ACTIVE 47 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 }; 50 };
51 51
>> 52 /* off-board header */
52 &ecspi2 { 53 &ecspi2 {
53 pinctrl-names = "default"; 54 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_spi2>; 55 pinctrl-0 = <&pinctrl_spi2>;
55 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> !! 56 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
56 <&gpio1 10 GPIO_ACTIVE_LOW> <<
57 status = "okay"; 57 status = "okay";
58 <<
59 tpm@1 { <<
60 compatible = "atmel,attpm20p", <<
61 reg = <0x1>; <<
62 spi-max-frequency = <36000000> <<
63 }; <<
64 }; 58 };
65 59
66 &gpio1 { 60 &gpio1 {
67 gpio-line-names = "", "", "", "", "", 61 gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
68 "", "dio1", "", "", "", "", "" 62 "", "dio1", "", "", "", "", "", "",
69 "", "", "", "", "", "", "", "" 63 "", "", "", "", "", "", "", "",
70 "", "", "", "", "", "", "", "" 64 "", "", "", "", "", "", "", "";
71 }; 65 };
72 66
73 &gpio4 { 67 &gpio4 {
74 gpio-line-names = "", "", "", "dio2", 68 gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
75 "", "", "", "", "", "", "", "" 69 "", "", "", "", "", "", "", "",
76 "", "", "", "", "", "", "", "" 70 "", "", "", "", "", "", "", "",
77 "", "", "", "", "", "", "", "" 71 "", "", "", "", "", "", "", "";
78 }; 72 };
79 73
80 &i2c2 { 74 &i2c2 {
81 clock-frequency = <400000>; 75 clock-frequency = <400000>;
82 pinctrl-names = "default"; 76 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_i2c2>; 77 pinctrl-0 = <&pinctrl_i2c2>;
84 status = "okay"; 78 status = "okay";
85 79
86 accelerometer@19 { 80 accelerometer@19 {
87 pinctrl-names = "default"; 81 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_accel>; 82 pinctrl-0 = <&pinctrl_accel>;
89 compatible = "st,lis2de12"; 83 compatible = "st,lis2de12";
90 reg = <0x19>; 84 reg = <0x19>;
91 st,drdy-int-pin = <1>; 85 st,drdy-int-pin = <1>;
92 interrupt-parent = <&gpio4>; 86 interrupt-parent = <&gpio4>;
93 interrupts = <5 IRQ_TYPE_LEVEL 87 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> 88 interrupt-names = "INT1";
94 }; 89 };
95 }; 90 };
96 91
97 /* off-board header */ 92 /* off-board header */
98 &i2c3 { 93 &i2c3 {
99 clock-frequency = <400000>; 94 clock-frequency = <400000>;
100 pinctrl-names = "default"; 95 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c3>; 96 pinctrl-0 = <&pinctrl_i2c3>;
102 status = "okay"; 97 status = "okay";
103 }; 98 };
104 99
105 &pcie_phy { 100 &pcie_phy {
106 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 101 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
107 fsl,clkreq-unsupported; 102 fsl,clkreq-unsupported;
108 clocks = <&pcie0_refclk>; 103 clocks = <&pcie0_refclk>;
109 clock-names = "ref"; 104 clock-names = "ref";
110 status = "okay"; 105 status = "okay";
111 }; 106 };
112 107
113 &pcie0 { 108 &pcie0 {
114 pinctrl-names = "default"; 109 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_pcie0>; 110 pinctrl-0 = <&pinctrl_pcie0>;
116 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW 111 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
117 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 112 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
118 <&clk IMX8MM_CLK_PCIE1_AUX>; 113 <&clk IMX8MM_CLK_PCIE1_AUX>;
119 assigned-clocks = <&clk IMX8MM_CLK_PCI 114 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
120 <&clk IMX8MM_CLK_PCI 115 <&clk IMX8MM_CLK_PCIE1_CTRL>;
121 assigned-clock-rates = <10000000>, <25 116 assigned-clock-rates = <10000000>, <250000000>;
122 assigned-clock-parents = <&clk IMX8MM_ 117 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
123 <&clk IMX8MM_ 118 <&clk IMX8MM_SYS_PLL2_250M>;
124 status = "okay"; 119 status = "okay";
125 }; 120 };
126 121
127 /* GPS */ 122 /* GPS */
128 &uart1 { 123 &uart1 {
129 pinctrl-names = "default"; 124 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart1>; 125 pinctrl-0 = <&pinctrl_uart1>;
131 status = "okay"; 126 status = "okay";
132 }; 127 };
133 128
134 /* off-board header */ 129 /* off-board header */
135 &uart3 { 130 &uart3 {
136 pinctrl-names = "default"; 131 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart3>; 132 pinctrl-0 = <&pinctrl_uart3>;
138 status = "okay"; 133 status = "okay";
139 }; 134 };
140 135
141 &usbotg1 { 136 &usbotg1 {
142 pinctrl-names = "default"; 137 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usbotg1>; 138 pinctrl-0 = <&pinctrl_usbotg1>;
144 dr_mode = "otg"; 139 dr_mode = "otg";
145 over-current-active-low; 140 over-current-active-low;
146 status = "okay"; 141 status = "okay";
147 }; 142 };
148 143
149 &usbotg2 { 144 &usbotg2 {
150 dr_mode = "host"; 145 dr_mode = "host";
151 disable-over-current; 146 disable-over-current;
152 status = "okay"; 147 status = "okay";
153 }; 148 };
154 149
155 &iomuxc { 150 &iomuxc {
156 pinctrl-names = "default"; 151 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_hog>; 152 pinctrl-0 = <&pinctrl_hog>;
158 153
159 pinctrl_hog: hoggrp { 154 pinctrl_hog: hoggrp {
160 fsl,pins = < 155 fsl,pins = <
161 MX8MM_IOMUXC_SPDIF_TX_ 156 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
162 MX8MM_IOMUXC_GPIO1_IO0 157 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
163 MX8MM_IOMUXC_SAI1_RXD5 158 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
164 MX8MM_IOMUXC_GPIO1_IO0 159 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
165 MX8MM_IOMUXC_GPIO1_IO0 160 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
166 MX8MM_IOMUXC_SAI1_RXD1 161 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
167 MX8MM_IOMUXC_SAI1_RXD2 162 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
168 >; 163 >;
169 }; 164 };
170 165
171 pinctrl_accel: accelgrp { 166 pinctrl_accel: accelgrp {
172 fsl,pins = < 167 fsl,pins = <
173 MX8MM_IOMUXC_SAI1_RXD3 168 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
174 >; 169 >;
175 }; 170 };
176 171
177 pinctrl_gpio_leds: gpioledgrp { 172 pinctrl_gpio_leds: gpioledgrp {
178 fsl,pins = < 173 fsl,pins = <
179 MX8MM_IOMUXC_SPDIF_EXT 174 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
180 MX8MM_IOMUXC_SPDIF_RX_ 175 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
181 >; 176 >;
182 }; 177 };
183 178
184 pinctrl_i2c3: i2c3grp { 179 pinctrl_i2c3: i2c3grp {
185 fsl,pins = < 180 fsl,pins = <
186 MX8MM_IOMUXC_I2C3_SCL_ 181 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
187 MX8MM_IOMUXC_I2C3_SDA_ 182 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
188 >; 183 >;
189 }; 184 };
190 185
191 pinctrl_pcie0: pcie0grp { 186 pinctrl_pcie0: pcie0grp {
192 fsl,pins = < 187 fsl,pins = <
193 MX8MM_IOMUXC_SAI1_RXD4 188 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
194 >; 189 >;
195 }; 190 };
196 191
197 pinctrl_pps: ppsgrp { 192 pinctrl_pps: ppsgrp {
198 fsl,pins = < 193 fsl,pins = <
199 MX8MM_IOMUXC_GPIO1_IO1 194 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
200 >; 195 >;
201 }; 196 };
202 197
203 pinctrl_spi2: spi2grp { 198 pinctrl_spi2: spi2grp {
204 fsl,pins = < 199 fsl,pins = <
205 MX8MM_IOMUXC_ECSPI2_SC 200 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
206 MX8MM_IOMUXC_ECSPI2_MO 201 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
207 MX8MM_IOMUXC_ECSPI2_MI 202 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
208 MX8MM_IOMUXC_ECSPI2_SS 203 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
209 MX8MM_IOMUXC_GPIO1_IO1 <<
210 >; 204 >;
211 }; 205 };
212 206
213 pinctrl_uart1: uart1grp { 207 pinctrl_uart1: uart1grp {
214 fsl,pins = < 208 fsl,pins = <
215 MX8MM_IOMUXC_UART1_RXD 209 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
216 MX8MM_IOMUXC_UART1_TXD 210 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
217 >; 211 >;
218 }; 212 };
219 213
220 pinctrl_uart3: uart3grp { 214 pinctrl_uart3: uart3grp {
221 fsl,pins = < 215 fsl,pins = <
222 MX8MM_IOMUXC_UART3_RXD 216 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
223 MX8MM_IOMUXC_UART3_TXD 217 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
224 >; 218 >;
225 }; 219 };
226 220
227 pinctrl_usbotg1: usbotg1grp { 221 pinctrl_usbotg1: usbotg1grp {
228 fsl,pins = < 222 fsl,pins = <
229 MX8MM_IOMUXC_GPIO1_IO1 223 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
230 MX8MM_IOMUXC_GPIO1_IO1 224 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
231 >; 225 >;
232 }; 226 };
233 }; 227 };
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