1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Gateworks Corporation 3 * Copyright 2022 Gateworks Corporation
4 * 4 *
5 * GW72xx RS485 HD: 5 * GW72xx RS485 HD:
6 * - GPIO1_0 rs485_term selects on-chip termi 6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high 7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven high 8 * - GPIO4_2 rs485_hd needs to be driven high (active)
9 * - UART4_TX is DE for RS485 transmitter 9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high 10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be pulled high 11 * - RS485_HALF needs to be pulled high
12 */ 12 */
13 13
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 15
16 #include "imx8mm-pinfunc.h" 16 #include "imx8mm-pinfunc.h"
17 17
18 /dts-v1/; 18 /dts-v1/;
19 /plugin/; 19 /plugin/;
20 20
21 &gpio4 { 21 &gpio4 {
22 rs485-en-hog { 22 rs485-en-hog {
23 gpio-hog; 23 gpio-hog;
24 gpios = <0 GPIO_ACTIVE_HIGH>; 24 gpios = <0 GPIO_ACTIVE_HIGH>;
25 output-high; 25 output-high;
26 line-name = "rs485_en"; 26 line-name = "rs485_en";
27 }; 27 };
28 28
29 rs485-hd-hog { 29 rs485-hd-hog {
30 gpio-hog; 30 gpio-hog;
31 gpios = <2 GPIO_ACTIVE_HIGH>; 31 gpios = <2 GPIO_ACTIVE_HIGH>;
32 output-high; 32 output-high;
33 line-name = "rs485_hd"; 33 line-name = "rs485_hd";
34 }; 34 };
35 }; 35 };
36 36
37 &uart2 { 37 &uart2 {
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart2>; 39 pinctrl-0 = <&pinctrl_uart2>;
40 rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIG 40 rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
41 linux,rs485-enabled-at-boot-time; 41 linux,rs485-enabled-at-boot-time;
42 status = "okay"; 42 status = "okay";
43 }; 43 };
44 44
45 &uart4 { 45 &uart4 {
46 status = "disabled"; 46 status = "disabled";
47 }; 47 };
48 48
49 &iomuxc { 49 &iomuxc {
50 pinctrl_uart2: uart2grp { 50 pinctrl_uart2: uart2grp {
51 fsl,pins = < 51 fsl,pins = <
52 MX8MM_IOMUXC_UART2_RXD 52 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
53 MX8MM_IOMUXC_UART2_TXD 53 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
54 MX8MM_IOMUXC_UART4_TXD 54 MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
55 >; 55 >;
56 }; 56 };
57 }; 57 };
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