1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 Gateworks Corporation 3 * Copyright 2020 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
9 8
10 / { 9 / {
11 aliases { 10 aliases {
12 ethernet1 = ð1; <<
13 usb0 = &usbotg1; 11 usb0 = &usbotg1;
14 usb1 = &usbotg2; 12 usb1 = &usbotg2;
15 }; 13 };
16 14
17 led-controller { 15 led-controller {
18 compatible = "gpio-leds"; 16 compatible = "gpio-leds";
19 pinctrl-names = "default"; 17 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_led 18 pinctrl-0 = <&pinctrl_gpio_leds>;
21 19
22 led-0 { 20 led-0 {
23 function = LED_FUNCTIO 21 function = LED_FUNCTION_STATUS;
24 color = <LED_COLOR_ID_ 22 color = <LED_COLOR_ID_GREEN>;
25 gpios = <&gpio5 5 GPIO 23 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26 default-state = "on"; 24 default-state = "on";
27 linux,default-trigger 25 linux,default-trigger = "heartbeat";
28 }; 26 };
29 27
30 led-1 { 28 led-1 {
31 function = LED_FUNCTIO 29 function = LED_FUNCTION_STATUS;
32 color = <LED_COLOR_ID_ 30 color = <LED_COLOR_ID_RED>;
33 gpios = <&gpio5 4 GPIO 31 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34 default-state = "off"; 32 default-state = "off";
35 }; 33 };
36 }; 34 };
37 35
38 pcie0_refclk: pcie0-refclk { <<
39 compatible = "fixed-clock"; <<
40 #clock-cells = <0>; <<
41 clock-frequency = <100000000>; <<
42 }; <<
43 <<
44 pps { 36 pps {
45 compatible = "pps-gpio"; 37 compatible = "pps-gpio";
46 pinctrl-names = "default"; 38 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>; 39 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE 40 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49 status = "okay"; 41 status = "okay";
50 }; 42 };
51 43
52 reg_1p8v: regulator-1p8v { 44 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed" 45 compatible = "regulator-fixed";
54 regulator-name = "1P8V"; 46 regulator-name = "1P8V";
55 regulator-min-microvolt = <180 47 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <180 48 regulator-max-microvolt = <1800000>;
57 regulator-always-on; 49 regulator-always-on;
58 }; 50 };
59 51
60 reg_3p3v: regulator-3p3v { 52 reg_3p3v: regulator-3p3v {
61 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
62 regulator-name = "3P3V"; 54 regulator-name = "3P3V";
63 regulator-min-microvolt = <330 55 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <330 56 regulator-max-microvolt = <3300000>;
65 regulator-always-on; 57 regulator-always-on;
66 }; 58 };
67 59
68 reg_usb_otg1_vbus: regulator-usb-otg1 60 reg_usb_otg1_vbus: regulator-usb-otg1 {
69 pinctrl-names = "default"; 61 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_reg_usb1 62 pinctrl-0 = <&pinctrl_reg_usb1_en>;
71 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
72 regulator-name = "usb_otg1_vbu 64 regulator-name = "usb_otg1_vbus";
73 gpio = <&gpio1 12 GPIO_ACTIVE_ 65 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
74 enable-active-high; 66 enable-active-high;
75 regulator-min-microvolt = <500 67 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <500 68 regulator-max-microvolt = <5000000>;
77 }; 69 };
78 70
79 reg_usb_otg2_vbus: regulator-usb-otg2 71 reg_usb_otg2_vbus: regulator-usb-otg2 {
80 pinctrl-names = "default"; 72 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_reg_usb2 73 pinctrl-0 = <&pinctrl_reg_usb2_en>;
82 compatible = "regulator-fixed" 74 compatible = "regulator-fixed";
83 regulator-name = "usb_otg2_vbu 75 regulator-name = "usb_otg2_vbus";
84 gpio = <&gpio1 8 GPIO_ACTIVE_H 76 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
85 enable-active-high; 77 enable-active-high;
86 regulator-min-microvolt = <500 78 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <500 79 regulator-max-microvolt = <5000000>;
88 }; 80 };
89 81
90 reg_wifi_en: regulator-wifi-en { 82 reg_wifi_en: regulator-wifi-en {
91 pinctrl-names = "default"; 83 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_reg_wl>; 84 pinctrl-0 = <&pinctrl_reg_wl>;
93 compatible = "regulator-fixed" 85 compatible = "regulator-fixed";
94 regulator-name = "wl"; 86 regulator-name = "wl";
95 gpio = <&gpio1 5 GPIO_ACTIVE_H 87 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <100>; 88 startup-delay-us = <100>;
97 enable-active-high; 89 enable-active-high;
98 regulator-min-microvolt = <330 90 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <330 91 regulator-max-microvolt = <3300000>;
100 }; 92 };
101 }; 93 };
102 94
103 /* off-board header */ 95 /* off-board header */
104 &ecspi2 { 96 &ecspi2 {
105 pinctrl-names = "default"; 97 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi2>; 98 pinctrl-0 = <&pinctrl_spi2>;
107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> !! 99 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
108 <&gpio1 10 GPIO_ACTIVE_LOW> <<
109 status = "okay"; 100 status = "okay";
110 <<
111 tpm@1 { <<
112 compatible = "atmel,attpm20p", <<
113 reg = <0x1>; <<
114 spi-max-frequency = <36000000> <<
115 }; <<
116 }; <<
117 <<
118 &gpio1 { <<
119 gpio-line-names = "rs485_term", "mipi_ <<
120 "", "", "pci_usb_sel", "dio0", <<
121 "", "dio1", "", "", "", "", "" <<
122 "", "", "", "", "", "", "", "" <<
123 "", "", "", "", "", "", "", "" <<
124 }; <<
125 <<
126 &gpio4 { <<
127 gpio-line-names = "rs485_en", "mipi_gp <<
128 "mipi_gpio1", "", "", "pci_wdi <<
129 "", "", "", "", "", "", "", "" <<
130 "", "", "", "", "", "", "", "" <<
131 "", "", "", "", "", "", "", "" <<
132 }; 101 };
133 102
134 &i2c2 { 103 &i2c2 {
135 clock-frequency = <400000>; 104 clock-frequency = <400000>;
136 pinctrl-names = "default"; 105 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_i2c2>; 106 pinctrl-0 = <&pinctrl_i2c2>;
138 status = "okay"; 107 status = "okay";
139 108
140 accelerometer@19 { 109 accelerometer@19 {
141 pinctrl-names = "default"; 110 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_accel>; 111 pinctrl-0 = <&pinctrl_accel>;
143 compatible = "st,lis2de12"; 112 compatible = "st,lis2de12";
144 reg = <0x19>; 113 reg = <0x19>;
145 st,drdy-int-pin = <1>; 114 st,drdy-int-pin = <1>;
146 interrupt-parent = <&gpio4>; 115 interrupt-parent = <&gpio4>;
147 interrupts = <5 IRQ_TYPE_LEVEL 116 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> 117 interrupt-names = "INT1";
148 }; 118 };
149 }; 119 };
150 120
151 /* off-board header */ 121 /* off-board header */
152 &i2c3 { 122 &i2c3 {
153 clock-frequency = <400000>; 123 clock-frequency = <400000>;
154 pinctrl-names = "default"; 124 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c3>; 125 pinctrl-0 = <&pinctrl_i2c3>;
156 status = "okay"; 126 status = "okay";
157 }; 127 };
158 128
159 &pcie_phy { <<
160 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
161 fsl,clkreq-unsupported; <<
162 clocks = <&pcie0_refclk>; <<
163 clock-names = "ref"; <<
164 status = "okay"; <<
165 }; <<
166 <<
167 &pcie0 { <<
168 pinctrl-names = "default"; <<
169 pinctrl-0 = <&pinctrl_pcie0>; <<
170 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW <<
171 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <<
172 <&clk IMX8MM_CLK_PCIE1_AUX>; <<
173 assigned-clocks = <&clk IMX8MM_CLK_PCI <<
174 <&clk IMX8MM_CLK_PCI <<
175 assigned-clock-rates = <10000000>, <25 <<
176 assigned-clock-parents = <&clk IMX8MM_ <<
177 <&clk IMX8MM_ <<
178 status = "okay"; <<
179 <<
180 pcie@0,0 { <<
181 reg = <0x0000 0 0 0 0>; <<
182 device_type = "pci"; <<
183 #address-cells = <3>; <<
184 #size-cells = <2>; <<
185 ranges; <<
186 <<
187 pcie@0,0 { <<
188 reg = <0x0000 0 0 0 0> <<
189 device_type = "pci"; <<
190 #address-cells = <3>; <<
191 #size-cells = <2>; <<
192 ranges; <<
193 <<
194 pcie@4,0 { <<
195 reg = <0x2000 <<
196 device_type = <<
197 #address-cells <<
198 #size-cells = <<
199 ranges; <<
200 <<
201 eth1: ethernet <<
202 reg = <<
203 #addre <<
204 #size- <<
205 ranges <<
206 <<
207 local- <<
208 }; <<
209 }; <<
210 }; <<
211 }; <<
212 }; <<
213 <<
214 /* off-board header */ 129 /* off-board header */
215 &sai3 { 130 &sai3 {
216 pinctrl-names = "default"; 131 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_sai3>; 132 pinctrl-0 = <&pinctrl_sai3>;
218 assigned-clocks = <&clk IMX8MM_CLK_SAI 133 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
219 assigned-clock-parents = <&clk IMX8MM_ 134 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
220 assigned-clock-rates = <24576000>; 135 assigned-clock-rates = <24576000>;
221 status = "okay"; 136 status = "okay";
222 }; 137 };
223 138
224 /* GPS */ 139 /* GPS */
225 &uart1 { 140 &uart1 {
226 pinctrl-names = "default"; 141 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>; 142 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay"; 143 status = "okay";
229 }; 144 };
230 145
231 /* bluetooth HCI */ 146 /* bluetooth HCI */
232 &uart3 { 147 &uart3 {
233 pinctrl-names = "default"; 148 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 149 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
235 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW> 150 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
236 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW> 151 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
237 status = "okay"; 152 status = "okay";
238 153
239 bluetooth { 154 bluetooth {
240 compatible = "brcm,bcm4330-bt" 155 compatible = "brcm,bcm4330-bt";
241 shutdown-gpios = <&gpio1 3 GPI 156 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
242 }; 157 };
243 }; 158 };
244 159
245 /* RS232 */ 160 /* RS232 */
246 &uart4 { 161 &uart4 {
247 pinctrl-names = "default"; 162 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart4>; 163 pinctrl-0 = <&pinctrl_uart4>;
249 status = "okay"; 164 status = "okay";
250 }; 165 };
251 166
252 &usbotg1 { 167 &usbotg1 {
253 dr_mode = "otg"; 168 dr_mode = "otg";
254 over-current-active-low; 169 over-current-active-low;
255 vbus-supply = <®_usb_otg1_vbus>; 170 vbus-supply = <®_usb_otg1_vbus>;
256 status = "okay"; 171 status = "okay";
257 }; 172 };
258 173
259 &usbotg2 { 174 &usbotg2 {
260 dr_mode = "host"; 175 dr_mode = "host";
261 disable-over-current; 176 disable-over-current;
262 vbus-supply = <®_usb_otg2_vbus>; 177 vbus-supply = <®_usb_otg2_vbus>;
263 status = "okay"; 178 status = "okay";
264 }; 179 };
265 180
266 /* SDIO WiFi */ 181 /* SDIO WiFi */
267 &usdhc1 { 182 &usdhc1 {
268 pinctrl-names = "default"; 183 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usdhc1>; 184 pinctrl-0 = <&pinctrl_usdhc1>;
270 bus-width = <4>; 185 bus-width = <4>;
271 non-removable; 186 non-removable;
272 vmmc-supply = <®_wifi_en>; 187 vmmc-supply = <®_wifi_en>;
273 status = "okay"; 188 status = "okay";
274 }; 189 };
275 190
276 /* microSD */ 191 /* microSD */
277 &usdhc2 { 192 &usdhc2 {
278 pinctrl-names = "default", "state_100m 193 pinctrl-names = "default", "state_100mhz", "state_200mhz";
279 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 194 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
280 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 195 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
281 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 196 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
282 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 197 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
283 bus-width = <4>; 198 bus-width = <4>;
284 vmmc-supply = <®_3p3v>; 199 vmmc-supply = <®_3p3v>;
285 status = "okay"; 200 status = "okay";
286 }; 201 };
287 202
288 &iomuxc { 203 &iomuxc {
289 pinctrl-names = "default"; 204 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_hog>; 205 pinctrl-0 = <&pinctrl_hog>;
291 206
292 pinctrl_hog: hoggrp { 207 pinctrl_hog: hoggrp {
293 fsl,pins = < 208 fsl,pins = <
294 MX8MM_IOMUXC_SPDIF_TX_ 209 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
295 MX8MM_IOMUXC_GPIO1_IO0 210 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
296 MX8MM_IOMUXC_SAI1_RXD5 211 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
297 MX8MM_IOMUXC_GPIO1_IO0 212 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
298 MX8MM_IOMUXC_GPIO1_IO0 213 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
299 MX8MM_IOMUXC_GPIO1_IO0 214 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
300 MX8MM_IOMUXC_SAI1_RXFS 215 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
301 MX8MM_IOMUXC_SAI1_RXD0 216 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
302 >; 217 >;
303 }; 218 };
304 219
305 pinctrl_accel: accelgrp { 220 pinctrl_accel: accelgrp {
306 fsl,pins = < 221 fsl,pins = <
307 MX8MM_IOMUXC_SAI1_RXD3 222 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
308 >; 223 >;
309 }; 224 };
310 225
311 pinctrl_bten: btengrp { 226 pinctrl_bten: btengrp {
312 fsl,pins = < 227 fsl,pins = <
313 MX8MM_IOMUXC_GPIO1_IO0 228 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
314 >; 229 >;
315 }; 230 };
316 231
317 pinctrl_gpio_leds: gpioledgrp { 232 pinctrl_gpio_leds: gpioledgrp {
318 fsl,pins = < 233 fsl,pins = <
319 MX8MM_IOMUXC_SPDIF_EXT 234 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
320 MX8MM_IOMUXC_SPDIF_RX_ 235 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
321 >; 236 >;
322 }; 237 };
323 238
324 pinctrl_i2c3: i2c3grp { 239 pinctrl_i2c3: i2c3grp {
325 fsl,pins = < 240 fsl,pins = <
326 MX8MM_IOMUXC_I2C3_SCL_ 241 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
327 MX8MM_IOMUXC_I2C3_SDA_ 242 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
328 >; 243 >;
329 }; 244 };
330 245
331 pinctrl_pcie0: pcie0grp { <<
332 fsl,pins = < <<
333 MX8MM_IOMUXC_SAI1_RXD4 <<
334 >; <<
335 }; <<
336 <<
337 pinctrl_pps: ppsgrp { 246 pinctrl_pps: ppsgrp {
338 fsl,pins = < 247 fsl,pins = <
339 MX8MM_IOMUXC_GPIO1_IO1 248 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
340 >; 249 >;
341 }; 250 };
342 251
343 pinctrl_reg_wl: regwlgrp { 252 pinctrl_reg_wl: regwlgrp {
344 fsl,pins = < 253 fsl,pins = <
345 MX8MM_IOMUXC_GPIO1_IO0 254 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
346 >; 255 >;
347 }; 256 };
348 257
349 pinctrl_reg_usb1_en: regusb1grp { 258 pinctrl_reg_usb1_en: regusb1grp {
350 fsl,pins = < 259 fsl,pins = <
351 MX8MM_IOMUXC_GPIO1_IO1 260 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
352 MX8MM_IOMUXC_GPIO1_IO1 261 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
353 >; 262 >;
354 }; 263 };
355 264
356 pinctrl_reg_usb2_en: regusb2grp { 265 pinctrl_reg_usb2_en: regusb2grp {
357 fsl,pins = < 266 fsl,pins = <
358 MX8MM_IOMUXC_GPIO1_IO0 267 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
359 >; 268 >;
360 }; 269 };
361 270
362 pinctrl_sai3: sai3grp { 271 pinctrl_sai3: sai3grp {
363 fsl,pins = < 272 fsl,pins = <
364 MX8MM_IOMUXC_SAI3_TXFS 273 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
365 MX8MM_IOMUXC_SAI3_TXC_ 274 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
366 MX8MM_IOMUXC_SAI3_MCLK 275 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
367 MX8MM_IOMUXC_SAI3_TXD_ 276 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
368 MX8MM_IOMUXC_SAI3_RXD_ 277 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
369 >; 278 >;
370 }; 279 };
371 280
372 pinctrl_spi2: spi2grp { 281 pinctrl_spi2: spi2grp {
373 fsl,pins = < 282 fsl,pins = <
374 MX8MM_IOMUXC_ECSPI2_SC 283 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
375 MX8MM_IOMUXC_ECSPI2_MO 284 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
376 MX8MM_IOMUXC_ECSPI2_MI 285 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
377 MX8MM_IOMUXC_ECSPI2_SS 286 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
378 MX8MM_IOMUXC_GPIO1_IO1 <<
379 >; 287 >;
380 }; 288 };
381 289
382 pinctrl_uart1: uart1grp { 290 pinctrl_uart1: uart1grp {
383 fsl,pins = < 291 fsl,pins = <
384 MX8MM_IOMUXC_UART1_RXD 292 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
385 MX8MM_IOMUXC_UART1_TXD 293 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
386 >; 294 >;
387 }; 295 };
388 296
389 pinctrl_uart3: uart3grp { 297 pinctrl_uart3: uart3grp {
390 fsl,pins = < 298 fsl,pins = <
391 MX8MM_IOMUXC_UART3_RXD 299 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
392 MX8MM_IOMUXC_UART3_TXD 300 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
393 MX8MM_IOMUXC_ECSPI1_MI 301 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
394 MX8MM_IOMUXC_ECSPI1_SS 302 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
395 >; 303 >;
396 }; 304 };
397 305
398 pinctrl_uart4: uart4grp { 306 pinctrl_uart4: uart4grp {
399 fsl,pins = < 307 fsl,pins = <
400 MX8MM_IOMUXC_UART4_RXD 308 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
401 MX8MM_IOMUXC_UART4_TXD 309 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
402 >; 310 >;
403 }; 311 };
404 312
405 pinctrl_usdhc1: usdhc1grp { 313 pinctrl_usdhc1: usdhc1grp {
406 fsl,pins = < 314 fsl,pins = <
407 MX8MM_IOMUXC_SD1_CLK_U 315 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
408 MX8MM_IOMUXC_SD1_CMD_U 316 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
409 MX8MM_IOMUXC_SD1_DATA0 317 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
410 MX8MM_IOMUXC_SD1_DATA1 318 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
411 MX8MM_IOMUXC_SD1_DATA2 319 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
412 MX8MM_IOMUXC_SD1_DATA3 320 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
413 >; 321 >;
414 }; 322 };
415 323
416 pinctrl_usdhc2: usdhc2grp { 324 pinctrl_usdhc2: usdhc2grp {
417 fsl,pins = < 325 fsl,pins = <
418 MX8MM_IOMUXC_SD2_CLK_U 326 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
419 MX8MM_IOMUXC_SD2_CMD_U 327 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
420 MX8MM_IOMUXC_SD2_DATA0 328 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
421 MX8MM_IOMUXC_SD2_DATA1 329 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
422 MX8MM_IOMUXC_SD2_DATA2 330 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
423 MX8MM_IOMUXC_SD2_DATA3 331 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
424 >; 332 >;
425 }; 333 };
426 334
427 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 335 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
428 fsl,pins = < 336 fsl,pins = <
429 MX8MM_IOMUXC_SD2_CLK_U 337 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
430 MX8MM_IOMUXC_SD2_CMD_U 338 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
431 MX8MM_IOMUXC_SD2_DATA0 339 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
432 MX8MM_IOMUXC_SD2_DATA1 340 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
433 MX8MM_IOMUXC_SD2_DATA2 341 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
434 MX8MM_IOMUXC_SD2_DATA3 342 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
435 >; 343 >;
436 }; 344 };
437 345
438 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 346 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
439 fsl,pins = < 347 fsl,pins = <
440 MX8MM_IOMUXC_SD2_CLK_U 348 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
441 MX8MM_IOMUXC_SD2_CMD_U 349 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
442 MX8MM_IOMUXC_SD2_DATA0 350 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
443 MX8MM_IOMUXC_SD2_DATA1 351 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
444 MX8MM_IOMUXC_SD2_DATA2 352 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
445 MX8MM_IOMUXC_SD2_DATA3 353 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
446 >; 354 >;
447 }; 355 };
448 356
449 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 357 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
450 fsl,pins = < 358 fsl,pins = <
451 MX8MM_IOMUXC_SD2_CD_B_ 359 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
452 MX8MM_IOMUXC_SD2_RESET 360 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
453 MX8MM_IOMUXC_GPIO1_IO0 361 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
454 >; 362 >;
455 }; 363 };
456 }; 364 };
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