1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9
10 / {
11 aliases {
12 ethernet1 = ð1;
13 usb0 = &usbotg1;
14 usb1 = &usbotg2;
15 };
16
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_led
21
22 led-0 {
23 function = LED_FUNCTIO
24 color = <LED_COLOR_ID_
25 gpios = <&gpio5 5 GPIO
26 default-state = "on";
27 linux,default-trigger
28 };
29
30 led-1 {
31 function = LED_FUNCTIO
32 color = <LED_COLOR_ID_
33 gpios = <&gpio5 4 GPIO
34 default-state = "off";
35 };
36 };
37
38 pcie0_refclk: pcie0-refclk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <100000000>;
42 };
43
44 pps {
45 compatible = "pps-gpio";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE
49 status = "okay";
50 };
51
52 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed"
54 regulator-name = "1P8V";
55 regulator-min-microvolt = <180
56 regulator-max-microvolt = <180
57 regulator-always-on;
58 };
59
60 reg_3p3v: regulator-3p3v {
61 compatible = "regulator-fixed"
62 regulator-name = "3P3V";
63 regulator-min-microvolt = <330
64 regulator-max-microvolt = <330
65 regulator-always-on;
66 };
67
68 reg_usb_otg1_vbus: regulator-usb-otg1
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_reg_usb1
71 compatible = "regulator-fixed"
72 regulator-name = "usb_otg1_vbu
73 gpio = <&gpio1 12 GPIO_ACTIVE_
74 enable-active-high;
75 regulator-min-microvolt = <500
76 regulator-max-microvolt = <500
77 };
78
79 reg_usb_otg2_vbus: regulator-usb-otg2
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_reg_usb2
82 compatible = "regulator-fixed"
83 regulator-name = "usb_otg2_vbu
84 gpio = <&gpio1 8 GPIO_ACTIVE_H
85 enable-active-high;
86 regulator-min-microvolt = <500
87 regulator-max-microvolt = <500
88 };
89
90 reg_wifi_en: regulator-wifi-en {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_reg_wl>;
93 compatible = "regulator-fixed"
94 regulator-name = "wl";
95 gpio = <&gpio1 5 GPIO_ACTIVE_H
96 startup-delay-us = <100>;
97 enable-active-high;
98 regulator-min-microvolt = <330
99 regulator-max-microvolt = <330
100 };
101 };
102
103 /* off-board header */
104 &ecspi2 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi2>;
107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
108 <&gpio1 10 GPIO_ACTIVE_LOW>
109 status = "okay";
110
111 tpm@1 {
112 compatible = "atmel,attpm20p",
113 reg = <0x1>;
114 spi-max-frequency = <36000000>
115 };
116 };
117
118 &gpio1 {
119 gpio-line-names = "rs485_term", "mipi_
120 "", "", "pci_usb_sel", "dio0",
121 "", "dio1", "", "", "", "", ""
122 "", "", "", "", "", "", "", ""
123 "", "", "", "", "", "", "", ""
124 };
125
126 &gpio4 {
127 gpio-line-names = "rs485_en", "mipi_gp
128 "mipi_gpio1", "", "", "pci_wdi
129 "", "", "", "", "", "", "", ""
130 "", "", "", "", "", "", "", ""
131 "", "", "", "", "", "", "", ""
132 };
133
134 &i2c2 {
135 clock-frequency = <400000>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_i2c2>;
138 status = "okay";
139
140 accelerometer@19 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_accel>;
143 compatible = "st,lis2de12";
144 reg = <0x19>;
145 st,drdy-int-pin = <1>;
146 interrupt-parent = <&gpio4>;
147 interrupts = <5 IRQ_TYPE_LEVEL
148 };
149 };
150
151 /* off-board header */
152 &i2c3 {
153 clock-frequency = <400000>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c3>;
156 status = "okay";
157 };
158
159 &pcie_phy {
160 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
161 fsl,clkreq-unsupported;
162 clocks = <&pcie0_refclk>;
163 clock-names = "ref";
164 status = "okay";
165 };
166
167 &pcie0 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_pcie0>;
170 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW
171 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
172 <&clk IMX8MM_CLK_PCIE1_AUX>;
173 assigned-clocks = <&clk IMX8MM_CLK_PCI
174 <&clk IMX8MM_CLK_PCI
175 assigned-clock-rates = <10000000>, <25
176 assigned-clock-parents = <&clk IMX8MM_
177 <&clk IMX8MM_
178 status = "okay";
179
180 pcie@0,0 {
181 reg = <0x0000 0 0 0 0>;
182 device_type = "pci";
183 #address-cells = <3>;
184 #size-cells = <2>;
185 ranges;
186
187 pcie@0,0 {
188 reg = <0x0000 0 0 0 0>
189 device_type = "pci";
190 #address-cells = <3>;
191 #size-cells = <2>;
192 ranges;
193
194 pcie@4,0 {
195 reg = <0x2000
196 device_type =
197 #address-cells
198 #size-cells =
199 ranges;
200
201 eth1: ethernet
202 reg =
203 #addre
204 #size-
205 ranges
206
207 local-
208 };
209 };
210 };
211 };
212 };
213
214 /* off-board header */
215 &sai3 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_sai3>;
218 assigned-clocks = <&clk IMX8MM_CLK_SAI
219 assigned-clock-parents = <&clk IMX8MM_
220 assigned-clock-rates = <24576000>;
221 status = "okay";
222 };
223
224 /* GPS */
225 &uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay";
229 };
230
231 /* bluetooth HCI */
232 &uart3 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart3>, <&pinctr
235 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>
236 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>
237 status = "okay";
238
239 bluetooth {
240 compatible = "brcm,bcm4330-bt"
241 shutdown-gpios = <&gpio1 3 GPI
242 };
243 };
244
245 /* RS232 */
246 &uart4 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart4>;
249 status = "okay";
250 };
251
252 &usbotg1 {
253 dr_mode = "otg";
254 over-current-active-low;
255 vbus-supply = <®_usb_otg1_vbus>;
256 status = "okay";
257 };
258
259 &usbotg2 {
260 dr_mode = "host";
261 disable-over-current;
262 vbus-supply = <®_usb_otg2_vbus>;
263 status = "okay";
264 };
265
266 /* SDIO WiFi */
267 &usdhc1 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usdhc1>;
270 bus-width = <4>;
271 non-removable;
272 vmmc-supply = <®_wifi_en>;
273 status = "okay";
274 };
275
276 /* microSD */
277 &usdhc2 {
278 pinctrl-names = "default", "state_100m
279 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
280 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
281 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
282 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
283 bus-width = <4>;
284 vmmc-supply = <®_3p3v>;
285 status = "okay";
286 };
287
288 &iomuxc {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_hog>;
291
292 pinctrl_hog: hoggrp {
293 fsl,pins = <
294 MX8MM_IOMUXC_SPDIF_TX_
295 MX8MM_IOMUXC_GPIO1_IO0
296 MX8MM_IOMUXC_SAI1_RXD5
297 MX8MM_IOMUXC_GPIO1_IO0
298 MX8MM_IOMUXC_GPIO1_IO0
299 MX8MM_IOMUXC_GPIO1_IO0
300 MX8MM_IOMUXC_SAI1_RXFS
301 MX8MM_IOMUXC_SAI1_RXD0
302 >;
303 };
304
305 pinctrl_accel: accelgrp {
306 fsl,pins = <
307 MX8MM_IOMUXC_SAI1_RXD3
308 >;
309 };
310
311 pinctrl_bten: btengrp {
312 fsl,pins = <
313 MX8MM_IOMUXC_GPIO1_IO0
314 >;
315 };
316
317 pinctrl_gpio_leds: gpioledgrp {
318 fsl,pins = <
319 MX8MM_IOMUXC_SPDIF_EXT
320 MX8MM_IOMUXC_SPDIF_RX_
321 >;
322 };
323
324 pinctrl_i2c3: i2c3grp {
325 fsl,pins = <
326 MX8MM_IOMUXC_I2C3_SCL_
327 MX8MM_IOMUXC_I2C3_SDA_
328 >;
329 };
330
331 pinctrl_pcie0: pcie0grp {
332 fsl,pins = <
333 MX8MM_IOMUXC_SAI1_RXD4
334 >;
335 };
336
337 pinctrl_pps: ppsgrp {
338 fsl,pins = <
339 MX8MM_IOMUXC_GPIO1_IO1
340 >;
341 };
342
343 pinctrl_reg_wl: regwlgrp {
344 fsl,pins = <
345 MX8MM_IOMUXC_GPIO1_IO0
346 >;
347 };
348
349 pinctrl_reg_usb1_en: regusb1grp {
350 fsl,pins = <
351 MX8MM_IOMUXC_GPIO1_IO1
352 MX8MM_IOMUXC_GPIO1_IO1
353 >;
354 };
355
356 pinctrl_reg_usb2_en: regusb2grp {
357 fsl,pins = <
358 MX8MM_IOMUXC_GPIO1_IO0
359 >;
360 };
361
362 pinctrl_sai3: sai3grp {
363 fsl,pins = <
364 MX8MM_IOMUXC_SAI3_TXFS
365 MX8MM_IOMUXC_SAI3_TXC_
366 MX8MM_IOMUXC_SAI3_MCLK
367 MX8MM_IOMUXC_SAI3_TXD_
368 MX8MM_IOMUXC_SAI3_RXD_
369 >;
370 };
371
372 pinctrl_spi2: spi2grp {
373 fsl,pins = <
374 MX8MM_IOMUXC_ECSPI2_SC
375 MX8MM_IOMUXC_ECSPI2_MO
376 MX8MM_IOMUXC_ECSPI2_MI
377 MX8MM_IOMUXC_ECSPI2_SS
378 MX8MM_IOMUXC_GPIO1_IO1
379 >;
380 };
381
382 pinctrl_uart1: uart1grp {
383 fsl,pins = <
384 MX8MM_IOMUXC_UART1_RXD
385 MX8MM_IOMUXC_UART1_TXD
386 >;
387 };
388
389 pinctrl_uart3: uart3grp {
390 fsl,pins = <
391 MX8MM_IOMUXC_UART3_RXD
392 MX8MM_IOMUXC_UART3_TXD
393 MX8MM_IOMUXC_ECSPI1_MI
394 MX8MM_IOMUXC_ECSPI1_SS
395 >;
396 };
397
398 pinctrl_uart4: uart4grp {
399 fsl,pins = <
400 MX8MM_IOMUXC_UART4_RXD
401 MX8MM_IOMUXC_UART4_TXD
402 >;
403 };
404
405 pinctrl_usdhc1: usdhc1grp {
406 fsl,pins = <
407 MX8MM_IOMUXC_SD1_CLK_U
408 MX8MM_IOMUXC_SD1_CMD_U
409 MX8MM_IOMUXC_SD1_DATA0
410 MX8MM_IOMUXC_SD1_DATA1
411 MX8MM_IOMUXC_SD1_DATA2
412 MX8MM_IOMUXC_SD1_DATA3
413 >;
414 };
415
416 pinctrl_usdhc2: usdhc2grp {
417 fsl,pins = <
418 MX8MM_IOMUXC_SD2_CLK_U
419 MX8MM_IOMUXC_SD2_CMD_U
420 MX8MM_IOMUXC_SD2_DATA0
421 MX8MM_IOMUXC_SD2_DATA1
422 MX8MM_IOMUXC_SD2_DATA2
423 MX8MM_IOMUXC_SD2_DATA3
424 >;
425 };
426
427 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
428 fsl,pins = <
429 MX8MM_IOMUXC_SD2_CLK_U
430 MX8MM_IOMUXC_SD2_CMD_U
431 MX8MM_IOMUXC_SD2_DATA0
432 MX8MM_IOMUXC_SD2_DATA1
433 MX8MM_IOMUXC_SD2_DATA2
434 MX8MM_IOMUXC_SD2_DATA3
435 >;
436 };
437
438 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
439 fsl,pins = <
440 MX8MM_IOMUXC_SD2_CLK_U
441 MX8MM_IOMUXC_SD2_CMD_U
442 MX8MM_IOMUXC_SD2_DATA0
443 MX8MM_IOMUXC_SD2_DATA1
444 MX8MM_IOMUXC_SD2_DATA2
445 MX8MM_IOMUXC_SD2_DATA3
446 >;
447 };
448
449 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
450 fsl,pins = <
451 MX8MM_IOMUXC_SD2_CD_B_
452 MX8MM_IOMUXC_SD2_RESET
453 MX8MM_IOMUXC_GPIO1_IO0
454 >;
455 };
456 };
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