1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2020 Gateworks Corporation 3 * Copyright 2020 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 9
10 / { 10 / {
11 aliases { 11 aliases {
12 ethernet1 = ð1; 12 ethernet1 = ð1;
13 usb0 = &usbotg1; 13 usb0 = &usbotg1;
14 usb1 = &usbotg2; 14 usb1 = &usbotg2;
15 }; 15 };
16 16
17 led-controller { 17 led-controller {
18 compatible = "gpio-leds"; 18 compatible = "gpio-leds";
19 pinctrl-names = "default"; 19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_led 20 pinctrl-0 = <&pinctrl_gpio_leds>;
21 21
22 led-0 { 22 led-0 {
23 function = LED_FUNCTIO 23 function = LED_FUNCTION_STATUS;
24 color = <LED_COLOR_ID_ 24 color = <LED_COLOR_ID_GREEN>;
25 gpios = <&gpio5 5 GPIO 25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26 default-state = "on"; 26 default-state = "on";
27 linux,default-trigger 27 linux,default-trigger = "heartbeat";
28 }; 28 };
29 29
30 led-1 { 30 led-1 {
31 function = LED_FUNCTIO 31 function = LED_FUNCTION_STATUS;
32 color = <LED_COLOR_ID_ 32 color = <LED_COLOR_ID_RED>;
33 gpios = <&gpio5 4 GPIO 33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34 default-state = "off"; 34 default-state = "off";
35 }; 35 };
36 }; 36 };
37 37
38 pcie0_refclk: pcie0-refclk { 38 pcie0_refclk: pcie0-refclk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 clock-frequency = <100000000>; 41 clock-frequency = <100000000>;
42 }; 42 };
43 43
44 pps { 44 pps {
45 compatible = "pps-gpio"; 45 compatible = "pps-gpio";
46 pinctrl-names = "default"; 46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>; 47 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE 48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49 status = "okay"; 49 status = "okay";
50 }; 50 };
51 51
52 reg_1p8v: regulator-1p8v { 52 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
54 regulator-name = "1P8V"; 54 regulator-name = "1P8V";
55 regulator-min-microvolt = <180 55 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <180 56 regulator-max-microvolt = <1800000>;
57 regulator-always-on; 57 regulator-always-on;
58 }; 58 };
59 59
60 reg_3p3v: regulator-3p3v { 60 reg_3p3v: regulator-3p3v {
61 compatible = "regulator-fixed" 61 compatible = "regulator-fixed";
62 regulator-name = "3P3V"; 62 regulator-name = "3P3V";
63 regulator-min-microvolt = <330 63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <330 64 regulator-max-microvolt = <3300000>;
65 regulator-always-on; 65 regulator-always-on;
66 }; 66 };
67 67
68 reg_usb_otg1_vbus: regulator-usb-otg1 68 reg_usb_otg1_vbus: regulator-usb-otg1 {
69 pinctrl-names = "default"; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_reg_usb1 70 pinctrl-0 = <&pinctrl_reg_usb1_en>;
71 compatible = "regulator-fixed" 71 compatible = "regulator-fixed";
72 regulator-name = "usb_otg1_vbu 72 regulator-name = "usb_otg1_vbus";
73 gpio = <&gpio1 12 GPIO_ACTIVE_ 73 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
74 enable-active-high; 74 enable-active-high;
75 regulator-min-microvolt = <500 75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <500 76 regulator-max-microvolt = <5000000>;
77 }; 77 };
78 78
79 reg_usb_otg2_vbus: regulator-usb-otg2 79 reg_usb_otg2_vbus: regulator-usb-otg2 {
80 pinctrl-names = "default"; 80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_reg_usb2 81 pinctrl-0 = <&pinctrl_reg_usb2_en>;
82 compatible = "regulator-fixed" 82 compatible = "regulator-fixed";
83 regulator-name = "usb_otg2_vbu 83 regulator-name = "usb_otg2_vbus";
84 gpio = <&gpio1 8 GPIO_ACTIVE_H 84 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
85 enable-active-high; 85 enable-active-high;
86 regulator-min-microvolt = <500 86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <500 87 regulator-max-microvolt = <5000000>;
88 }; 88 };
89 89
90 reg_wifi_en: regulator-wifi-en { 90 reg_wifi_en: regulator-wifi-en {
91 pinctrl-names = "default"; 91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_reg_wl>; 92 pinctrl-0 = <&pinctrl_reg_wl>;
93 compatible = "regulator-fixed" 93 compatible = "regulator-fixed";
94 regulator-name = "wl"; 94 regulator-name = "wl";
95 gpio = <&gpio1 5 GPIO_ACTIVE_H 95 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <100>; 96 startup-delay-us = <100>;
97 enable-active-high; 97 enable-active-high;
98 regulator-min-microvolt = <330 98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <330 99 regulator-max-microvolt = <3300000>;
100 }; 100 };
101 }; 101 };
102 102
103 /* off-board header */ 103 /* off-board header */
104 &ecspi2 { 104 &ecspi2 {
105 pinctrl-names = "default"; 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi2>; 106 pinctrl-0 = <&pinctrl_spi2>;
107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> !! 107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
108 <&gpio1 10 GPIO_ACTIVE_LOW> <<
109 status = "okay"; 108 status = "okay";
110 <<
111 tpm@1 { <<
112 compatible = "atmel,attpm20p", <<
113 reg = <0x1>; <<
114 spi-max-frequency = <36000000> <<
115 }; <<
116 }; 109 };
117 110
118 &gpio1 { 111 &gpio1 {
119 gpio-line-names = "rs485_term", "mipi_ 112 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
120 "", "", "pci_usb_sel", "dio0", 113 "", "", "pci_usb_sel", "dio0",
121 "", "dio1", "", "", "", "", "" 114 "", "dio1", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "" 115 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "" 116 "", "", "", "", "", "", "", "";
124 }; 117 };
125 118
126 &gpio4 { 119 &gpio4 {
127 gpio-line-names = "rs485_en", "mipi_gp 120 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
128 "mipi_gpio1", "", "", "pci_wdi 121 "mipi_gpio1", "", "", "pci_wdis#",
129 "", "", "", "", "", "", "", "" 122 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "" 123 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "" 124 "", "", "", "", "", "", "", "";
132 }; 125 };
133 126
134 &i2c2 { 127 &i2c2 {
135 clock-frequency = <400000>; 128 clock-frequency = <400000>;
136 pinctrl-names = "default"; 129 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_i2c2>; 130 pinctrl-0 = <&pinctrl_i2c2>;
138 status = "okay"; 131 status = "okay";
139 132
140 accelerometer@19 { 133 accelerometer@19 {
141 pinctrl-names = "default"; 134 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_accel>; 135 pinctrl-0 = <&pinctrl_accel>;
143 compatible = "st,lis2de12"; 136 compatible = "st,lis2de12";
144 reg = <0x19>; 137 reg = <0x19>;
145 st,drdy-int-pin = <1>; 138 st,drdy-int-pin = <1>;
146 interrupt-parent = <&gpio4>; 139 interrupt-parent = <&gpio4>;
147 interrupts = <5 IRQ_TYPE_LEVEL 140 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> 141 interrupt-names = "INT1";
148 }; 142 };
149 }; 143 };
150 144
151 /* off-board header */ 145 /* off-board header */
152 &i2c3 { 146 &i2c3 {
153 clock-frequency = <400000>; 147 clock-frequency = <400000>;
154 pinctrl-names = "default"; 148 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c3>; 149 pinctrl-0 = <&pinctrl_i2c3>;
156 status = "okay"; 150 status = "okay";
157 }; 151 };
158 152
159 &pcie_phy { 153 &pcie_phy {
160 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 154 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
161 fsl,clkreq-unsupported; 155 fsl,clkreq-unsupported;
162 clocks = <&pcie0_refclk>; 156 clocks = <&pcie0_refclk>;
163 clock-names = "ref"; 157 clock-names = "ref";
164 status = "okay"; 158 status = "okay";
165 }; 159 };
166 160
167 &pcie0 { 161 &pcie0 {
168 pinctrl-names = "default"; 162 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_pcie0>; 163 pinctrl-0 = <&pinctrl_pcie0>;
170 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW 164 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
171 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 165 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
172 <&clk IMX8MM_CLK_PCIE1_AUX>; 166 <&clk IMX8MM_CLK_PCIE1_AUX>;
173 assigned-clocks = <&clk IMX8MM_CLK_PCI 167 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
174 <&clk IMX8MM_CLK_PCI 168 <&clk IMX8MM_CLK_PCIE1_CTRL>;
175 assigned-clock-rates = <10000000>, <25 169 assigned-clock-rates = <10000000>, <250000000>;
176 assigned-clock-parents = <&clk IMX8MM_ 170 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
177 <&clk IMX8MM_ 171 <&clk IMX8MM_SYS_PLL2_250M>;
178 status = "okay"; 172 status = "okay";
179 173
180 pcie@0,0 { 174 pcie@0,0 {
181 reg = <0x0000 0 0 0 0>; 175 reg = <0x0000 0 0 0 0>;
182 device_type = "pci"; !! 176 #address-cells = <1>;
183 #address-cells = <3>; !! 177 #size-cells = <0>;
184 #size-cells = <2>; <<
185 ranges; <<
186 178
187 pcie@0,0 { !! 179 pcie@1,0 {
188 reg = <0x0000 0 0 0 0> 180 reg = <0x0000 0 0 0 0>;
189 device_type = "pci"; !! 181 #address-cells = <1>;
190 #address-cells = <3>; !! 182 #size-cells = <0>;
191 #size-cells = <2>; <<
192 ranges; <<
193 183
194 pcie@4,0 { !! 184 pcie@2,4 {
195 reg = <0x2000 185 reg = <0x2000 0 0 0 0>;
196 device_type = !! 186 #address-cells = <1>;
197 #address-cells !! 187 #size-cells = <0>;
198 #size-cells = <<
199 ranges; <<
200 188
201 eth1: ethernet !! 189 eth1: pcie@6,0 {
202 reg = 190 reg = <0x0000 0 0 0 0>;
203 #addre !! 191 #address-cells = <1>;
204 #size- !! 192 #size-cells = <0>;
205 ranges <<
206 193
207 local- 194 local-mac-address = [00 00 00 00 00 00];
208 }; 195 };
209 }; 196 };
210 }; 197 };
211 }; 198 };
212 }; 199 };
213 200
214 /* off-board header */ 201 /* off-board header */
215 &sai3 { 202 &sai3 {
216 pinctrl-names = "default"; 203 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_sai3>; 204 pinctrl-0 = <&pinctrl_sai3>;
218 assigned-clocks = <&clk IMX8MM_CLK_SAI 205 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
219 assigned-clock-parents = <&clk IMX8MM_ 206 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
220 assigned-clock-rates = <24576000>; 207 assigned-clock-rates = <24576000>;
221 status = "okay"; 208 status = "okay";
222 }; 209 };
223 210
224 /* GPS */ 211 /* GPS */
225 &uart1 { 212 &uart1 {
226 pinctrl-names = "default"; 213 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>; 214 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay"; 215 status = "okay";
229 }; 216 };
230 217
231 /* bluetooth HCI */ 218 /* bluetooth HCI */
232 &uart3 { 219 &uart3 {
233 pinctrl-names = "default"; 220 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 221 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
235 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW> 222 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
236 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW> 223 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
237 status = "okay"; 224 status = "okay";
238 225
239 bluetooth { 226 bluetooth {
240 compatible = "brcm,bcm4330-bt" 227 compatible = "brcm,bcm4330-bt";
241 shutdown-gpios = <&gpio1 3 GPI 228 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
242 }; 229 };
243 }; 230 };
244 231
245 /* RS232 */ 232 /* RS232 */
246 &uart4 { 233 &uart4 {
247 pinctrl-names = "default"; 234 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart4>; 235 pinctrl-0 = <&pinctrl_uart4>;
249 status = "okay"; 236 status = "okay";
250 }; 237 };
251 238
252 &usbotg1 { 239 &usbotg1 {
253 dr_mode = "otg"; 240 dr_mode = "otg";
254 over-current-active-low; 241 over-current-active-low;
255 vbus-supply = <®_usb_otg1_vbus>; 242 vbus-supply = <®_usb_otg1_vbus>;
256 status = "okay"; 243 status = "okay";
257 }; 244 };
258 245
259 &usbotg2 { 246 &usbotg2 {
260 dr_mode = "host"; 247 dr_mode = "host";
261 disable-over-current; 248 disable-over-current;
262 vbus-supply = <®_usb_otg2_vbus>; 249 vbus-supply = <®_usb_otg2_vbus>;
263 status = "okay"; 250 status = "okay";
264 }; 251 };
265 252
266 /* SDIO WiFi */ 253 /* SDIO WiFi */
267 &usdhc1 { 254 &usdhc1 {
268 pinctrl-names = "default"; 255 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usdhc1>; 256 pinctrl-0 = <&pinctrl_usdhc1>;
270 bus-width = <4>; 257 bus-width = <4>;
271 non-removable; 258 non-removable;
272 vmmc-supply = <®_wifi_en>; 259 vmmc-supply = <®_wifi_en>;
273 status = "okay"; 260 status = "okay";
274 }; 261 };
275 262
276 /* microSD */ 263 /* microSD */
277 &usdhc2 { 264 &usdhc2 {
278 pinctrl-names = "default", "state_100m 265 pinctrl-names = "default", "state_100mhz", "state_200mhz";
279 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 266 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
280 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 267 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
281 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 268 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
282 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 269 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
283 bus-width = <4>; 270 bus-width = <4>;
284 vmmc-supply = <®_3p3v>; 271 vmmc-supply = <®_3p3v>;
285 status = "okay"; 272 status = "okay";
286 }; 273 };
287 274
288 &iomuxc { 275 &iomuxc {
289 pinctrl-names = "default"; 276 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_hog>; 277 pinctrl-0 = <&pinctrl_hog>;
291 278
292 pinctrl_hog: hoggrp { 279 pinctrl_hog: hoggrp {
293 fsl,pins = < 280 fsl,pins = <
294 MX8MM_IOMUXC_SPDIF_TX_ 281 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
295 MX8MM_IOMUXC_GPIO1_IO0 282 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
296 MX8MM_IOMUXC_SAI1_RXD5 283 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
297 MX8MM_IOMUXC_GPIO1_IO0 284 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
298 MX8MM_IOMUXC_GPIO1_IO0 285 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
299 MX8MM_IOMUXC_GPIO1_IO0 286 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
300 MX8MM_IOMUXC_SAI1_RXFS 287 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
301 MX8MM_IOMUXC_SAI1_RXD0 288 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
302 >; 289 >;
303 }; 290 };
304 291
305 pinctrl_accel: accelgrp { 292 pinctrl_accel: accelgrp {
306 fsl,pins = < 293 fsl,pins = <
307 MX8MM_IOMUXC_SAI1_RXD3 294 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
308 >; 295 >;
309 }; 296 };
310 297
311 pinctrl_bten: btengrp { 298 pinctrl_bten: btengrp {
312 fsl,pins = < 299 fsl,pins = <
313 MX8MM_IOMUXC_GPIO1_IO0 300 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
314 >; 301 >;
315 }; 302 };
316 303
317 pinctrl_gpio_leds: gpioledgrp { 304 pinctrl_gpio_leds: gpioledgrp {
318 fsl,pins = < 305 fsl,pins = <
319 MX8MM_IOMUXC_SPDIF_EXT 306 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
320 MX8MM_IOMUXC_SPDIF_RX_ 307 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
321 >; 308 >;
322 }; 309 };
323 310
324 pinctrl_i2c3: i2c3grp { 311 pinctrl_i2c3: i2c3grp {
325 fsl,pins = < 312 fsl,pins = <
326 MX8MM_IOMUXC_I2C3_SCL_ 313 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
327 MX8MM_IOMUXC_I2C3_SDA_ 314 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
328 >; 315 >;
329 }; 316 };
330 317
331 pinctrl_pcie0: pcie0grp { 318 pinctrl_pcie0: pcie0grp {
332 fsl,pins = < 319 fsl,pins = <
333 MX8MM_IOMUXC_SAI1_RXD4 320 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
334 >; 321 >;
335 }; 322 };
336 323
337 pinctrl_pps: ppsgrp { 324 pinctrl_pps: ppsgrp {
338 fsl,pins = < 325 fsl,pins = <
339 MX8MM_IOMUXC_GPIO1_IO1 326 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
340 >; 327 >;
341 }; 328 };
342 329
343 pinctrl_reg_wl: regwlgrp { 330 pinctrl_reg_wl: regwlgrp {
344 fsl,pins = < 331 fsl,pins = <
345 MX8MM_IOMUXC_GPIO1_IO0 332 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
346 >; 333 >;
347 }; 334 };
348 335
349 pinctrl_reg_usb1_en: regusb1grp { 336 pinctrl_reg_usb1_en: regusb1grp {
350 fsl,pins = < 337 fsl,pins = <
351 MX8MM_IOMUXC_GPIO1_IO1 338 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
352 MX8MM_IOMUXC_GPIO1_IO1 339 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
353 >; 340 >;
354 }; 341 };
355 342
356 pinctrl_reg_usb2_en: regusb2grp { 343 pinctrl_reg_usb2_en: regusb2grp {
357 fsl,pins = < 344 fsl,pins = <
358 MX8MM_IOMUXC_GPIO1_IO0 345 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
359 >; 346 >;
360 }; 347 };
361 348
362 pinctrl_sai3: sai3grp { 349 pinctrl_sai3: sai3grp {
363 fsl,pins = < 350 fsl,pins = <
364 MX8MM_IOMUXC_SAI3_TXFS 351 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
365 MX8MM_IOMUXC_SAI3_TXC_ 352 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
366 MX8MM_IOMUXC_SAI3_MCLK 353 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
367 MX8MM_IOMUXC_SAI3_TXD_ 354 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
368 MX8MM_IOMUXC_SAI3_RXD_ 355 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
369 >; 356 >;
370 }; 357 };
371 358
372 pinctrl_spi2: spi2grp { 359 pinctrl_spi2: spi2grp {
373 fsl,pins = < 360 fsl,pins = <
374 MX8MM_IOMUXC_ECSPI2_SC 361 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
375 MX8MM_IOMUXC_ECSPI2_MO 362 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
376 MX8MM_IOMUXC_ECSPI2_MI 363 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
377 MX8MM_IOMUXC_ECSPI2_SS 364 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
378 MX8MM_IOMUXC_GPIO1_IO1 <<
379 >; 365 >;
380 }; 366 };
381 367
382 pinctrl_uart1: uart1grp { 368 pinctrl_uart1: uart1grp {
383 fsl,pins = < 369 fsl,pins = <
384 MX8MM_IOMUXC_UART1_RXD 370 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
385 MX8MM_IOMUXC_UART1_TXD 371 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
386 >; 372 >;
387 }; 373 };
388 374
389 pinctrl_uart3: uart3grp { 375 pinctrl_uart3: uart3grp {
390 fsl,pins = < 376 fsl,pins = <
391 MX8MM_IOMUXC_UART3_RXD 377 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
392 MX8MM_IOMUXC_UART3_TXD 378 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
393 MX8MM_IOMUXC_ECSPI1_MI 379 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
394 MX8MM_IOMUXC_ECSPI1_SS 380 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
395 >; 381 >;
396 }; 382 };
397 383
398 pinctrl_uart4: uart4grp { 384 pinctrl_uart4: uart4grp {
399 fsl,pins = < 385 fsl,pins = <
400 MX8MM_IOMUXC_UART4_RXD 386 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
401 MX8MM_IOMUXC_UART4_TXD 387 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
402 >; 388 >;
403 }; 389 };
404 390
405 pinctrl_usdhc1: usdhc1grp { 391 pinctrl_usdhc1: usdhc1grp {
406 fsl,pins = < 392 fsl,pins = <
407 MX8MM_IOMUXC_SD1_CLK_U 393 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
408 MX8MM_IOMUXC_SD1_CMD_U 394 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
409 MX8MM_IOMUXC_SD1_DATA0 395 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
410 MX8MM_IOMUXC_SD1_DATA1 396 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
411 MX8MM_IOMUXC_SD1_DATA2 397 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
412 MX8MM_IOMUXC_SD1_DATA3 398 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
413 >; 399 >;
414 }; 400 };
415 401
416 pinctrl_usdhc2: usdhc2grp { 402 pinctrl_usdhc2: usdhc2grp {
417 fsl,pins = < 403 fsl,pins = <
418 MX8MM_IOMUXC_SD2_CLK_U 404 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
419 MX8MM_IOMUXC_SD2_CMD_U 405 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
420 MX8MM_IOMUXC_SD2_DATA0 406 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
421 MX8MM_IOMUXC_SD2_DATA1 407 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
422 MX8MM_IOMUXC_SD2_DATA2 408 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
423 MX8MM_IOMUXC_SD2_DATA3 409 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
424 >; 410 >;
425 }; 411 };
426 412
427 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 413 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
428 fsl,pins = < 414 fsl,pins = <
429 MX8MM_IOMUXC_SD2_CLK_U 415 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
430 MX8MM_IOMUXC_SD2_CMD_U 416 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
431 MX8MM_IOMUXC_SD2_DATA0 417 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
432 MX8MM_IOMUXC_SD2_DATA1 418 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
433 MX8MM_IOMUXC_SD2_DATA2 419 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
434 MX8MM_IOMUXC_SD2_DATA3 420 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
435 >; 421 >;
436 }; 422 };
437 423
438 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 424 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
439 fsl,pins = < 425 fsl,pins = <
440 MX8MM_IOMUXC_SD2_CLK_U 426 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
441 MX8MM_IOMUXC_SD2_CMD_U 427 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
442 MX8MM_IOMUXC_SD2_DATA0 428 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
443 MX8MM_IOMUXC_SD2_DATA1 429 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
444 MX8MM_IOMUXC_SD2_DATA2 430 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
445 MX8MM_IOMUXC_SD2_DATA3 431 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
446 >; 432 >;
447 }; 433 };
448 434
449 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 435 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
450 fsl,pins = < 436 fsl,pins = <
451 MX8MM_IOMUXC_SD2_CD_B_ 437 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
452 MX8MM_IOMUXC_SD2_RESET 438 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
453 MX8MM_IOMUXC_GPIO1_IO0 439 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
454 >; 440 >;
455 }; 441 };
456 }; 442 };
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