1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 13
14 #include "imx8mm.dtsi" 14 #include "imx8mm.dtsi"
15 15
16 / { 16 / {
17 model = "Gateworks Venice GW7902 i.MX8 17 model = "Gateworks Venice GW7902 i.MX8MM board";
18 compatible = "gw,imx8mm-gw7902", "fsl, 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19 19
20 aliases { 20 aliases {
21 ethernet1 = ð1; 21 ethernet1 = ð1;
22 usb0 = &usbotg1; 22 usb0 = &usbotg1;
23 usb1 = &usbotg2; 23 usb1 = &usbotg2;
24 }; 24 };
25 25
26 chosen { 26 chosen {
27 stdout-path = &uart2; 27 stdout-path = &uart2;
28 }; 28 };
29 29
30 memory@40000000 { 30 memory@40000000 {
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000 0 0x8000 32 reg = <0x0 0x40000000 0 0x80000000>;
33 }; 33 };
34 34
35 can20m: can20m { 35 can20m: can20m {
36 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
37 #clock-cells = <0>; 37 #clock-cells = <0>;
38 clock-frequency = <20000000>; 38 clock-frequency = <20000000>;
39 clock-output-names = "can20m"; 39 clock-output-names = "can20m";
40 }; 40 };
41 41
42 gpio-keys { 42 gpio-keys {
43 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
44 44
45 key-user-pb { 45 key-user-pb {
46 label = "user_pb"; 46 label = "user_pb";
47 gpios = <&gpio 2 GPIO_ 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48 linux,code = <BTN_0>; 48 linux,code = <BTN_0>;
49 }; 49 };
50 50
51 key-user-pb1x { 51 key-user-pb1x {
52 label = "user_pb1x"; 52 label = "user_pb1x";
53 linux,code = <BTN_1>; 53 linux,code = <BTN_1>;
54 interrupt-parent = <&g 54 interrupt-parent = <&gsc>;
55 interrupts = <0>; 55 interrupts = <0>;
56 }; 56 };
57 57
58 key-erased { 58 key-erased {
59 label = "key_erased"; 59 label = "key_erased";
60 linux,code = <BTN_2>; 60 linux,code = <BTN_2>;
61 interrupt-parent = <&g 61 interrupt-parent = <&gsc>;
62 interrupts = <1>; 62 interrupts = <1>;
63 }; 63 };
64 64
65 key-eeprom-wp { 65 key-eeprom-wp {
66 label = "eeprom_wp"; 66 label = "eeprom_wp";
67 linux,code = <BTN_3>; 67 linux,code = <BTN_3>;
68 interrupt-parent = <&g 68 interrupt-parent = <&gsc>;
69 interrupts = <2>; 69 interrupts = <2>;
70 }; 70 };
71 71
72 key-tamper { 72 key-tamper {
73 label = "tamper"; 73 label = "tamper";
74 linux,code = <BTN_4>; 74 linux,code = <BTN_4>;
75 interrupt-parent = <&g 75 interrupt-parent = <&gsc>;
76 interrupts = <5>; 76 interrupts = <5>;
77 }; 77 };
78 78
79 switch-hold { 79 switch-hold {
80 label = "switch_hold"; 80 label = "switch_hold";
81 linux,code = <BTN_5>; 81 linux,code = <BTN_5>;
82 interrupt-parent = <&g 82 interrupt-parent = <&gsc>;
83 interrupts = <7>; 83 interrupts = <7>;
84 }; 84 };
85 }; 85 };
86 86
87 led-controller { 87 led-controller {
88 compatible = "gpio-leds"; 88 compatible = "gpio-leds";
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_gpio_led 90 pinctrl-0 = <&pinctrl_gpio_leds>;
91 91
92 led-0 { 92 led-0 {
93 function = LED_FUNCTIO 93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_ 94 color = <LED_COLOR_ID_GREEN>;
95 label = "panel1"; 95 label = "panel1";
96 gpios = <&gpio3 21 GPI 96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97 default-state = "off"; 97 default-state = "off";
98 }; 98 };
99 99
100 led-1 { 100 led-1 {
101 function = LED_FUNCTIO 101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_ 102 color = <LED_COLOR_ID_GREEN>;
103 label = "panel2"; 103 label = "panel2";
104 gpios = <&gpio3 23 GPI 104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105 default-state = "off"; 105 default-state = "off";
106 }; 106 };
107 107
108 led-2 { 108 led-2 {
109 function = LED_FUNCTIO 109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_ 110 color = <LED_COLOR_ID_GREEN>;
111 label = "panel3"; 111 label = "panel3";
112 gpios = <&gpio3 22 GPI 112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113 default-state = "off"; 113 default-state = "off";
114 }; 114 };
115 115
116 led-3 { 116 led-3 {
117 function = LED_FUNCTIO 117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_ 118 color = <LED_COLOR_ID_GREEN>;
119 label = "panel4"; 119 label = "panel4";
120 gpios = <&gpio3 20 GPI 120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121 default-state = "off"; 121 default-state = "off";
122 }; 122 };
123 123
124 led-4 { 124 led-4 {
125 function = LED_FUNCTIO 125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_ 126 color = <LED_COLOR_ID_GREEN>;
127 label = "panel5"; 127 label = "panel5";
128 gpios = <&gpio3 25 GPI 128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129 default-state = "off"; 129 default-state = "off";
130 }; 130 };
131 }; 131 };
132 132
133 pcie0_refclk: pcie0-refclk { 133 pcie0_refclk: pcie0-refclk {
134 compatible = "fixed-clock"; 134 compatible = "fixed-clock";
135 #clock-cells = <0>; 135 #clock-cells = <0>;
136 clock-frequency = <100000000>; 136 clock-frequency = <100000000>;
137 }; 137 };
138 138
139 pps { 139 pps {
140 compatible = "pps-gpio"; 140 compatible = "pps-gpio";
141 pinctrl-names = "default"; 141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pps>; 142 pinctrl-0 = <&pinctrl_pps>;
143 gpios = <&gpio3 24 GPIO_ACTIVE 143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144 status = "okay"; 144 status = "okay";
145 }; 145 };
146 146
147 reg_3p3v: regulator-3p3v { 147 reg_3p3v: regulator-3p3v {
148 compatible = "regulator-fixed" 148 compatible = "regulator-fixed";
149 regulator-name = "3P3V"; 149 regulator-name = "3P3V";
150 regulator-min-microvolt = <330 150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <330 151 regulator-max-microvolt = <3300000>;
152 regulator-always-on; 152 regulator-always-on;
153 }; 153 };
154 154
155 reg_usb1_vbus: regulator-usb1 { 155 reg_usb1_vbus: regulator-usb1 {
156 compatible = "regulator-fixed" 156 compatible = "regulator-fixed";
157 pinctrl-names = "default"; 157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_usb1 158 pinctrl-0 = <&pinctrl_reg_usb1>;
159 regulator-name = "usb_usb1_vbu 159 regulator-name = "usb_usb1_vbus";
160 gpio = <&gpio2 7 GPIO_ACTIVE_H 160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161 enable-active-high; 161 enable-active-high;
162 regulator-min-microvolt = <500 162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <500 163 regulator-max-microvolt = <5000000>;
164 }; 164 };
165 165
166 reg_wifi: regulator-wifi { 166 reg_wifi: regulator-wifi {
167 compatible = "regulator-fixed" 167 compatible = "regulator-fixed";
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_reg_wl>; 169 pinctrl-0 = <&pinctrl_reg_wl>;
170 regulator-name = "wifi"; 170 regulator-name = "wifi";
171 gpio = <&gpio2 19 GPIO_ACTIVE_ 171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172 enable-active-high; 172 enable-active-high;
173 startup-delay-us = <100>; 173 startup-delay-us = <100>;
174 regulator-min-microvolt = <330 174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <330 175 regulator-max-microvolt = <3300000>;
176 }; 176 };
177 }; 177 };
178 178
179 &A53_0 { 179 &A53_0 {
180 cpu-supply = <&buck2>; 180 cpu-supply = <&buck2>;
181 }; 181 };
182 182
183 &A53_1 { 183 &A53_1 {
184 cpu-supply = <&buck2>; 184 cpu-supply = <&buck2>;
185 }; 185 };
186 186
187 &A53_2 { 187 &A53_2 {
188 cpu-supply = <&buck2>; 188 cpu-supply = <&buck2>;
189 }; 189 };
190 190
191 &A53_3 { 191 &A53_3 {
192 cpu-supply = <&buck2>; 192 cpu-supply = <&buck2>;
193 }; 193 };
194 194
195 &ddrc { 195 &ddrc {
196 operating-points-v2 = <&ddrc_opp_table 196 operating-points-v2 = <&ddrc_opp_table>;
197 197
198 ddrc_opp_table: opp-table { 198 ddrc_opp_table: opp-table {
199 compatible = "operating-points 199 compatible = "operating-points-v2";
200 200
201 opp-25000000 { 201 opp-25000000 {
202 opp-hz = /bits/ 64 <25 202 opp-hz = /bits/ 64 <25000000>;
203 }; 203 };
204 204
205 opp-100000000 { 205 opp-100000000 {
206 opp-hz = /bits/ 64 <10 206 opp-hz = /bits/ 64 <100000000>;
207 }; 207 };
208 208
209 opp-750000000 { 209 opp-750000000 {
210 opp-hz = /bits/ 64 <75 210 opp-hz = /bits/ 64 <750000000>;
211 }; 211 };
212 }; 212 };
213 }; 213 };
214 214
215 &ecspi1 { 215 &ecspi1 {
216 pinctrl-names = "default"; 216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spi1>; 217 pinctrl-0 = <&pinctrl_spi1>;
218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219 status = "okay"; 219 status = "okay";
220 220
221 can@0 { 221 can@0 {
222 compatible = "microchip,mcp251 222 compatible = "microchip,mcp2515";
223 reg = <0>; 223 reg = <0>;
224 clocks = <&can20m>; 224 clocks = <&can20m>;
225 interrupt-parent = <&gpio2>; 225 interrupt-parent = <&gpio2>;
226 interrupts = <3 IRQ_TYPE_LEVEL 226 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227 spi-max-frequency = <10000000> 227 spi-max-frequency = <10000000>;
228 }; 228 };
229 }; 229 };
230 230
231 /* off-board header */ 231 /* off-board header */
232 &ecspi2 { 232 &ecspi2 {
233 pinctrl-names = "default"; 233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_spi2>; 234 pinctrl-0 = <&pinctrl_spi2>;
235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236 status = "okay"; 236 status = "okay";
237 }; 237 };
238 238
239 &fec1 { 239 &fec1 {
240 pinctrl-names = "default"; 240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_fec1>; 241 pinctrl-0 = <&pinctrl_fec1>;
242 phy-mode = "rgmii-id"; 242 phy-mode = "rgmii-id";
243 phy-handle = <ðphy0>; 243 phy-handle = <ðphy0>;
244 local-mac-address = [00 00 00 00 00 00 244 local-mac-address = [00 00 00 00 00 00];
245 status = "okay"; 245 status = "okay";
246 246
247 mdio { 247 mdio {
248 #address-cells = <1>; 248 #address-cells = <1>;
249 #size-cells = <0>; 249 #size-cells = <0>;
250 250
251 ethphy0: ethernet-phy@0 { 251 ethphy0: ethernet-phy@0 {
252 compatible = "ethernet 252 compatible = "ethernet-phy-ieee802.3-c22";
253 reg = <0>; 253 reg = <0>;
254 ti,rx-internal-delay = 254 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255 ti,tx-internal-delay = 255 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256 tx-fifo-depth = <DP838 256 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257 rx-fifo-depth = <DP838 257 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 }; 258 };
259 }; 259 };
260 }; 260 };
261 261
262 &gpio1 { 262 &gpio1 {
263 gpio-line-names = "", "", "", "", "", 263 gpio-line-names = "", "", "", "", "", "", "", "",
264 "m2_pwr_en", "", "", "", "", " 264 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
265 "", "", "", "", "", "", "", "" 265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "" 266 "", "", "", "", "", "", "", "";
267 }; 267 };
268 268
269 &gpio2 { 269 &gpio2 {
270 gpio-line-names = "", "", "", "", "", 270 gpio-line-names = "", "", "", "", "", "", "", "",
271 "uart2_en#", "", "", "", "", " 271 "uart2_en#", "", "", "", "", "", "", "",
272 "", "", "", "", "", "", "", "" 272 "", "", "", "", "", "", "", "",
273 "", "", "", "", "", "", "", "" 273 "", "", "", "", "", "", "", "";
274 }; 274 };
275 275
276 &gpio3 { 276 &gpio3 {
277 gpio-line-names = "", "m2_gdis#", "", 277 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278 "", "", "", "", "", "", "", "" 278 "", "", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "" 279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 280 "", "", "", "", "", "", "", "";
281 }; 281 };
282 282
283 &gpio4 { 283 &gpio4 {
284 gpio-line-names = "", "", "", "", "", 284 gpio-line-names = "", "", "", "", "", "", "", "",
285 "", "", "", "amp_gpio3", "amp_ 285 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286 "lte_pwr#", "lte_rst", "lte_in 286 "lte_pwr#", "lte_rst", "lte_int", "",
287 "amp_gpio4", "app_gpio1", "vdd 287 "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
288 "", "uart1_term", "uart1_half" 288 "", "uart1_term", "uart1_half", "app_gpio2",
289 "mipi_gpio1", "", "", ""; 289 "mipi_gpio1", "", "", "";
290 }; 290 };
291 291
292 &gpio5 { 292 &gpio5 {
293 gpio-line-names = "", "", "", "mipi_gp 293 gpio-line-names = "", "", "", "mipi_gpio4",
294 "mipi_gpio3", "mipi_gpio2", "" 294 "mipi_gpio3", "mipi_gpio2", "", "",
295 "", "", "", "", "", "", "", "" 295 "", "", "", "", "", "", "", "",
296 "", "", "", "", "", "", "", "" 296 "", "", "", "", "", "", "", "",
297 "", "", "", "", "", "", "", "" 297 "", "", "", "", "", "", "", "";
298 }; 298 };
299 299
300 &i2c1 { 300 &i2c1 {
301 clock-frequency = <100000>; 301 clock-frequency = <100000>;
302 pinctrl-names = "default", "gpio"; 302 pinctrl-names = "default", "gpio";
303 pinctrl-0 = <&pinctrl_i2c1>; 303 pinctrl-0 = <&pinctrl_i2c1>;
304 pinctrl-1 = <&pinctrl_i2c1_gpio>; 304 pinctrl-1 = <&pinctrl_i2c1_gpio>;
305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
307 status = "okay"; 307 status = "okay";
308 308
309 gsc: gsc@20 { 309 gsc: gsc@20 {
310 compatible = "gw,gsc"; 310 compatible = "gw,gsc";
311 reg = <0x20>; 311 reg = <0x20>;
312 pinctrl-0 = <&pinctrl_gsc>; 312 pinctrl-0 = <&pinctrl_gsc>;
313 interrupt-parent = <&gpio2>; 313 interrupt-parent = <&gpio2>;
314 interrupts = <6 IRQ_TYPE_EDGE_ 314 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315 interrupt-controller; 315 interrupt-controller;
316 #interrupt-cells = <1>; 316 #interrupt-cells = <1>;
317 #address-cells = <1>; 317 #address-cells = <1>;
318 #size-cells = <0>; 318 #size-cells = <0>;
319 319
320 adc { 320 adc {
321 compatible = "gw,gsc-a 321 compatible = "gw,gsc-adc";
322 #address-cells = <1>; 322 #address-cells = <1>;
323 #size-cells = <0>; 323 #size-cells = <0>;
324 324
325 channel@6 { 325 channel@6 {
326 gw,mode = <0>; 326 gw,mode = <0>;
327 reg = <0x06>; 327 reg = <0x06>;
328 label = "temp" 328 label = "temp";
329 }; 329 };
330 330
331 channel@8 { 331 channel@8 {
332 gw,mode = <3>; 332 gw,mode = <3>;
333 reg = <0x08>; 333 reg = <0x08>;
334 label = "vdd_b 334 label = "vdd_bat";
335 }; 335 };
336 336
337 channel@82 { 337 channel@82 {
338 gw,mode = <2>; 338 gw,mode = <2>;
339 reg = <0x82>; 339 reg = <0x82>;
340 label = "vin"; 340 label = "vin";
341 gw,voltage-div 341 gw,voltage-divider-ohms = <22100 1000>;
342 gw,voltage-off 342 gw,voltage-offset-microvolt = <700000>;
343 }; 343 };
344 344
345 channel@84 { 345 channel@84 {
346 gw,mode = <2>; 346 gw,mode = <2>;
347 reg = <0x84>; 347 reg = <0x84>;
348 label = "vin_4 348 label = "vin_4p0";
349 gw,voltage-div 349 gw,voltage-divider-ohms = <10000 10000>;
350 }; 350 };
351 351
352 channel@86 { 352 channel@86 {
353 gw,mode = <2>; 353 gw,mode = <2>;
354 reg = <0x86>; 354 reg = <0x86>;
355 label = "vdd_3 355 label = "vdd_3p3";
356 gw,voltage-div 356 gw,voltage-divider-ohms = <10000 10000>;
357 }; 357 };
358 358
359 channel@88 { 359 channel@88 {
360 gw,mode = <2>; 360 gw,mode = <2>;
361 reg = <0x88>; 361 reg = <0x88>;
362 label = "vdd_0 362 label = "vdd_0p9";
363 }; 363 };
364 364
365 channel@8c { 365 channel@8c {
366 gw,mode = <2>; 366 gw,mode = <2>;
367 reg = <0x8c>; 367 reg = <0x8c>;
368 label = "vdd_s 368 label = "vdd_soc";
369 }; 369 };
370 370
371 channel@8e { 371 channel@8e {
372 gw,mode = <2>; 372 gw,mode = <2>;
373 reg = <0x8e>; 373 reg = <0x8e>;
374 label = "vdd_a 374 label = "vdd_arm";
375 }; 375 };
376 376
377 channel@90 { 377 channel@90 {
378 gw,mode = <2>; 378 gw,mode = <2>;
379 reg = <0x90>; 379 reg = <0x90>;
380 label = "vdd_1 380 label = "vdd_1p8";
381 }; 381 };
382 382
383 channel@92 { 383 channel@92 {
384 gw,mode = <2>; 384 gw,mode = <2>;
385 reg = <0x92>; 385 reg = <0x92>;
386 label = "vdd_d 386 label = "vdd_dram";
387 }; 387 };
388 388
389 channel@98 { 389 channel@98 {
390 gw,mode = <2>; 390 gw,mode = <2>;
391 reg = <0x98>; 391 reg = <0x98>;
392 label = "vdd_1 392 label = "vdd_1p0";
393 }; 393 };
394 394
395 channel@9a { 395 channel@9a {
396 gw,mode = <2>; 396 gw,mode = <2>;
397 reg = <0x9a>; 397 reg = <0x9a>;
398 label = "vdd_2 398 label = "vdd_2p5";
399 gw,voltage-div 399 gw,voltage-divider-ohms = <10000 10000>;
400 }; 400 };
401 401
402 channel@9c { 402 channel@9c {
403 gw,mode = <2>; 403 gw,mode = <2>;
404 reg = <0x9c>; 404 reg = <0x9c>;
405 label = "vdd_5 405 label = "vdd_5p0";
406 gw,voltage-div 406 gw,voltage-divider-ohms = <10000 10000>;
407 }; 407 };
408 408
409 channel@a2 { 409 channel@a2 {
410 gw,mode = <2>; 410 gw,mode = <2>;
411 reg = <0xa2>; 411 reg = <0xa2>;
412 label = "vdd_g 412 label = "vdd_gsc";
413 gw,voltage-div 413 gw,voltage-divider-ohms = <10000 10000>;
414 }; 414 };
415 }; 415 };
416 }; 416 };
417 417
418 gpio: gpio@23 { 418 gpio: gpio@23 {
419 compatible = "nxp,pca9555"; 419 compatible = "nxp,pca9555";
420 reg = <0x23>; 420 reg = <0x23>;
421 gpio-controller; 421 gpio-controller;
422 #gpio-cells = <2>; 422 #gpio-cells = <2>;
423 interrupt-parent = <&gsc>; 423 interrupt-parent = <&gsc>;
424 interrupts = <4>; 424 interrupts = <4>;
425 }; 425 };
426 426
427 pmic@4b { 427 pmic@4b {
428 compatible = "rohm,bd71847"; 428 compatible = "rohm,bd71847";
429 reg = <0x4b>; 429 reg = <0x4b>;
430 pinctrl-names = "default"; 430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_pmic>; 431 pinctrl-0 = <&pinctrl_pmic>;
432 interrupt-parent = <&gpio3>; 432 interrupt-parent = <&gpio3>;
433 interrupts = <8 IRQ_TYPE_LEVEL 433 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
434 rohm,reset-snvs-powered; 434 rohm,reset-snvs-powered;
435 #clock-cells = <0>; 435 #clock-cells = <0>;
436 clocks = <&osc_32k>; 436 clocks = <&osc_32k>;
437 clock-output-names = "clk-32k- 437 clock-output-names = "clk-32k-out";
438 438
439 regulators { 439 regulators {
440 /* vdd_soc: 0.805-0.90 440 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
441 BUCK1 { 441 BUCK1 {
442 regulator-name 442 regulator-name = "buck1";
443 regulator-min- 443 regulator-min-microvolt = <700000>;
444 regulator-max- 444 regulator-max-microvolt = <1300000>;
445 regulator-boot 445 regulator-boot-on;
446 regulator-alwa 446 regulator-always-on;
447 regulator-ramp 447 regulator-ramp-delay = <1250>;
448 }; 448 };
449 449
450 /* vdd_arm: 0.805-1.0V 450 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
451 buck2: BUCK2 { 451 buck2: BUCK2 {
452 regulator-name 452 regulator-name = "buck2";
453 regulator-min- 453 regulator-min-microvolt = <700000>;
454 regulator-max- 454 regulator-max-microvolt = <1300000>;
455 regulator-boot 455 regulator-boot-on;
456 regulator-alwa 456 regulator-always-on;
457 regulator-ramp 457 regulator-ramp-delay = <1250>;
458 rohm,dvs-run-v 458 rohm,dvs-run-voltage = <1000000>;
459 rohm,dvs-idle- 459 rohm,dvs-idle-voltage = <900000>;
460 }; 460 };
461 461
462 /* vdd_0p9: 0.805-1.0V 462 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
463 BUCK3 { 463 BUCK3 {
464 regulator-name 464 regulator-name = "buck3";
465 regulator-min- 465 regulator-min-microvolt = <700000>;
466 regulator-max- 466 regulator-max-microvolt = <1350000>;
467 regulator-boot 467 regulator-boot-on;
468 regulator-alwa 468 regulator-always-on;
469 }; 469 };
470 470
471 /* vdd_3p3 */ 471 /* vdd_3p3 */
472 BUCK4 { 472 BUCK4 {
473 regulator-name 473 regulator-name = "buck4";
474 regulator-min- 474 regulator-min-microvolt = <3000000>;
475 regulator-max- 475 regulator-max-microvolt = <3300000>;
476 regulator-boot 476 regulator-boot-on;
477 regulator-alwa 477 regulator-always-on;
478 }; 478 };
479 479
480 /* vdd_1p8 */ 480 /* vdd_1p8 */
481 BUCK5 { 481 BUCK5 {
482 regulator-name 482 regulator-name = "buck5";
483 regulator-min- 483 regulator-min-microvolt = <1605000>;
484 regulator-max- 484 regulator-max-microvolt = <1995000>;
485 regulator-boot 485 regulator-boot-on;
486 regulator-alwa 486 regulator-always-on;
487 }; 487 };
488 488
489 /* vdd_dram */ 489 /* vdd_dram */
490 BUCK6 { 490 BUCK6 {
491 regulator-name 491 regulator-name = "buck6";
492 regulator-min- 492 regulator-min-microvolt = <800000>;
493 regulator-max- 493 regulator-max-microvolt = <1400000>;
494 regulator-boot 494 regulator-boot-on;
495 regulator-alwa 495 regulator-always-on;
496 }; 496 };
497 497
498 /* nvcc_snvs_1p8 */ 498 /* nvcc_snvs_1p8 */
499 LDO1 { 499 LDO1 {
500 regulator-name 500 regulator-name = "ldo1";
501 regulator-min- 501 regulator-min-microvolt = <1600000>;
502 regulator-max- 502 regulator-max-microvolt = <1900000>;
503 regulator-boot 503 regulator-boot-on;
504 regulator-alwa 504 regulator-always-on;
505 }; 505 };
506 506
507 /* vdd_snvs_0p8 */ 507 /* vdd_snvs_0p8 */
508 LDO2 { 508 LDO2 {
509 regulator-name 509 regulator-name = "ldo2";
510 regulator-min- 510 regulator-min-microvolt = <800000>;
511 regulator-max- 511 regulator-max-microvolt = <900000>;
512 regulator-boot 512 regulator-boot-on;
513 regulator-alwa 513 regulator-always-on;
514 }; 514 };
515 515
516 /* vdda_1p8 */ 516 /* vdda_1p8 */
517 LDO3 { 517 LDO3 {
518 regulator-name 518 regulator-name = "ldo3";
519 regulator-min- 519 regulator-min-microvolt = <1800000>;
520 regulator-max- 520 regulator-max-microvolt = <3300000>;
521 regulator-boot 521 regulator-boot-on;
522 regulator-alwa 522 regulator-always-on;
523 }; 523 };
524 524
525 LDO4 { 525 LDO4 {
526 regulator-name 526 regulator-name = "ldo4";
527 regulator-min- 527 regulator-min-microvolt = <900000>;
528 regulator-max- 528 regulator-max-microvolt = <1800000>;
529 regulator-boot 529 regulator-boot-on;
530 regulator-alwa 530 regulator-always-on;
531 }; 531 };
532 532
533 LDO6 { 533 LDO6 {
534 regulator-name 534 regulator-name = "ldo6";
535 regulator-min- 535 regulator-min-microvolt = <900000>;
536 regulator-max- 536 regulator-max-microvolt = <1800000>;
537 regulator-boot 537 regulator-boot-on;
538 regulator-alwa 538 regulator-always-on;
539 }; 539 };
540 }; 540 };
541 }; 541 };
542 542
543 eeprom@50 { 543 eeprom@50 {
544 compatible = "atmel,24c02"; 544 compatible = "atmel,24c02";
545 reg = <0x50>; 545 reg = <0x50>;
546 pagesize = <16>; 546 pagesize = <16>;
547 }; 547 };
548 548
549 eeprom@51 { 549 eeprom@51 {
550 compatible = "atmel,24c02"; 550 compatible = "atmel,24c02";
551 reg = <0x51>; 551 reg = <0x51>;
552 pagesize = <16>; 552 pagesize = <16>;
553 }; 553 };
554 554
555 eeprom@52 { 555 eeprom@52 {
556 compatible = "atmel,24c02"; 556 compatible = "atmel,24c02";
557 reg = <0x52>; 557 reg = <0x52>;
558 pagesize = <16>; 558 pagesize = <16>;
559 }; 559 };
560 560
561 eeprom@53 { 561 eeprom@53 {
562 compatible = "atmel,24c02"; 562 compatible = "atmel,24c02";
563 reg = <0x53>; 563 reg = <0x53>;
564 pagesize = <16>; 564 pagesize = <16>;
565 }; 565 };
566 566
567 rtc@68 { 567 rtc@68 {
568 compatible = "dallas,ds1672"; 568 compatible = "dallas,ds1672";
569 reg = <0x68>; 569 reg = <0x68>;
570 }; 570 };
571 }; 571 };
572 572
573 &i2c2 { 573 &i2c2 {
574 clock-frequency = <400000>; 574 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio"; 575 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c2>; 576 pinctrl-0 = <&pinctrl_i2c2>;
577 pinctrl-1 = <&pinctrl_i2c2_gpio>; 577 pinctrl-1 = <&pinctrl_i2c2_gpio>;
578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
580 status = "okay"; 580 status = "okay";
581 581
582 accelerometer@19 { 582 accelerometer@19 {
583 compatible = "st,lis2de12"; 583 compatible = "st,lis2de12";
584 pinctrl-names = "default"; 584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_accel>; 585 pinctrl-0 = <&pinctrl_accel>;
586 reg = <0x19>; 586 reg = <0x19>;
587 st,drdy-int-pin = <1>; 587 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>; 588 interrupt-parent = <&gpio1>;
589 interrupts = <12 IRQ_TYPE_LEVE 589 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
590 }; 590 };
591 }; 591 };
592 592
593 /* off-board header */ 593 /* off-board header */
594 &i2c3 { 594 &i2c3 {
595 clock-frequency = <400000>; 595 clock-frequency = <400000>;
596 pinctrl-names = "default", "gpio"; 596 pinctrl-names = "default", "gpio";
597 pinctrl-0 = <&pinctrl_i2c3>; 597 pinctrl-0 = <&pinctrl_i2c3>;
598 pinctrl-1 = <&pinctrl_i2c3_gpio>; 598 pinctrl-1 = <&pinctrl_i2c3_gpio>;
599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
601 status = "okay"; 601 status = "okay";
602 }; 602 };
603 603
604 /* off-board header */ 604 /* off-board header */
605 &i2c4 { 605 &i2c4 {
606 clock-frequency = <400000>; 606 clock-frequency = <400000>;
607 pinctrl-names = "default", "gpio"; 607 pinctrl-names = "default", "gpio";
608 pinctrl-0 = <&pinctrl_i2c4>; 608 pinctrl-0 = <&pinctrl_i2c4>;
609 pinctrl-1 = <&pinctrl_i2c4_gpio>; 609 pinctrl-1 = <&pinctrl_i2c4_gpio>;
610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
612 status = "okay"; 612 status = "okay";
613 }; 613 };
614 614
615 &pcie_phy { 615 &pcie_phy {
616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
617 fsl,clkreq-unsupported; 617 fsl,clkreq-unsupported;
618 clocks = <&pcie0_refclk>; 618 clocks = <&pcie0_refclk>;
619 clock-names = "ref"; 619 clock-names = "ref";
620 status = "okay"; 620 status = "okay";
621 }; 621 };
622 622
623 &pcie0 { 623 &pcie0 {
624 pinctrl-names = "default"; 624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pcie0>; 625 pinctrl-0 = <&pinctrl_pcie0>;
626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW 626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
628 <&clk IMX8MM_CLK_PCIE1_AUX>; 628 <&clk IMX8MM_CLK_PCIE1_AUX>;
629 assigned-clocks = <&clk IMX8MM_CLK_PCI 629 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
630 <&clk IMX8MM_CLK_PCI 630 <&clk IMX8MM_CLK_PCIE1_CTRL>;
631 assigned-clock-rates = <10000000>, <25 631 assigned-clock-rates = <10000000>, <250000000>;
632 assigned-clock-parents = <&clk IMX8MM_ 632 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
633 <&clk IMX8MM_ 633 <&clk IMX8MM_SYS_PLL2_250M>;
634 status = "okay"; 634 status = "okay";
635 635
636 pcie@0,0 { 636 pcie@0,0 {
637 reg = <0x0000 0 0 0 0>; 637 reg = <0x0000 0 0 0 0>;
638 device_type = "pci"; 638 device_type = "pci";
639 #address-cells = <3>; 639 #address-cells = <3>;
640 #size-cells = <2>; 640 #size-cells = <2>;
641 ranges; 641 ranges;
642 642
643 eth1: ethernet@0,0 { 643 eth1: ethernet@0,0 {
644 reg = <0x0000 0 0 0 0> 644 reg = <0x0000 0 0 0 0>;
645 #address-cells = <3>; 645 #address-cells = <3>;
646 #size-cells = <2>; 646 #size-cells = <2>;
647 ranges; 647 ranges;
648 648
649 local-mac-address = [0 649 local-mac-address = [00 00 00 00 00 00];
650 }; 650 };
651 }; 651 };
652 }; 652 };
653 653
654 /* off-board header */ 654 /* off-board header */
655 &sai3 { 655 &sai3 {
656 pinctrl-names = "default"; 656 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_sai3>; 657 pinctrl-0 = <&pinctrl_sai3>;
658 assigned-clocks = <&clk IMX8MM_CLK_SAI 658 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
659 assigned-clock-parents = <&clk IMX8MM_ 659 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
660 assigned-clock-rates = <24576000>; 660 assigned-clock-rates = <24576000>;
661 status = "okay"; 661 status = "okay";
662 }; 662 };
663 663
664 /* RS232/RS485/RS422 selectable */ 664 /* RS232/RS485/RS422 selectable */
665 &uart1 { 665 &uart1 {
666 pinctrl-names = "default"; 666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 667 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
668 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW 668 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
669 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW 669 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
670 status = "okay"; 670 status = "okay";
671 }; 671 };
672 672
673 /* RS232 console */ 673 /* RS232 console */
674 &uart2 { 674 &uart2 {
675 pinctrl-names = "default"; 675 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_uart2>; 676 pinctrl-0 = <&pinctrl_uart2>;
677 status = "okay"; 677 status = "okay";
678 }; 678 };
679 679
680 /* bluetooth HCI */ 680 /* bluetooth HCI */
681 &uart3 { 681 &uart3 {
682 pinctrl-names = "default"; 682 pinctrl-names = "default";
683 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 683 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
684 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 684 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
685 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 685 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
686 status = "okay"; 686 status = "okay";
687 687
688 bluetooth { 688 bluetooth {
689 compatible = "brcm,bcm4330-bt" 689 compatible = "brcm,bcm4330-bt";
690 shutdown-gpios = <&gpio2 12 GP 690 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
691 }; 691 };
692 }; 692 };
693 693
694 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 694 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
695 &uart4 { 695 &uart4 {
696 pinctrl-names = "default"; 696 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_uart4>; 697 pinctrl-0 = <&pinctrl_uart4>;
698 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW> 698 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
699 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW> 699 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
700 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW> 700 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
701 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW> 701 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
702 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW> 702 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
703 status = "okay"; 703 status = "okay";
704 }; 704 };
705 705
706 &usbotg1 { 706 &usbotg1 {
707 dr_mode = "host"; 707 dr_mode = "host";
708 vbus-supply = <®_usb1_vbus>; 708 vbus-supply = <®_usb1_vbus>;
709 disable-over-current; 709 disable-over-current;
710 status = "okay"; 710 status = "okay";
711 }; 711 };
712 712
713 &usbotg2 { 713 &usbotg2 {
714 dr_mode = "host"; 714 dr_mode = "host";
715 disable-over-current; 715 disable-over-current;
716 status = "okay"; 716 status = "okay";
717 }; 717 };
718 718
719 /* SDIO WiFi */ 719 /* SDIO WiFi */
720 &usdhc2 { 720 &usdhc2 {
721 pinctrl-names = "default", "state_100m 721 pinctrl-names = "default", "state_100mhz", "state_200mhz";
722 pinctrl-0 = <&pinctrl_usdhc2>; 722 pinctrl-0 = <&pinctrl_usdhc2>;
723 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 723 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
724 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 724 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
725 bus-width = <4>; 725 bus-width = <4>;
726 non-removable; 726 non-removable;
727 vmmc-supply = <®_wifi>; 727 vmmc-supply = <®_wifi>;
728 #address-cells = <1>; 728 #address-cells = <1>;
729 #size-cells = <0>; 729 #size-cells = <0>;
730 status = "okay"; 730 status = "okay";
731 731
732 wifi@0 { 732 wifi@0 {
733 compatible = "brcm,bcm43455-fm 733 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
734 reg = <0>; 734 reg = <0>;
735 }; 735 };
736 }; 736 };
737 737
738 /* eMMC */ 738 /* eMMC */
739 &usdhc3 { 739 &usdhc3 {
740 pinctrl-names = "default", "state_100m 740 pinctrl-names = "default", "state_100mhz", "state_200mhz";
741 pinctrl-0 = <&pinctrl_usdhc3>; 741 pinctrl-0 = <&pinctrl_usdhc3>;
742 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 742 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
743 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 743 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
744 bus-width = <8>; 744 bus-width = <8>;
745 non-removable; 745 non-removable;
746 status = "okay"; 746 status = "okay";
747 }; 747 };
748 748
749 &wdog1 { 749 &wdog1 {
750 pinctrl-names = "default"; 750 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_wdog>; 751 pinctrl-0 = <&pinctrl_wdog>;
752 fsl,ext-reset-output; 752 fsl,ext-reset-output;
753 status = "okay"; 753 status = "okay";
754 }; 754 };
755 755
756 &iomuxc { 756 &iomuxc {
757 pinctrl-names = "default"; 757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_hog>; 758 pinctrl-0 = <&pinctrl_hog>;
759 759
760 pinctrl_hog: hoggrp { 760 pinctrl_hog: hoggrp {
761 fsl,pins = < 761 fsl,pins = <
762 MX8MM_IOMUXC_NAND_CE0_ 762 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
763 MX8MM_IOMUXC_GPIO1_IO0 763 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
764 MX8MM_IOMUXC_GPIO1_IO1 764 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
765 MX8MM_IOMUXC_NAND_DATA 765 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
766 MX8MM_IOMUXC_GPIO1_IO1 766 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
767 MX8MM_IOMUXC_SAI1_TXD6 767 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
768 MX8MM_IOMUXC_SAI1_TXD5 768 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
769 MX8MM_IOMUXC_SAI1_TXD4 769 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
770 MX8MM_IOMUXC_SAI1_TXD2 770 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
771 MX8MM_IOMUXC_SAI1_TXD0 771 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
772 MX8MM_IOMUXC_SAI1_TXC_ 772 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
773 MX8MM_IOMUXC_SAI1_MCLK 773 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
774 MX8MM_IOMUXC_SAI2_RXFS 774 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
775 MX8MM_IOMUXC_SAI2_RXC_ 775 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
776 MX8MM_IOMUXC_SAI2_MCLK 776 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
777 MX8MM_IOMUXC_SD1_DATA6 777 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
778 MX8MM_IOMUXC_SAI3_RXFS 778 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
779 MX8MM_IOMUXC_SPDIF_EXT 779 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
780 MX8MM_IOMUXC_SPDIF_RX_ 780 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
781 MX8MM_IOMUXC_SPDIF_TX_ 781 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
782 >; 782 >;
783 }; 783 };
784 784
785 pinctrl_accel: accelgrp { 785 pinctrl_accel: accelgrp {
786 fsl,pins = < 786 fsl,pins = <
787 MX8MM_IOMUXC_GPIO1_IO1 787 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
788 >; 788 >;
789 }; 789 };
790 790
791 pinctrl_fec1: fec1grp { 791 pinctrl_fec1: fec1grp {
792 fsl,pins = < 792 fsl,pins = <
793 MX8MM_IOMUXC_ENET_MDC_ 793 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
794 MX8MM_IOMUXC_ENET_MDIO 794 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
795 MX8MM_IOMUXC_ENET_TD3_ 795 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
796 MX8MM_IOMUXC_ENET_TD2_ 796 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
797 MX8MM_IOMUXC_ENET_TD1_ 797 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
798 MX8MM_IOMUXC_ENET_TD0_ 798 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
799 MX8MM_IOMUXC_ENET_RD3_ 799 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
800 MX8MM_IOMUXC_ENET_RD2_ 800 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
801 MX8MM_IOMUXC_ENET_RD1_ 801 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
802 MX8MM_IOMUXC_ENET_RD0_ 802 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
803 MX8MM_IOMUXC_ENET_TXC_ 803 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
804 MX8MM_IOMUXC_ENET_RXC_ 804 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
805 MX8MM_IOMUXC_ENET_RX_C 805 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
806 MX8MM_IOMUXC_ENET_TX_C 806 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
807 MX8MM_IOMUXC_GPIO1_IO1 807 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
808 MX8MM_IOMUXC_GPIO1_IO1 808 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
809 >; 809 >;
810 }; 810 };
811 811
812 pinctrl_gsc: gscgrp { 812 pinctrl_gsc: gscgrp {
813 fsl,pins = < 813 fsl,pins = <
814 MX8MM_IOMUXC_SD1_DATA4 814 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
815 >; 815 >;
816 }; 816 };
817 817
818 pinctrl_i2c1: i2c1grp { 818 pinctrl_i2c1: i2c1grp {
819 fsl,pins = < 819 fsl,pins = <
820 MX8MM_IOMUXC_I2C1_SCL_ 820 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
821 MX8MM_IOMUXC_I2C1_SDA_ 821 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
822 >; 822 >;
823 }; 823 };
824 824
825 pinctrl_i2c1_gpio: i2c1gpiogrp { 825 pinctrl_i2c1_gpio: i2c1gpiogrp {
826 fsl,pins = < 826 fsl,pins = <
827 MX8MM_IOMUXC_I2C1_SCL_ 827 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
828 MX8MM_IOMUXC_I2C1_SDA_ 828 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
829 >; 829 >;
830 }; 830 };
831 831
832 pinctrl_i2c2: i2c2grp { 832 pinctrl_i2c2: i2c2grp {
833 fsl,pins = < 833 fsl,pins = <
834 MX8MM_IOMUXC_I2C2_SCL_ 834 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
835 MX8MM_IOMUXC_I2C2_SDA_ 835 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
836 >; 836 >;
837 }; 837 };
838 838
839 pinctrl_i2c2_gpio: i2c2gpiogrp { 839 pinctrl_i2c2_gpio: i2c2gpiogrp {
840 fsl,pins = < 840 fsl,pins = <
841 MX8MM_IOMUXC_I2C2_SCL_ 841 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
842 MX8MM_IOMUXC_I2C2_SDA_ 842 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
843 >; 843 >;
844 }; 844 };
845 845
846 pinctrl_i2c3: i2c3grp { 846 pinctrl_i2c3: i2c3grp {
847 fsl,pins = < 847 fsl,pins = <
848 MX8MM_IOMUXC_I2C3_SCL_ 848 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
849 MX8MM_IOMUXC_I2C3_SDA_ 849 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
850 >; 850 >;
851 }; 851 };
852 852
853 pinctrl_i2c3_gpio: i2c3gpiogrp { 853 pinctrl_i2c3_gpio: i2c3gpiogrp {
854 fsl,pins = < 854 fsl,pins = <
855 MX8MM_IOMUXC_I2C3_SCL_ 855 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
856 MX8MM_IOMUXC_I2C3_SDA_ 856 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
857 >; 857 >;
858 }; 858 };
859 859
860 pinctrl_i2c4: i2c4grp { 860 pinctrl_i2c4: i2c4grp {
861 fsl,pins = < 861 fsl,pins = <
862 MX8MM_IOMUXC_I2C4_SCL_ 862 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C4_SDA_ 863 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
864 >; 864 >;
865 }; 865 };
866 866
867 pinctrl_i2c4_gpio: i2c4gpiogrp { 867 pinctrl_i2c4_gpio: i2c4gpiogrp {
868 fsl,pins = < 868 fsl,pins = <
869 MX8MM_IOMUXC_I2C4_SCL_ 869 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
870 MX8MM_IOMUXC_I2C4_SDA_ 870 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
871 >; 871 >;
872 }; 872 };
873 873
874 pinctrl_gpio_leds: gpioledgrp { 874 pinctrl_gpio_leds: gpioledgrp {
875 fsl,pins = < 875 fsl,pins = <
876 MX8MM_IOMUXC_SAI5_RXD0 876 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
877 MX8MM_IOMUXC_SAI5_RXD2 877 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
878 MX8MM_IOMUXC_SAI5_RXD1 878 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
879 MX8MM_IOMUXC_SAI5_RXC_ 879 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
880 MX8MM_IOMUXC_SAI5_MCLK 880 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
881 >; 881 >;
882 }; 882 };
883 883
884 pinctrl_pcie0: pciegrp { 884 pinctrl_pcie0: pciegrp {
885 fsl,pins = < 885 fsl,pins = <
886 MX8MM_IOMUXC_SAI1_RXD3 886 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
887 >; 887 >;
888 }; 888 };
889 889
890 pinctrl_pmic: pmicgrp { 890 pinctrl_pmic: pmicgrp {
891 fsl,pins = < 891 fsl,pins = <
892 MX8MM_IOMUXC_NAND_DATA 892 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
893 >; 893 >;
894 }; 894 };
895 895
896 pinctrl_pps: ppsgrp { 896 pinctrl_pps: ppsgrp {
897 fsl,pins = < 897 fsl,pins = <
898 MX8MM_IOMUXC_SAI5_RXD3 898 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
899 >; 899 >;
900 }; 900 };
901 901
902 pinctrl_reg_wl: regwlgrp { 902 pinctrl_reg_wl: regwlgrp {
903 fsl,pins = < 903 fsl,pins = <
904 MX8MM_IOMUXC_SD2_RESET 904 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
905 >; 905 >;
906 }; 906 };
907 907
908 pinctrl_reg_usb1: regusb1grp { 908 pinctrl_reg_usb1: regusb1grp {
909 fsl,pins = < 909 fsl,pins = <
910 MX8MM_IOMUXC_SD1_DATA5 910 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
911 >; 911 >;
912 }; 912 };
913 913
914 pinctrl_sai3: sai3grp { 914 pinctrl_sai3: sai3grp {
915 fsl,pins = < 915 fsl,pins = <
916 MX8MM_IOMUXC_SAI3_MCLK 916 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
917 MX8MM_IOMUXC_SAI3_RXD_ 917 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
918 MX8MM_IOMUXC_SAI3_TXC_ 918 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
919 MX8MM_IOMUXC_SAI3_TXD_ 919 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
920 MX8MM_IOMUXC_SAI3_TXFS 920 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
921 >; 921 >;
922 }; 922 };
923 923
924 pinctrl_spi1: spi1grp { 924 pinctrl_spi1: spi1grp {
925 fsl,pins = < 925 fsl,pins = <
926 MX8MM_IOMUXC_ECSPI1_SC 926 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
927 MX8MM_IOMUXC_ECSPI1_MO 927 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
928 MX8MM_IOMUXC_ECSPI1_MI 928 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
929 MX8MM_IOMUXC_ECSPI1_SS 929 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
930 MX8MM_IOMUXC_SD1_DATA1 930 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
931 >; 931 >;
932 }; 932 };
933 933
934 pinctrl_spi2: spi2grp { 934 pinctrl_spi2: spi2grp {
935 fsl,pins = < 935 fsl,pins = <
936 MX8MM_IOMUXC_ECSPI2_SC 936 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
937 MX8MM_IOMUXC_ECSPI2_MO 937 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
938 MX8MM_IOMUXC_ECSPI2_MI 938 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
939 MX8MM_IOMUXC_ECSPI2_SS 939 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
940 >; 940 >;
941 }; 941 };
942 942
943 pinctrl_uart1: uart1grp { 943 pinctrl_uart1: uart1grp {
944 fsl,pins = < 944 fsl,pins = <
945 MX8MM_IOMUXC_UART1_RXD 945 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
946 MX8MM_IOMUXC_UART1_TXD 946 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
947 MX8MM_IOMUXC_SAI1_TXFS 947 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
948 MX8MM_IOMUXC_SAI2_TXFS 948 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
949 >; 949 >;
950 }; 950 };
951 951
952 pinctrl_uart1_gpio: uart1gpiogrp { 952 pinctrl_uart1_gpio: uart1gpiogrp {
953 fsl,pins = < 953 fsl,pins = <
954 MX8MM_IOMUXC_SAI2_TXD0 954 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
955 MX8MM_IOMUXC_SAI2_TXC_ 955 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
956 MX8MM_IOMUXC_SAI2_RXD0 956 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
957 >; 957 >;
958 }; 958 };
959 959
960 pinctrl_uart2: uart2grp { 960 pinctrl_uart2: uart2grp {
961 fsl,pins = < 961 fsl,pins = <
962 MX8MM_IOMUXC_UART2_RXD 962 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
963 MX8MM_IOMUXC_UART2_TXD 963 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
964 >; 964 >;
965 }; 965 };
966 966
967 pinctrl_uart3_gpio: uart3_gpiogrp { 967 pinctrl_uart3_gpio: uart3_gpiogrp {
968 fsl,pins = < 968 fsl,pins = <
969 MX8MM_IOMUXC_SD2_CD_B_ 969 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
970 >; 970 >;
971 }; 971 };
972 972
973 pinctrl_uart3: uart3grp { 973 pinctrl_uart3: uart3grp {
974 fsl,pins = < 974 fsl,pins = <
975 MX8MM_IOMUXC_UART3_RXD 975 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
976 MX8MM_IOMUXC_UART3_TXD 976 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
977 MX8MM_IOMUXC_SD1_CLK_G 977 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
978 MX8MM_IOMUXC_SD1_CMD_G 978 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
979 >; 979 >;
980 }; 980 };
981 981
982 pinctrl_uart4: uart4grp { 982 pinctrl_uart4: uart4grp {
983 fsl,pins = < 983 fsl,pins = <
984 MX8MM_IOMUXC_UART4_RXD 984 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
985 MX8MM_IOMUXC_UART4_TXD 985 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
986 MX8MM_IOMUXC_SAI1_RXC_ 986 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
987 MX8MM_IOMUXC_SAI1_RXD0 987 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
988 MX8MM_IOMUXC_SAI1_RXD1 988 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
989 MX8MM_IOMUXC_SAI1_RXD2 989 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
990 MX8MM_IOMUXC_SAI1_RXD4 990 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
991 MX8MM_IOMUXC_SAI1_RXD5 991 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
992 MX8MM_IOMUXC_SAI1_RXFS 992 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
993 MX8MM_IOMUXC_GPIO1_IO0 993 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
994 >; 994 >;
995 }; 995 };
996 996
997 pinctrl_usdhc2: usdhc2grp { 997 pinctrl_usdhc2: usdhc2grp {
998 fsl,pins = < 998 fsl,pins = <
999 MX8MM_IOMUXC_SD2_CLK_U 999 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1000 MX8MM_IOMUXC_SD2_CMD_ 1000 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1001 MX8MM_IOMUXC_SD2_DATA 1001 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1002 MX8MM_IOMUXC_SD2_DATA 1002 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1003 MX8MM_IOMUXC_SD2_DATA 1003 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1004 MX8MM_IOMUXC_SD2_DATA 1004 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1005 >; 1005 >;
1006 }; 1006 };
1007 1007
1008 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1008 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1009 fsl,pins = < 1009 fsl,pins = <
1010 MX8MM_IOMUXC_SD2_CLK_ 1010 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1011 MX8MM_IOMUXC_SD2_CMD_ 1011 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1012 MX8MM_IOMUXC_SD2_DATA 1012 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1013 MX8MM_IOMUXC_SD2_DATA 1013 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1014 MX8MM_IOMUXC_SD2_DATA 1014 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1015 MX8MM_IOMUXC_SD2_DATA 1015 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1016 >; 1016 >;
1017 }; 1017 };
1018 1018
1019 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1019 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1020 fsl,pins = < 1020 fsl,pins = <
1021 MX8MM_IOMUXC_SD2_CLK_ 1021 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1022 MX8MM_IOMUXC_SD2_CMD_ 1022 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1023 MX8MM_IOMUXC_SD2_DATA 1023 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1024 MX8MM_IOMUXC_SD2_DATA 1024 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1025 MX8MM_IOMUXC_SD2_DATA 1025 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1026 MX8MM_IOMUXC_SD2_DATA 1026 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1027 >; 1027 >;
1028 }; 1028 };
1029 1029
1030 pinctrl_usdhc3: usdhc3grp { 1030 pinctrl_usdhc3: usdhc3grp {
1031 fsl,pins = < 1031 fsl,pins = <
1032 MX8MM_IOMUXC_NAND_WE_ 1032 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1033 MX8MM_IOMUXC_NAND_WP_ 1033 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1034 MX8MM_IOMUXC_NAND_DAT 1034 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1035 MX8MM_IOMUXC_NAND_DAT 1035 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1036 MX8MM_IOMUXC_NAND_DAT 1036 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1037 MX8MM_IOMUXC_NAND_DAT 1037 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1038 MX8MM_IOMUXC_NAND_RE_ 1038 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1039 MX8MM_IOMUXC_NAND_CE2 1039 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1040 MX8MM_IOMUXC_NAND_CE3 1040 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1041 MX8MM_IOMUXC_NAND_CLE 1041 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1042 MX8MM_IOMUXC_NAND_CE1 1042 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1043 >; 1043 >;
1044 }; 1044 };
1045 1045
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1047 fsl,pins = < 1047 fsl,pins = <
1048 MX8MM_IOMUXC_NAND_WE_ 1048 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1049 MX8MM_IOMUXC_NAND_WP_ 1049 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1050 MX8MM_IOMUXC_NAND_DAT 1050 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1051 MX8MM_IOMUXC_NAND_DAT 1051 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1052 MX8MM_IOMUXC_NAND_DAT 1052 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1053 MX8MM_IOMUXC_NAND_DAT 1053 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1054 MX8MM_IOMUXC_NAND_RE_ 1054 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1055 MX8MM_IOMUXC_NAND_CE2 1055 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1056 MX8MM_IOMUXC_NAND_CE3 1056 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1057 MX8MM_IOMUXC_NAND_CLE 1057 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1058 MX8MM_IOMUXC_NAND_CE1 1058 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1059 >; 1059 >;
1060 }; 1060 };
1061 1061
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1063 fsl,pins = < 1063 fsl,pins = <
1064 MX8MM_IOMUXC_NAND_WE_ 1064 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1065 MX8MM_IOMUXC_NAND_WP_ 1065 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1066 MX8MM_IOMUXC_NAND_DAT 1066 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1067 MX8MM_IOMUXC_NAND_DAT 1067 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1068 MX8MM_IOMUXC_NAND_DAT 1068 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1069 MX8MM_IOMUXC_NAND_DAT 1069 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1070 MX8MM_IOMUXC_NAND_RE_ 1070 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1071 MX8MM_IOMUXC_NAND_CE2 1071 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1072 MX8MM_IOMUXC_NAND_CE3 1072 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1073 MX8MM_IOMUXC_NAND_CLE 1073 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1074 MX8MM_IOMUXC_NAND_CE1 1074 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1075 >; 1075 >;
1076 }; 1076 };
1077 1077
1078 pinctrl_wdog: wdoggrp { 1078 pinctrl_wdog: wdoggrp {
1079 fsl,pins = < 1079 fsl,pins = <
1080 MX8MM_IOMUXC_GPIO1_IO 1080 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1081 >; 1081 >;
1082 }; 1082 };
1083 }; 1083 };
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