1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
13 12
14 #include "imx8mm.dtsi" 13 #include "imx8mm.dtsi"
15 14
16 / { 15 / {
17 model = "Gateworks Venice GW7902 i.MX8 16 model = "Gateworks Venice GW7902 i.MX8MM board";
18 compatible = "gw,imx8mm-gw7902", "fsl, 17 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19 18
20 aliases { 19 aliases {
21 ethernet1 = ð1; <<
22 usb0 = &usbotg1; 20 usb0 = &usbotg1;
23 usb1 = &usbotg2; 21 usb1 = &usbotg2;
24 }; 22 };
25 23
26 chosen { 24 chosen {
27 stdout-path = &uart2; 25 stdout-path = &uart2;
28 }; 26 };
29 27
30 memory@40000000 { 28 memory@40000000 {
31 device_type = "memory"; 29 device_type = "memory";
32 reg = <0x0 0x40000000 0 0x8000 30 reg = <0x0 0x40000000 0 0x80000000>;
33 }; 31 };
34 32
35 can20m: can20m { 33 can20m: can20m {
36 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
37 #clock-cells = <0>; 35 #clock-cells = <0>;
38 clock-frequency = <20000000>; 36 clock-frequency = <20000000>;
39 clock-output-names = "can20m"; 37 clock-output-names = "can20m";
40 }; 38 };
41 39
42 gpio-keys { 40 gpio-keys {
43 compatible = "gpio-keys"; 41 compatible = "gpio-keys";
44 42
45 key-user-pb { !! 43 user-pb {
46 label = "user_pb"; 44 label = "user_pb";
47 gpios = <&gpio 2 GPIO_ 45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48 linux,code = <BTN_0>; 46 linux,code = <BTN_0>;
49 }; 47 };
50 48
51 key-user-pb1x { !! 49 user-pb1x {
52 label = "user_pb1x"; 50 label = "user_pb1x";
53 linux,code = <BTN_1>; 51 linux,code = <BTN_1>;
54 interrupt-parent = <&g 52 interrupt-parent = <&gsc>;
55 interrupts = <0>; 53 interrupts = <0>;
56 }; 54 };
57 55
58 key-erased { 56 key-erased {
59 label = "key_erased"; 57 label = "key_erased";
60 linux,code = <BTN_2>; 58 linux,code = <BTN_2>;
61 interrupt-parent = <&g 59 interrupt-parent = <&gsc>;
62 interrupts = <1>; 60 interrupts = <1>;
63 }; 61 };
64 62
65 key-eeprom-wp { !! 63 eeprom-wp {
66 label = "eeprom_wp"; 64 label = "eeprom_wp";
67 linux,code = <BTN_3>; 65 linux,code = <BTN_3>;
68 interrupt-parent = <&g 66 interrupt-parent = <&gsc>;
69 interrupts = <2>; 67 interrupts = <2>;
70 }; 68 };
71 69
72 key-tamper { !! 70 tamper {
73 label = "tamper"; 71 label = "tamper";
74 linux,code = <BTN_4>; 72 linux,code = <BTN_4>;
75 interrupt-parent = <&g 73 interrupt-parent = <&gsc>;
76 interrupts = <5>; 74 interrupts = <5>;
77 }; 75 };
78 76
79 switch-hold { 77 switch-hold {
80 label = "switch_hold"; 78 label = "switch_hold";
81 linux,code = <BTN_5>; 79 linux,code = <BTN_5>;
82 interrupt-parent = <&g 80 interrupt-parent = <&gsc>;
83 interrupts = <7>; 81 interrupts = <7>;
84 }; 82 };
85 }; 83 };
86 84
87 led-controller { 85 led-controller {
88 compatible = "gpio-leds"; 86 compatible = "gpio-leds";
89 pinctrl-names = "default"; 87 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_gpio_led 88 pinctrl-0 = <&pinctrl_gpio_leds>;
91 89
92 led-0 { 90 led-0 {
93 function = LED_FUNCTIO 91 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_ 92 color = <LED_COLOR_ID_GREEN>;
95 label = "panel1"; 93 label = "panel1";
96 gpios = <&gpio3 21 GPI 94 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97 default-state = "off"; 95 default-state = "off";
98 }; 96 };
99 97
100 led-1 { 98 led-1 {
101 function = LED_FUNCTIO 99 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_ 100 color = <LED_COLOR_ID_GREEN>;
103 label = "panel2"; 101 label = "panel2";
104 gpios = <&gpio3 23 GPI 102 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105 default-state = "off"; 103 default-state = "off";
106 }; 104 };
107 105
108 led-2 { 106 led-2 {
109 function = LED_FUNCTIO 107 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_ 108 color = <LED_COLOR_ID_GREEN>;
111 label = "panel3"; 109 label = "panel3";
112 gpios = <&gpio3 22 GPI 110 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113 default-state = "off"; 111 default-state = "off";
114 }; 112 };
115 113
116 led-3 { 114 led-3 {
117 function = LED_FUNCTIO 115 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_ 116 color = <LED_COLOR_ID_GREEN>;
119 label = "panel4"; 117 label = "panel4";
120 gpios = <&gpio3 20 GPI 118 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121 default-state = "off"; 119 default-state = "off";
122 }; 120 };
123 121
124 led-4 { 122 led-4 {
125 function = LED_FUNCTIO 123 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_ 124 color = <LED_COLOR_ID_GREEN>;
127 label = "panel5"; 125 label = "panel5";
128 gpios = <&gpio3 25 GPI 126 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129 default-state = "off"; 127 default-state = "off";
130 }; 128 };
131 }; 129 };
132 130
133 pcie0_refclk: pcie0-refclk { <<
134 compatible = "fixed-clock"; <<
135 #clock-cells = <0>; <<
136 clock-frequency = <100000000>; <<
137 }; <<
138 <<
139 pps { 131 pps {
140 compatible = "pps-gpio"; 132 compatible = "pps-gpio";
141 pinctrl-names = "default"; 133 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pps>; 134 pinctrl-0 = <&pinctrl_pps>;
143 gpios = <&gpio3 24 GPIO_ACTIVE 135 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144 status = "okay"; 136 status = "okay";
145 }; 137 };
146 138
147 reg_3p3v: regulator-3p3v { 139 reg_3p3v: regulator-3p3v {
148 compatible = "regulator-fixed" 140 compatible = "regulator-fixed";
149 regulator-name = "3P3V"; 141 regulator-name = "3P3V";
150 regulator-min-microvolt = <330 142 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <330 143 regulator-max-microvolt = <3300000>;
152 regulator-always-on; 144 regulator-always-on;
153 }; 145 };
154 146
155 reg_usb1_vbus: regulator-usb1 { 147 reg_usb1_vbus: regulator-usb1 {
156 compatible = "regulator-fixed" 148 compatible = "regulator-fixed";
157 pinctrl-names = "default"; 149 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_usb1 150 pinctrl-0 = <&pinctrl_reg_usb1>;
159 regulator-name = "usb_usb1_vbu 151 regulator-name = "usb_usb1_vbus";
160 gpio = <&gpio2 7 GPIO_ACTIVE_H 152 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161 enable-active-high; 153 enable-active-high;
162 regulator-min-microvolt = <500 154 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <500 155 regulator-max-microvolt = <5000000>;
164 }; 156 };
165 157
166 reg_wifi: regulator-wifi { 158 reg_wifi: regulator-wifi {
167 compatible = "regulator-fixed" 159 compatible = "regulator-fixed";
168 pinctrl-names = "default"; 160 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_reg_wl>; 161 pinctrl-0 = <&pinctrl_reg_wl>;
170 regulator-name = "wifi"; 162 regulator-name = "wifi";
171 gpio = <&gpio2 19 GPIO_ACTIVE_ 163 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172 enable-active-high; 164 enable-active-high;
173 startup-delay-us = <100>; 165 startup-delay-us = <100>;
174 regulator-min-microvolt = <330 166 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <330 167 regulator-max-microvolt = <3300000>;
176 }; 168 };
177 }; 169 };
178 170
179 &A53_0 { 171 &A53_0 {
180 cpu-supply = <&buck2>; 172 cpu-supply = <&buck2>;
181 }; 173 };
182 174
183 &A53_1 { 175 &A53_1 {
184 cpu-supply = <&buck2>; 176 cpu-supply = <&buck2>;
185 }; 177 };
186 178
187 &A53_2 { 179 &A53_2 {
188 cpu-supply = <&buck2>; 180 cpu-supply = <&buck2>;
189 }; 181 };
190 182
191 &A53_3 { 183 &A53_3 {
192 cpu-supply = <&buck2>; 184 cpu-supply = <&buck2>;
193 }; 185 };
194 186
195 &ddrc { 187 &ddrc {
196 operating-points-v2 = <&ddrc_opp_table 188 operating-points-v2 = <&ddrc_opp_table>;
197 189
198 ddrc_opp_table: opp-table { 190 ddrc_opp_table: opp-table {
199 compatible = "operating-points 191 compatible = "operating-points-v2";
200 192
201 opp-25000000 { !! 193 opp-25M {
202 opp-hz = /bits/ 64 <25 194 opp-hz = /bits/ 64 <25000000>;
203 }; 195 };
204 196
205 opp-100000000 { !! 197 opp-100M {
206 opp-hz = /bits/ 64 <10 198 opp-hz = /bits/ 64 <100000000>;
207 }; 199 };
208 200
209 opp-750000000 { !! 201 opp-750M {
210 opp-hz = /bits/ 64 <75 202 opp-hz = /bits/ 64 <750000000>;
211 }; 203 };
212 }; 204 };
213 }; 205 };
214 206
215 &ecspi1 { 207 &ecspi1 {
216 pinctrl-names = "default"; 208 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spi1>; 209 pinctrl-0 = <&pinctrl_spi1>;
218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 210 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219 status = "okay"; 211 status = "okay";
220 212
221 can@0 { 213 can@0 {
222 compatible = "microchip,mcp251 214 compatible = "microchip,mcp2515";
223 reg = <0>; 215 reg = <0>;
224 clocks = <&can20m>; 216 clocks = <&can20m>;
>> 217 oscillator-frequency = <20000000>;
225 interrupt-parent = <&gpio2>; 218 interrupt-parent = <&gpio2>;
226 interrupts = <3 IRQ_TYPE_LEVEL 219 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227 spi-max-frequency = <10000000> 220 spi-max-frequency = <10000000>;
228 }; 221 };
229 }; 222 };
230 223
231 /* off-board header */ 224 /* off-board header */
232 &ecspi2 { 225 &ecspi2 {
233 pinctrl-names = "default"; 226 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_spi2>; 227 pinctrl-0 = <&pinctrl_spi2>;
235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 228 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236 status = "okay"; 229 status = "okay";
237 }; 230 };
238 231
239 &fec1 { 232 &fec1 {
240 pinctrl-names = "default"; 233 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_fec1>; 234 pinctrl-0 = <&pinctrl_fec1>;
242 phy-mode = "rgmii-id"; 235 phy-mode = "rgmii-id";
243 phy-handle = <ðphy0>; 236 phy-handle = <ðphy0>;
244 local-mac-address = [00 00 00 00 00 00 237 local-mac-address = [00 00 00 00 00 00];
245 status = "okay"; 238 status = "okay";
246 239
247 mdio { 240 mdio {
248 #address-cells = <1>; 241 #address-cells = <1>;
249 #size-cells = <0>; 242 #size-cells = <0>;
250 243
251 ethphy0: ethernet-phy@0 { 244 ethphy0: ethernet-phy@0 {
252 compatible = "ethernet 245 compatible = "ethernet-phy-ieee802.3-c22";
253 reg = <0>; 246 reg = <0>;
254 ti,rx-internal-delay = 247 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255 ti,tx-internal-delay = 248 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256 tx-fifo-depth = <DP838 249 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257 rx-fifo-depth = <DP838 250 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 }; 251 };
259 }; 252 };
260 }; 253 };
261 254
262 &gpio1 { <<
263 gpio-line-names = "", "", "", "", "", <<
264 "m2_pwr_en", "", "", "", "", " <<
265 "", "", "", "", "", "", "", "" <<
266 "", "", "", "", "", "", "", "" <<
267 }; <<
268 <<
269 &gpio2 { <<
270 gpio-line-names = "", "", "", "", "", <<
271 "uart2_en#", "", "", "", "", " <<
272 "", "", "", "", "", "", "", "" <<
273 "", "", "", "", "", "", "", "" <<
274 }; <<
275 <<
276 &gpio3 { <<
277 gpio-line-names = "", "m2_gdis#", "", <<
278 "", "", "", "", "", "", "", "" <<
279 "", "", "", "", "", "", "", "" <<
280 "", "", "", "", "", "", "", "" <<
281 }; <<
282 <<
283 &gpio4 { <<
284 gpio-line-names = "", "", "", "", "", <<
285 "", "", "", "amp_gpio3", "amp_ <<
286 "lte_pwr#", "lte_rst", "lte_in <<
287 "amp_gpio4", "app_gpio1", "vdd <<
288 "", "uart1_term", "uart1_half" <<
289 "mipi_gpio1", "", "", ""; <<
290 }; <<
291 <<
292 &gpio5 { <<
293 gpio-line-names = "", "", "", "mipi_gp <<
294 "mipi_gpio3", "mipi_gpio2", "" <<
295 "", "", "", "", "", "", "", "" <<
296 "", "", "", "", "", "", "", "" <<
297 "", "", "", "", "", "", "", "" <<
298 }; <<
299 <<
300 &i2c1 { 255 &i2c1 {
301 clock-frequency = <100000>; 256 clock-frequency = <100000>;
302 pinctrl-names = "default", "gpio"; !! 257 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c1>; 258 pinctrl-0 = <&pinctrl_i2c1>;
304 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
307 status = "okay"; 259 status = "okay";
308 260
309 gsc: gsc@20 { 261 gsc: gsc@20 {
310 compatible = "gw,gsc"; 262 compatible = "gw,gsc";
311 reg = <0x20>; 263 reg = <0x20>;
312 pinctrl-0 = <&pinctrl_gsc>; 264 pinctrl-0 = <&pinctrl_gsc>;
313 interrupt-parent = <&gpio2>; 265 interrupt-parent = <&gpio2>;
314 interrupts = <6 IRQ_TYPE_EDGE_ 266 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315 interrupt-controller; 267 interrupt-controller;
316 #interrupt-cells = <1>; 268 #interrupt-cells = <1>;
317 #address-cells = <1>; <<
318 #size-cells = <0>; <<
319 269
320 adc { 270 adc {
321 compatible = "gw,gsc-a 271 compatible = "gw,gsc-adc";
322 #address-cells = <1>; 272 #address-cells = <1>;
323 #size-cells = <0>; 273 #size-cells = <0>;
324 274
325 channel@6 { 275 channel@6 {
326 gw,mode = <0>; 276 gw,mode = <0>;
327 reg = <0x06>; 277 reg = <0x06>;
328 label = "temp" 278 label = "temp";
329 }; 279 };
330 280
331 channel@8 { 281 channel@8 {
332 gw,mode = <3>; !! 282 gw,mode = <1>;
333 reg = <0x08>; 283 reg = <0x08>;
334 label = "vdd_b 284 label = "vdd_bat";
335 }; 285 };
336 286
337 channel@82 { 287 channel@82 {
338 gw,mode = <2>; 288 gw,mode = <2>;
339 reg = <0x82>; 289 reg = <0x82>;
340 label = "vin"; 290 label = "vin";
341 gw,voltage-div 291 gw,voltage-divider-ohms = <22100 1000>;
342 gw,voltage-off 292 gw,voltage-offset-microvolt = <700000>;
343 }; 293 };
344 294
345 channel@84 { 295 channel@84 {
346 gw,mode = <2>; 296 gw,mode = <2>;
347 reg = <0x84>; 297 reg = <0x84>;
348 label = "vin_4 298 label = "vin_4p0";
349 gw,voltage-div 299 gw,voltage-divider-ohms = <10000 10000>;
350 }; 300 };
351 301
352 channel@86 { 302 channel@86 {
353 gw,mode = <2>; 303 gw,mode = <2>;
354 reg = <0x86>; 304 reg = <0x86>;
355 label = "vdd_3 305 label = "vdd_3p3";
356 gw,voltage-div 306 gw,voltage-divider-ohms = <10000 10000>;
357 }; 307 };
358 308
359 channel@88 { 309 channel@88 {
360 gw,mode = <2>; 310 gw,mode = <2>;
361 reg = <0x88>; 311 reg = <0x88>;
362 label = "vdd_0 312 label = "vdd_0p9";
363 }; 313 };
364 314
365 channel@8c { 315 channel@8c {
366 gw,mode = <2>; 316 gw,mode = <2>;
367 reg = <0x8c>; 317 reg = <0x8c>;
368 label = "vdd_s 318 label = "vdd_soc";
369 }; 319 };
370 320
371 channel@8e { 321 channel@8e {
372 gw,mode = <2>; 322 gw,mode = <2>;
373 reg = <0x8e>; 323 reg = <0x8e>;
374 label = "vdd_a 324 label = "vdd_arm";
375 }; 325 };
376 326
377 channel@90 { 327 channel@90 {
378 gw,mode = <2>; 328 gw,mode = <2>;
379 reg = <0x90>; 329 reg = <0x90>;
380 label = "vdd_1 330 label = "vdd_1p8";
381 }; 331 };
382 332
383 channel@92 { 333 channel@92 {
384 gw,mode = <2>; 334 gw,mode = <2>;
385 reg = <0x92>; 335 reg = <0x92>;
386 label = "vdd_d 336 label = "vdd_dram";
387 }; 337 };
388 338
389 channel@98 { 339 channel@98 {
390 gw,mode = <2>; 340 gw,mode = <2>;
391 reg = <0x98>; 341 reg = <0x98>;
392 label = "vdd_1 342 label = "vdd_1p0";
393 }; 343 };
394 344
395 channel@9a { 345 channel@9a {
396 gw,mode = <2>; 346 gw,mode = <2>;
397 reg = <0x9a>; 347 reg = <0x9a>;
398 label = "vdd_2 348 label = "vdd_2p5";
399 gw,voltage-div 349 gw,voltage-divider-ohms = <10000 10000>;
400 }; 350 };
401 351
402 channel@9c { <<
403 gw,mode = <2>; <<
404 reg = <0x9c>; <<
405 label = "vdd_5 <<
406 gw,voltage-div <<
407 }; <<
408 <<
409 channel@a2 { 352 channel@a2 {
410 gw,mode = <2>; 353 gw,mode = <2>;
411 reg = <0xa2>; 354 reg = <0xa2>;
412 label = "vdd_g 355 label = "vdd_gsc";
413 gw,voltage-div 356 gw,voltage-divider-ohms = <10000 10000>;
414 }; 357 };
415 }; 358 };
416 }; 359 };
417 360
418 gpio: gpio@23 { 361 gpio: gpio@23 {
419 compatible = "nxp,pca9555"; 362 compatible = "nxp,pca9555";
420 reg = <0x23>; 363 reg = <0x23>;
421 gpio-controller; 364 gpio-controller;
422 #gpio-cells = <2>; 365 #gpio-cells = <2>;
423 interrupt-parent = <&gsc>; 366 interrupt-parent = <&gsc>;
424 interrupts = <4>; 367 interrupts = <4>;
425 }; 368 };
426 369
427 pmic@4b { 370 pmic@4b {
428 compatible = "rohm,bd71847"; 371 compatible = "rohm,bd71847";
429 reg = <0x4b>; 372 reg = <0x4b>;
430 pinctrl-names = "default"; 373 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_pmic>; 374 pinctrl-0 = <&pinctrl_pmic>;
432 interrupt-parent = <&gpio3>; 375 interrupt-parent = <&gpio3>;
433 interrupts = <8 IRQ_TYPE_LEVEL 376 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
434 rohm,reset-snvs-powered; 377 rohm,reset-snvs-powered;
435 #clock-cells = <0>; 378 #clock-cells = <0>;
436 clocks = <&osc_32k>; !! 379 clocks = <&osc_32k 0>;
437 clock-output-names = "clk-32k- 380 clock-output-names = "clk-32k-out";
438 381
439 regulators { 382 regulators {
440 /* vdd_soc: 0.805-0.90 383 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
441 BUCK1 { 384 BUCK1 {
442 regulator-name 385 regulator-name = "buck1";
443 regulator-min- 386 regulator-min-microvolt = <700000>;
444 regulator-max- 387 regulator-max-microvolt = <1300000>;
445 regulator-boot 388 regulator-boot-on;
446 regulator-alwa 389 regulator-always-on;
447 regulator-ramp 390 regulator-ramp-delay = <1250>;
448 }; 391 };
449 392
450 /* vdd_arm: 0.805-1.0V 393 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
451 buck2: BUCK2 { 394 buck2: BUCK2 {
452 regulator-name 395 regulator-name = "buck2";
453 regulator-min- 396 regulator-min-microvolt = <700000>;
454 regulator-max- 397 regulator-max-microvolt = <1300000>;
455 regulator-boot 398 regulator-boot-on;
456 regulator-alwa 399 regulator-always-on;
457 regulator-ramp 400 regulator-ramp-delay = <1250>;
458 rohm,dvs-run-v 401 rohm,dvs-run-voltage = <1000000>;
459 rohm,dvs-idle- 402 rohm,dvs-idle-voltage = <900000>;
460 }; 403 };
461 404
462 /* vdd_0p9: 0.805-1.0V 405 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
463 BUCK3 { 406 BUCK3 {
464 regulator-name 407 regulator-name = "buck3";
465 regulator-min- 408 regulator-min-microvolt = <700000>;
466 regulator-max- 409 regulator-max-microvolt = <1350000>;
467 regulator-boot 410 regulator-boot-on;
468 regulator-alwa 411 regulator-always-on;
469 }; 412 };
470 413
471 /* vdd_3p3 */ 414 /* vdd_3p3 */
472 BUCK4 { 415 BUCK4 {
473 regulator-name 416 regulator-name = "buck4";
474 regulator-min- 417 regulator-min-microvolt = <3000000>;
475 regulator-max- 418 regulator-max-microvolt = <3300000>;
476 regulator-boot 419 regulator-boot-on;
477 regulator-alwa 420 regulator-always-on;
478 }; 421 };
479 422
480 /* vdd_1p8 */ 423 /* vdd_1p8 */
481 BUCK5 { 424 BUCK5 {
482 regulator-name 425 regulator-name = "buck5";
483 regulator-min- 426 regulator-min-microvolt = <1605000>;
484 regulator-max- 427 regulator-max-microvolt = <1995000>;
485 regulator-boot 428 regulator-boot-on;
486 regulator-alwa 429 regulator-always-on;
487 }; 430 };
488 431
489 /* vdd_dram */ 432 /* vdd_dram */
490 BUCK6 { 433 BUCK6 {
491 regulator-name 434 regulator-name = "buck6";
492 regulator-min- 435 regulator-min-microvolt = <800000>;
493 regulator-max- 436 regulator-max-microvolt = <1400000>;
494 regulator-boot 437 regulator-boot-on;
495 regulator-alwa 438 regulator-always-on;
496 }; 439 };
497 440
498 /* nvcc_snvs_1p8 */ 441 /* nvcc_snvs_1p8 */
499 LDO1 { 442 LDO1 {
500 regulator-name 443 regulator-name = "ldo1";
501 regulator-min- 444 regulator-min-microvolt = <1600000>;
502 regulator-max- 445 regulator-max-microvolt = <1900000>;
503 regulator-boot 446 regulator-boot-on;
504 regulator-alwa 447 regulator-always-on;
505 }; 448 };
506 449
507 /* vdd_snvs_0p8 */ 450 /* vdd_snvs_0p8 */
508 LDO2 { 451 LDO2 {
509 regulator-name 452 regulator-name = "ldo2";
510 regulator-min- 453 regulator-min-microvolt = <800000>;
511 regulator-max- 454 regulator-max-microvolt = <900000>;
512 regulator-boot 455 regulator-boot-on;
513 regulator-alwa 456 regulator-always-on;
514 }; 457 };
515 458
516 /* vdda_1p8 */ 459 /* vdda_1p8 */
517 LDO3 { 460 LDO3 {
518 regulator-name 461 regulator-name = "ldo3";
519 regulator-min- 462 regulator-min-microvolt = <1800000>;
520 regulator-max- 463 regulator-max-microvolt = <3300000>;
521 regulator-boot 464 regulator-boot-on;
522 regulator-alwa 465 regulator-always-on;
523 }; 466 };
524 467
525 LDO4 { 468 LDO4 {
526 regulator-name 469 regulator-name = "ldo4";
527 regulator-min- 470 regulator-min-microvolt = <900000>;
528 regulator-max- 471 regulator-max-microvolt = <1800000>;
529 regulator-boot 472 regulator-boot-on;
530 regulator-alwa 473 regulator-always-on;
531 }; 474 };
532 475
533 LDO6 { 476 LDO6 {
534 regulator-name 477 regulator-name = "ldo6";
535 regulator-min- 478 regulator-min-microvolt = <900000>;
536 regulator-max- 479 regulator-max-microvolt = <1800000>;
537 regulator-boot 480 regulator-boot-on;
538 regulator-alwa 481 regulator-always-on;
539 }; 482 };
540 }; 483 };
541 }; 484 };
542 485
543 eeprom@50 { 486 eeprom@50 {
544 compatible = "atmel,24c02"; 487 compatible = "atmel,24c02";
545 reg = <0x50>; 488 reg = <0x50>;
546 pagesize = <16>; 489 pagesize = <16>;
547 }; 490 };
548 491
549 eeprom@51 { 492 eeprom@51 {
550 compatible = "atmel,24c02"; 493 compatible = "atmel,24c02";
551 reg = <0x51>; 494 reg = <0x51>;
552 pagesize = <16>; 495 pagesize = <16>;
553 }; 496 };
554 497
555 eeprom@52 { 498 eeprom@52 {
556 compatible = "atmel,24c02"; 499 compatible = "atmel,24c02";
557 reg = <0x52>; 500 reg = <0x52>;
558 pagesize = <16>; 501 pagesize = <16>;
559 }; 502 };
560 503
561 eeprom@53 { 504 eeprom@53 {
562 compatible = "atmel,24c02"; 505 compatible = "atmel,24c02";
563 reg = <0x53>; 506 reg = <0x53>;
564 pagesize = <16>; 507 pagesize = <16>;
565 }; 508 };
566 509
567 rtc@68 { 510 rtc@68 {
568 compatible = "dallas,ds1672"; 511 compatible = "dallas,ds1672";
569 reg = <0x68>; 512 reg = <0x68>;
570 }; 513 };
571 }; 514 };
572 515
573 &i2c2 { 516 &i2c2 {
574 clock-frequency = <400000>; 517 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio"; !! 518 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_i2c2>; 519 pinctrl-0 = <&pinctrl_i2c2>;
577 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
580 status = "okay"; 520 status = "okay";
581 521
582 accelerometer@19 { 522 accelerometer@19 {
583 compatible = "st,lis2de12"; 523 compatible = "st,lis2de12";
584 pinctrl-names = "default"; 524 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_accel>; 525 pinctrl-0 = <&pinctrl_accel>;
586 reg = <0x19>; 526 reg = <0x19>;
587 st,drdy-int-pin = <1>; 527 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>; 528 interrupt-parent = <&gpio1>;
589 interrupts = <12 IRQ_TYPE_LEVE 529 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 530 interrupt-names = "INT1";
590 }; 531 };
591 }; 532 };
592 533
593 /* off-board header */ 534 /* off-board header */
594 &i2c3 { 535 &i2c3 {
595 clock-frequency = <400000>; 536 clock-frequency = <400000>;
596 pinctrl-names = "default", "gpio"; !! 537 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_i2c3>; 538 pinctrl-0 = <&pinctrl_i2c3>;
598 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
601 status = "okay"; 539 status = "okay";
602 }; 540 };
603 541
604 /* off-board header */ 542 /* off-board header */
605 &i2c4 { 543 &i2c4 {
606 clock-frequency = <400000>; 544 clock-frequency = <400000>;
607 pinctrl-names = "default", "gpio"; <<
608 pinctrl-0 = <&pinctrl_i2c4>; <<
609 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
612 status = "okay"; <<
613 }; <<
614 <<
615 &pcie_phy { <<
616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
617 fsl,clkreq-unsupported; <<
618 clocks = <&pcie0_refclk>; <<
619 clock-names = "ref"; <<
620 status = "okay"; <<
621 }; <<
622 <<
623 &pcie0 { <<
624 pinctrl-names = "default"; 545 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pcie0>; !! 546 pinctrl-0 = <&pinctrl_i2c4>;
626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW <<
627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <<
628 <&clk IMX8MM_CLK_PCIE1_AUX>; <<
629 assigned-clocks = <&clk IMX8MM_CLK_PCI <<
630 <&clk IMX8MM_CLK_PCI <<
631 assigned-clock-rates = <10000000>, <25 <<
632 assigned-clock-parents = <&clk IMX8MM_ <<
633 <&clk IMX8MM_ <<
634 status = "okay"; 547 status = "okay";
635 <<
636 pcie@0,0 { <<
637 reg = <0x0000 0 0 0 0>; <<
638 device_type = "pci"; <<
639 #address-cells = <3>; <<
640 #size-cells = <2>; <<
641 ranges; <<
642 <<
643 eth1: ethernet@0,0 { <<
644 reg = <0x0000 0 0 0 0> <<
645 #address-cells = <3>; <<
646 #size-cells = <2>; <<
647 ranges; <<
648 <<
649 local-mac-address = [0 <<
650 }; <<
651 }; <<
652 }; 548 };
653 549
654 /* off-board header */ 550 /* off-board header */
655 &sai3 { 551 &sai3 {
656 pinctrl-names = "default"; 552 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_sai3>; 553 pinctrl-0 = <&pinctrl_sai3>;
658 assigned-clocks = <&clk IMX8MM_CLK_SAI 554 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
659 assigned-clock-parents = <&clk IMX8MM_ 555 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
660 assigned-clock-rates = <24576000>; 556 assigned-clock-rates = <24576000>;
661 status = "okay"; 557 status = "okay";
662 }; 558 };
663 559
664 /* RS232/RS485/RS422 selectable */ 560 /* RS232/RS485/RS422 selectable */
665 &uart1 { 561 &uart1 {
666 pinctrl-names = "default"; 562 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 563 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
668 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW 564 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
669 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW !! 565 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
670 status = "okay"; 566 status = "okay";
671 }; 567 };
672 568
673 /* RS232 console */ 569 /* RS232 console */
674 &uart2 { 570 &uart2 {
675 pinctrl-names = "default"; 571 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_uart2>; 572 pinctrl-0 = <&pinctrl_uart2>;
677 status = "okay"; 573 status = "okay";
678 }; 574 };
679 575
680 /* bluetooth HCI */ 576 /* bluetooth HCI */
681 &uart3 { 577 &uart3 {
682 pinctrl-names = "default"; 578 pinctrl-names = "default";
683 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 579 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
684 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 580 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
685 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 581 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
686 status = "okay"; 582 status = "okay";
687 583
688 bluetooth { 584 bluetooth {
689 compatible = "brcm,bcm4330-bt" 585 compatible = "brcm,bcm4330-bt";
690 shutdown-gpios = <&gpio2 12 GP 586 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
691 }; 587 };
692 }; 588 };
693 589
694 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 590 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
695 &uart4 { 591 &uart4 {
696 pinctrl-names = "default"; 592 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_uart4>; 593 pinctrl-0 = <&pinctrl_uart4>;
698 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW> 594 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
699 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW> 595 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
700 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW> 596 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
701 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW> 597 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
702 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW> 598 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
703 status = "okay"; 599 status = "okay";
704 }; 600 };
705 601
706 &usbotg1 { 602 &usbotg1 {
707 dr_mode = "host"; 603 dr_mode = "host";
708 vbus-supply = <®_usb1_vbus>; 604 vbus-supply = <®_usb1_vbus>;
709 disable-over-current; 605 disable-over-current;
710 status = "okay"; 606 status = "okay";
711 }; 607 };
712 608
713 &usbotg2 { 609 &usbotg2 {
714 dr_mode = "host"; 610 dr_mode = "host";
715 disable-over-current; 611 disable-over-current;
716 status = "okay"; 612 status = "okay";
717 }; 613 };
718 614
719 /* SDIO WiFi */ 615 /* SDIO WiFi */
720 &usdhc2 { 616 &usdhc2 {
721 pinctrl-names = "default", "state_100m !! 617 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_usdhc2>; 618 pinctrl-0 = <&pinctrl_usdhc2>;
723 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; <<
724 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; <<
725 bus-width = <4>; 619 bus-width = <4>;
726 non-removable; 620 non-removable;
727 vmmc-supply = <®_wifi>; 621 vmmc-supply = <®_wifi>;
728 #address-cells = <1>; <<
729 #size-cells = <0>; <<
730 status = "okay"; 622 status = "okay";
731 <<
732 wifi@0 { <<
733 compatible = "brcm,bcm43455-fm <<
734 reg = <0>; <<
735 }; <<
736 }; 623 };
737 624
738 /* eMMC */ 625 /* eMMC */
739 &usdhc3 { 626 &usdhc3 {
740 pinctrl-names = "default", "state_100m 627 pinctrl-names = "default", "state_100mhz", "state_200mhz";
741 pinctrl-0 = <&pinctrl_usdhc3>; 628 pinctrl-0 = <&pinctrl_usdhc3>;
742 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 629 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
743 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 630 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
744 bus-width = <8>; 631 bus-width = <8>;
745 non-removable; 632 non-removable;
746 status = "okay"; 633 status = "okay";
747 }; 634 };
748 635
749 &wdog1 { 636 &wdog1 {
750 pinctrl-names = "default"; 637 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_wdog>; 638 pinctrl-0 = <&pinctrl_wdog>;
752 fsl,ext-reset-output; 639 fsl,ext-reset-output;
753 status = "okay"; 640 status = "okay";
754 }; 641 };
755 642
756 &iomuxc { 643 &iomuxc {
757 pinctrl-names = "default"; 644 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_hog>; 645 pinctrl-0 = <&pinctrl_hog>;
759 646
760 pinctrl_hog: hoggrp { 647 pinctrl_hog: hoggrp {
761 fsl,pins = < 648 fsl,pins = <
762 MX8MM_IOMUXC_NAND_CE0_ 649 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
763 MX8MM_IOMUXC_GPIO1_IO0 !! 650 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
764 MX8MM_IOMUXC_GPIO1_IO1 <<
765 MX8MM_IOMUXC_NAND_DATA 651 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
766 MX8MM_IOMUXC_GPIO1_IO1 652 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
767 MX8MM_IOMUXC_SAI1_TXD6 <<
768 MX8MM_IOMUXC_SAI1_TXD5 <<
769 MX8MM_IOMUXC_SAI1_TXD4 <<
770 MX8MM_IOMUXC_SAI1_TXD2 653 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
771 MX8MM_IOMUXC_SAI1_TXD0 654 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
772 MX8MM_IOMUXC_SAI1_TXC_ 655 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
773 MX8MM_IOMUXC_SAI1_MCLK 656 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
774 MX8MM_IOMUXC_SAI2_RXFS 657 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
775 MX8MM_IOMUXC_SAI2_RXC_ <<
776 MX8MM_IOMUXC_SAI2_MCLK 658 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
777 MX8MM_IOMUXC_SD1_DATA6 659 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
778 MX8MM_IOMUXC_SAI3_RXFS 660 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
779 MX8MM_IOMUXC_SPDIF_EXT 661 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
780 MX8MM_IOMUXC_SPDIF_RX_ 662 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
781 MX8MM_IOMUXC_SPDIF_TX_ 663 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
782 >; 664 >;
783 }; 665 };
784 666
785 pinctrl_accel: accelgrp { 667 pinctrl_accel: accelgrp {
786 fsl,pins = < 668 fsl,pins = <
787 MX8MM_IOMUXC_GPIO1_IO1 669 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
788 >; 670 >;
789 }; 671 };
790 672
791 pinctrl_fec1: fec1grp { 673 pinctrl_fec1: fec1grp {
792 fsl,pins = < 674 fsl,pins = <
793 MX8MM_IOMUXC_ENET_MDC_ 675 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
794 MX8MM_IOMUXC_ENET_MDIO 676 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
795 MX8MM_IOMUXC_ENET_TD3_ 677 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
796 MX8MM_IOMUXC_ENET_TD2_ 678 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
797 MX8MM_IOMUXC_ENET_TD1_ 679 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
798 MX8MM_IOMUXC_ENET_TD0_ 680 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
799 MX8MM_IOMUXC_ENET_RD3_ 681 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
800 MX8MM_IOMUXC_ENET_RD2_ 682 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
801 MX8MM_IOMUXC_ENET_RD1_ 683 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
802 MX8MM_IOMUXC_ENET_RD0_ 684 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
803 MX8MM_IOMUXC_ENET_TXC_ 685 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
804 MX8MM_IOMUXC_ENET_RXC_ 686 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
805 MX8MM_IOMUXC_ENET_RX_C 687 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
806 MX8MM_IOMUXC_ENET_TX_C 688 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
807 MX8MM_IOMUXC_GPIO1_IO1 689 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
808 MX8MM_IOMUXC_GPIO1_IO1 690 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
>> 691 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
>> 692 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
809 >; 693 >;
810 }; 694 };
811 695
812 pinctrl_gsc: gscgrp { 696 pinctrl_gsc: gscgrp {
813 fsl,pins = < 697 fsl,pins = <
814 MX8MM_IOMUXC_SD1_DATA4 698 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
815 >; 699 >;
816 }; 700 };
817 701
818 pinctrl_i2c1: i2c1grp { 702 pinctrl_i2c1: i2c1grp {
819 fsl,pins = < 703 fsl,pins = <
820 MX8MM_IOMUXC_I2C1_SCL_ 704 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
821 MX8MM_IOMUXC_I2C1_SDA_ 705 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
822 >; 706 >;
823 }; 707 };
824 708
825 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
826 fsl,pins = < <<
827 MX8MM_IOMUXC_I2C1_SCL_ <<
828 MX8MM_IOMUXC_I2C1_SDA_ <<
829 >; <<
830 }; <<
831 <<
832 pinctrl_i2c2: i2c2grp { 709 pinctrl_i2c2: i2c2grp {
833 fsl,pins = < 710 fsl,pins = <
834 MX8MM_IOMUXC_I2C2_SCL_ 711 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
835 MX8MM_IOMUXC_I2C2_SDA_ 712 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
836 >; 713 >;
837 }; 714 };
838 715
839 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
840 fsl,pins = < <<
841 MX8MM_IOMUXC_I2C2_SCL_ <<
842 MX8MM_IOMUXC_I2C2_SDA_ <<
843 >; <<
844 }; <<
845 <<
846 pinctrl_i2c3: i2c3grp { 716 pinctrl_i2c3: i2c3grp {
847 fsl,pins = < 717 fsl,pins = <
848 MX8MM_IOMUXC_I2C3_SCL_ 718 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
849 MX8MM_IOMUXC_I2C3_SDA_ 719 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
850 >; 720 >;
851 }; 721 };
852 722
853 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
854 fsl,pins = < <<
855 MX8MM_IOMUXC_I2C3_SCL_ <<
856 MX8MM_IOMUXC_I2C3_SDA_ <<
857 >; <<
858 }; <<
859 <<
860 pinctrl_i2c4: i2c4grp { 723 pinctrl_i2c4: i2c4grp {
861 fsl,pins = < 724 fsl,pins = <
862 MX8MM_IOMUXC_I2C4_SCL_ 725 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C4_SDA_ 726 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
864 >; 727 >;
865 }; 728 };
866 729
867 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
868 fsl,pins = < <<
869 MX8MM_IOMUXC_I2C4_SCL_ <<
870 MX8MM_IOMUXC_I2C4_SDA_ <<
871 >; <<
872 }; <<
873 <<
874 pinctrl_gpio_leds: gpioledgrp { 730 pinctrl_gpio_leds: gpioledgrp {
875 fsl,pins = < 731 fsl,pins = <
876 MX8MM_IOMUXC_SAI5_RXD0 732 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
877 MX8MM_IOMUXC_SAI5_RXD2 733 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
878 MX8MM_IOMUXC_SAI5_RXD1 734 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
879 MX8MM_IOMUXC_SAI5_RXC_ 735 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
880 MX8MM_IOMUXC_SAI5_MCLK 736 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
881 >; 737 >;
882 }; 738 };
883 739
884 pinctrl_pcie0: pciegrp { <<
885 fsl,pins = < <<
886 MX8MM_IOMUXC_SAI1_RXD3 <<
887 >; <<
888 }; <<
889 <<
890 pinctrl_pmic: pmicgrp { 740 pinctrl_pmic: pmicgrp {
891 fsl,pins = < 741 fsl,pins = <
892 MX8MM_IOMUXC_NAND_DATA 742 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
893 >; 743 >;
894 }; 744 };
895 745
896 pinctrl_pps: ppsgrp { 746 pinctrl_pps: ppsgrp {
897 fsl,pins = < 747 fsl,pins = <
898 MX8MM_IOMUXC_SAI5_RXD3 748 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
899 >; 749 >;
900 }; 750 };
901 751
902 pinctrl_reg_wl: regwlgrp { 752 pinctrl_reg_wl: regwlgrp {
903 fsl,pins = < 753 fsl,pins = <
904 MX8MM_IOMUXC_SD2_RESET 754 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
905 >; 755 >;
906 }; 756 };
907 757
908 pinctrl_reg_usb1: regusb1grp { 758 pinctrl_reg_usb1: regusb1grp {
909 fsl,pins = < 759 fsl,pins = <
910 MX8MM_IOMUXC_SD1_DATA5 760 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
911 >; 761 >;
912 }; 762 };
913 763
914 pinctrl_sai3: sai3grp { 764 pinctrl_sai3: sai3grp {
915 fsl,pins = < 765 fsl,pins = <
916 MX8MM_IOMUXC_SAI3_MCLK 766 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
917 MX8MM_IOMUXC_SAI3_RXD_ 767 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
918 MX8MM_IOMUXC_SAI3_TXC_ 768 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
919 MX8MM_IOMUXC_SAI3_TXD_ 769 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
920 MX8MM_IOMUXC_SAI3_TXFS 770 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
921 >; 771 >;
922 }; 772 };
923 773
924 pinctrl_spi1: spi1grp { 774 pinctrl_spi1: spi1grp {
925 fsl,pins = < 775 fsl,pins = <
926 MX8MM_IOMUXC_ECSPI1_SC 776 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
927 MX8MM_IOMUXC_ECSPI1_MO 777 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
928 MX8MM_IOMUXC_ECSPI1_MI 778 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
929 MX8MM_IOMUXC_ECSPI1_SS 779 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
930 MX8MM_IOMUXC_SD1_DATA1 780 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
931 >; 781 >;
932 }; 782 };
933 783
934 pinctrl_spi2: spi2grp { 784 pinctrl_spi2: spi2grp {
935 fsl,pins = < 785 fsl,pins = <
936 MX8MM_IOMUXC_ECSPI2_SC 786 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
937 MX8MM_IOMUXC_ECSPI2_MO 787 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
938 MX8MM_IOMUXC_ECSPI2_MI 788 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
939 MX8MM_IOMUXC_ECSPI2_SS 789 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
940 >; 790 >;
941 }; 791 };
942 792
943 pinctrl_uart1: uart1grp { 793 pinctrl_uart1: uart1grp {
944 fsl,pins = < 794 fsl,pins = <
945 MX8MM_IOMUXC_UART1_RXD 795 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
946 MX8MM_IOMUXC_UART1_TXD 796 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
947 MX8MM_IOMUXC_SAI1_TXFS 797 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
948 MX8MM_IOMUXC_SAI2_TXFS 798 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
949 >; 799 >;
950 }; 800 };
951 801
952 pinctrl_uart1_gpio: uart1gpiogrp { 802 pinctrl_uart1_gpio: uart1gpiogrp {
953 fsl,pins = < 803 fsl,pins = <
954 MX8MM_IOMUXC_SAI2_TXD0 804 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
955 MX8MM_IOMUXC_SAI2_TXC_ 805 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
956 MX8MM_IOMUXC_SAI2_RXD0 806 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
957 >; 807 >;
958 }; 808 };
959 809
960 pinctrl_uart2: uart2grp { 810 pinctrl_uart2: uart2grp {
961 fsl,pins = < 811 fsl,pins = <
962 MX8MM_IOMUXC_UART2_RXD 812 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
963 MX8MM_IOMUXC_UART2_TXD 813 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
964 >; 814 >;
965 }; 815 };
966 816
967 pinctrl_uart3_gpio: uart3_gpiogrp { 817 pinctrl_uart3_gpio: uart3_gpiogrp {
968 fsl,pins = < 818 fsl,pins = <
969 MX8MM_IOMUXC_SD2_CD_B_ 819 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
970 >; 820 >;
971 }; 821 };
972 822
973 pinctrl_uart3: uart3grp { 823 pinctrl_uart3: uart3grp {
974 fsl,pins = < 824 fsl,pins = <
975 MX8MM_IOMUXC_UART3_RXD 825 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
976 MX8MM_IOMUXC_UART3_TXD 826 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
977 MX8MM_IOMUXC_SD1_CLK_G 827 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
978 MX8MM_IOMUXC_SD1_CMD_G 828 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
979 >; 829 >;
980 }; 830 };
981 831
982 pinctrl_uart4: uart4grp { 832 pinctrl_uart4: uart4grp {
983 fsl,pins = < 833 fsl,pins = <
984 MX8MM_IOMUXC_UART4_RXD 834 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
985 MX8MM_IOMUXC_UART4_TXD 835 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
986 MX8MM_IOMUXC_SAI1_RXC_ 836 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
987 MX8MM_IOMUXC_SAI1_RXD0 837 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
988 MX8MM_IOMUXC_SAI1_RXD1 838 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
989 MX8MM_IOMUXC_SAI1_RXD2 839 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
990 MX8MM_IOMUXC_SAI1_RXD4 840 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
991 MX8MM_IOMUXC_SAI1_RXD5 841 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
992 MX8MM_IOMUXC_SAI1_RXFS 842 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
993 MX8MM_IOMUXC_GPIO1_IO0 843 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
994 >; 844 >;
995 }; 845 };
996 846
997 pinctrl_usdhc2: usdhc2grp { 847 pinctrl_usdhc2: usdhc2grp {
998 fsl,pins = < 848 fsl,pins = <
999 MX8MM_IOMUXC_SD2_CLK_U 849 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1000 MX8MM_IOMUXC_SD2_CMD_ 850 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1001 MX8MM_IOMUXC_SD2_DATA 851 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1002 MX8MM_IOMUXC_SD2_DATA 852 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1003 MX8MM_IOMUXC_SD2_DATA 853 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1004 MX8MM_IOMUXC_SD2_DATA 854 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1005 >; <<
1006 }; <<
1007 <<
1008 pinctrl_usdhc2_100mhz: usdhc2-100mhzg <<
1009 fsl,pins = < <<
1010 MX8MM_IOMUXC_SD2_CLK_ <<
1011 MX8MM_IOMUXC_SD2_CMD_ <<
1012 MX8MM_IOMUXC_SD2_DATA <<
1013 MX8MM_IOMUXC_SD2_DATA <<
1014 MX8MM_IOMUXC_SD2_DATA <<
1015 MX8MM_IOMUXC_SD2_DATA <<
1016 >; <<
1017 }; <<
1018 <<
1019 pinctrl_usdhc2_200mhz: usdhc2-200mhzg <<
1020 fsl,pins = < <<
1021 MX8MM_IOMUXC_SD2_CLK_ <<
1022 MX8MM_IOMUXC_SD2_CMD_ <<
1023 MX8MM_IOMUXC_SD2_DATA <<
1024 MX8MM_IOMUXC_SD2_DATA <<
1025 MX8MM_IOMUXC_SD2_DATA <<
1026 MX8MM_IOMUXC_SD2_DATA <<
1027 >; 855 >;
1028 }; 856 };
1029 857
1030 pinctrl_usdhc3: usdhc3grp { 858 pinctrl_usdhc3: usdhc3grp {
1031 fsl,pins = < 859 fsl,pins = <
1032 MX8MM_IOMUXC_NAND_WE_ 860 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1033 MX8MM_IOMUXC_NAND_WP_ 861 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1034 MX8MM_IOMUXC_NAND_DAT 862 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1035 MX8MM_IOMUXC_NAND_DAT 863 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1036 MX8MM_IOMUXC_NAND_DAT 864 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1037 MX8MM_IOMUXC_NAND_DAT 865 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1038 MX8MM_IOMUXC_NAND_RE_ 866 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1039 MX8MM_IOMUXC_NAND_CE2 867 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1040 MX8MM_IOMUXC_NAND_CE3 868 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1041 MX8MM_IOMUXC_NAND_CLE 869 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1042 MX8MM_IOMUXC_NAND_CE1 870 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1043 >; 871 >;
1044 }; 872 };
1045 873
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 874 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1047 fsl,pins = < 875 fsl,pins = <
1048 MX8MM_IOMUXC_NAND_WE_ 876 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1049 MX8MM_IOMUXC_NAND_WP_ 877 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1050 MX8MM_IOMUXC_NAND_DAT 878 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1051 MX8MM_IOMUXC_NAND_DAT 879 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1052 MX8MM_IOMUXC_NAND_DAT 880 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1053 MX8MM_IOMUXC_NAND_DAT 881 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1054 MX8MM_IOMUXC_NAND_RE_ 882 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1055 MX8MM_IOMUXC_NAND_CE2 883 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1056 MX8MM_IOMUXC_NAND_CE3 884 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1057 MX8MM_IOMUXC_NAND_CLE 885 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1058 MX8MM_IOMUXC_NAND_CE1 886 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1059 >; 887 >;
1060 }; 888 };
1061 889
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 890 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1063 fsl,pins = < 891 fsl,pins = <
1064 MX8MM_IOMUXC_NAND_WE_ 892 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1065 MX8MM_IOMUXC_NAND_WP_ 893 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1066 MX8MM_IOMUXC_NAND_DAT 894 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1067 MX8MM_IOMUXC_NAND_DAT 895 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1068 MX8MM_IOMUXC_NAND_DAT 896 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1069 MX8MM_IOMUXC_NAND_DAT 897 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1070 MX8MM_IOMUXC_NAND_RE_ 898 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1071 MX8MM_IOMUXC_NAND_CE2 899 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1072 MX8MM_IOMUXC_NAND_CE3 900 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1073 MX8MM_IOMUXC_NAND_CLE 901 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1074 MX8MM_IOMUXC_NAND_CE1 902 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1075 >; 903 >;
1076 }; 904 };
1077 905
1078 pinctrl_wdog: wdoggrp { 906 pinctrl_wdog: wdoggrp {
1079 fsl,pins = < 907 fsl,pins = <
1080 MX8MM_IOMUXC_GPIO1_IO 908 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1081 >; 909 >;
1082 }; 910 };
1083 }; 911 };
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