1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 13
14 #include "imx8mm.dtsi" 14 #include "imx8mm.dtsi"
15 15
16 / { 16 / {
17 model = "Gateworks Venice GW7902 i.MX8 17 model = "Gateworks Venice GW7902 i.MX8MM board";
18 compatible = "gw,imx8mm-gw7902", "fsl, 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19 19
20 aliases { 20 aliases {
21 ethernet1 = ð1; 21 ethernet1 = ð1;
22 usb0 = &usbotg1; 22 usb0 = &usbotg1;
23 usb1 = &usbotg2; 23 usb1 = &usbotg2;
24 }; 24 };
25 25
26 chosen { 26 chosen {
27 stdout-path = &uart2; 27 stdout-path = &uart2;
28 }; 28 };
29 29
30 memory@40000000 { 30 memory@40000000 {
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000 0 0x8000 32 reg = <0x0 0x40000000 0 0x80000000>;
33 }; 33 };
34 34
35 can20m: can20m { 35 can20m: can20m {
36 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
37 #clock-cells = <0>; 37 #clock-cells = <0>;
38 clock-frequency = <20000000>; 38 clock-frequency = <20000000>;
39 clock-output-names = "can20m"; 39 clock-output-names = "can20m";
40 }; 40 };
41 41
42 gpio-keys { 42 gpio-keys {
43 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
44 44
45 key-user-pb { 45 key-user-pb {
46 label = "user_pb"; 46 label = "user_pb";
47 gpios = <&gpio 2 GPIO_ 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48 linux,code = <BTN_0>; 48 linux,code = <BTN_0>;
49 }; 49 };
50 50
51 key-user-pb1x { 51 key-user-pb1x {
52 label = "user_pb1x"; 52 label = "user_pb1x";
53 linux,code = <BTN_1>; 53 linux,code = <BTN_1>;
54 interrupt-parent = <&g 54 interrupt-parent = <&gsc>;
55 interrupts = <0>; 55 interrupts = <0>;
56 }; 56 };
57 57
58 key-erased { 58 key-erased {
59 label = "key_erased"; 59 label = "key_erased";
60 linux,code = <BTN_2>; 60 linux,code = <BTN_2>;
61 interrupt-parent = <&g 61 interrupt-parent = <&gsc>;
62 interrupts = <1>; 62 interrupts = <1>;
63 }; 63 };
64 64
65 key-eeprom-wp { 65 key-eeprom-wp {
66 label = "eeprom_wp"; 66 label = "eeprom_wp";
67 linux,code = <BTN_3>; 67 linux,code = <BTN_3>;
68 interrupt-parent = <&g 68 interrupt-parent = <&gsc>;
69 interrupts = <2>; 69 interrupts = <2>;
70 }; 70 };
71 71
72 key-tamper { 72 key-tamper {
73 label = "tamper"; 73 label = "tamper";
74 linux,code = <BTN_4>; 74 linux,code = <BTN_4>;
75 interrupt-parent = <&g 75 interrupt-parent = <&gsc>;
76 interrupts = <5>; 76 interrupts = <5>;
77 }; 77 };
78 78
79 switch-hold { 79 switch-hold {
80 label = "switch_hold"; 80 label = "switch_hold";
81 linux,code = <BTN_5>; 81 linux,code = <BTN_5>;
82 interrupt-parent = <&g 82 interrupt-parent = <&gsc>;
83 interrupts = <7>; 83 interrupts = <7>;
84 }; 84 };
85 }; 85 };
86 86
87 led-controller { 87 led-controller {
88 compatible = "gpio-leds"; 88 compatible = "gpio-leds";
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_gpio_led 90 pinctrl-0 = <&pinctrl_gpio_leds>;
91 91
92 led-0 { 92 led-0 {
93 function = LED_FUNCTIO 93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_ 94 color = <LED_COLOR_ID_GREEN>;
95 label = "panel1"; 95 label = "panel1";
96 gpios = <&gpio3 21 GPI 96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97 default-state = "off"; 97 default-state = "off";
98 }; 98 };
99 99
100 led-1 { 100 led-1 {
101 function = LED_FUNCTIO 101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_ 102 color = <LED_COLOR_ID_GREEN>;
103 label = "panel2"; 103 label = "panel2";
104 gpios = <&gpio3 23 GPI 104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105 default-state = "off"; 105 default-state = "off";
106 }; 106 };
107 107
108 led-2 { 108 led-2 {
109 function = LED_FUNCTIO 109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_ 110 color = <LED_COLOR_ID_GREEN>;
111 label = "panel3"; 111 label = "panel3";
112 gpios = <&gpio3 22 GPI 112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113 default-state = "off"; 113 default-state = "off";
114 }; 114 };
115 115
116 led-3 { 116 led-3 {
117 function = LED_FUNCTIO 117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_ 118 color = <LED_COLOR_ID_GREEN>;
119 label = "panel4"; 119 label = "panel4";
120 gpios = <&gpio3 20 GPI 120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121 default-state = "off"; 121 default-state = "off";
122 }; 122 };
123 123
124 led-4 { 124 led-4 {
125 function = LED_FUNCTIO 125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_ 126 color = <LED_COLOR_ID_GREEN>;
127 label = "panel5"; 127 label = "panel5";
128 gpios = <&gpio3 25 GPI 128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129 default-state = "off"; 129 default-state = "off";
130 }; 130 };
131 }; 131 };
132 132
133 pcie0_refclk: pcie0-refclk { 133 pcie0_refclk: pcie0-refclk {
134 compatible = "fixed-clock"; 134 compatible = "fixed-clock";
135 #clock-cells = <0>; 135 #clock-cells = <0>;
136 clock-frequency = <100000000>; 136 clock-frequency = <100000000>;
137 }; 137 };
138 138
139 pps { 139 pps {
140 compatible = "pps-gpio"; 140 compatible = "pps-gpio";
141 pinctrl-names = "default"; 141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pps>; 142 pinctrl-0 = <&pinctrl_pps>;
143 gpios = <&gpio3 24 GPIO_ACTIVE 143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144 status = "okay"; 144 status = "okay";
145 }; 145 };
146 146
147 reg_3p3v: regulator-3p3v { 147 reg_3p3v: regulator-3p3v {
148 compatible = "regulator-fixed" 148 compatible = "regulator-fixed";
149 regulator-name = "3P3V"; 149 regulator-name = "3P3V";
150 regulator-min-microvolt = <330 150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <330 151 regulator-max-microvolt = <3300000>;
152 regulator-always-on; 152 regulator-always-on;
153 }; 153 };
154 154
155 reg_usb1_vbus: regulator-usb1 { 155 reg_usb1_vbus: regulator-usb1 {
156 compatible = "regulator-fixed" 156 compatible = "regulator-fixed";
157 pinctrl-names = "default"; 157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_usb1 158 pinctrl-0 = <&pinctrl_reg_usb1>;
159 regulator-name = "usb_usb1_vbu 159 regulator-name = "usb_usb1_vbus";
160 gpio = <&gpio2 7 GPIO_ACTIVE_H 160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161 enable-active-high; 161 enable-active-high;
162 regulator-min-microvolt = <500 162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <500 163 regulator-max-microvolt = <5000000>;
164 }; 164 };
165 165
166 reg_wifi: regulator-wifi { 166 reg_wifi: regulator-wifi {
167 compatible = "regulator-fixed" 167 compatible = "regulator-fixed";
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_reg_wl>; 169 pinctrl-0 = <&pinctrl_reg_wl>;
170 regulator-name = "wifi"; 170 regulator-name = "wifi";
171 gpio = <&gpio2 19 GPIO_ACTIVE_ 171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172 enable-active-high; 172 enable-active-high;
173 startup-delay-us = <100>; 173 startup-delay-us = <100>;
174 regulator-min-microvolt = <330 174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <330 175 regulator-max-microvolt = <3300000>;
176 }; 176 };
177 }; 177 };
178 178
179 &A53_0 { 179 &A53_0 {
180 cpu-supply = <&buck2>; 180 cpu-supply = <&buck2>;
181 }; 181 };
182 182
183 &A53_1 { 183 &A53_1 {
184 cpu-supply = <&buck2>; 184 cpu-supply = <&buck2>;
185 }; 185 };
186 186
187 &A53_2 { 187 &A53_2 {
188 cpu-supply = <&buck2>; 188 cpu-supply = <&buck2>;
189 }; 189 };
190 190
191 &A53_3 { 191 &A53_3 {
192 cpu-supply = <&buck2>; 192 cpu-supply = <&buck2>;
193 }; 193 };
194 194
195 &ddrc { 195 &ddrc {
196 operating-points-v2 = <&ddrc_opp_table 196 operating-points-v2 = <&ddrc_opp_table>;
197 197
198 ddrc_opp_table: opp-table { 198 ddrc_opp_table: opp-table {
199 compatible = "operating-points 199 compatible = "operating-points-v2";
200 200
201 opp-25000000 { !! 201 opp-25M {
202 opp-hz = /bits/ 64 <25 202 opp-hz = /bits/ 64 <25000000>;
203 }; 203 };
204 204
205 opp-100000000 { !! 205 opp-100M {
206 opp-hz = /bits/ 64 <10 206 opp-hz = /bits/ 64 <100000000>;
207 }; 207 };
208 208
209 opp-750000000 { !! 209 opp-750M {
210 opp-hz = /bits/ 64 <75 210 opp-hz = /bits/ 64 <750000000>;
211 }; 211 };
212 }; 212 };
213 }; 213 };
214 214
215 &ecspi1 { 215 &ecspi1 {
216 pinctrl-names = "default"; 216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spi1>; 217 pinctrl-0 = <&pinctrl_spi1>;
218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219 status = "okay"; 219 status = "okay";
220 220
221 can@0 { 221 can@0 {
222 compatible = "microchip,mcp251 222 compatible = "microchip,mcp2515";
223 reg = <0>; 223 reg = <0>;
224 clocks = <&can20m>; 224 clocks = <&can20m>;
225 interrupt-parent = <&gpio2>; 225 interrupt-parent = <&gpio2>;
226 interrupts = <3 IRQ_TYPE_LEVEL 226 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227 spi-max-frequency = <10000000> 227 spi-max-frequency = <10000000>;
228 }; 228 };
229 }; 229 };
230 230
231 /* off-board header */ 231 /* off-board header */
232 &ecspi2 { 232 &ecspi2 {
233 pinctrl-names = "default"; 233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_spi2>; 234 pinctrl-0 = <&pinctrl_spi2>;
235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236 status = "okay"; 236 status = "okay";
237 }; 237 };
238 238
239 &fec1 { 239 &fec1 {
240 pinctrl-names = "default"; 240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_fec1>; 241 pinctrl-0 = <&pinctrl_fec1>;
242 phy-mode = "rgmii-id"; 242 phy-mode = "rgmii-id";
243 phy-handle = <ðphy0>; 243 phy-handle = <ðphy0>;
244 local-mac-address = [00 00 00 00 00 00 244 local-mac-address = [00 00 00 00 00 00];
245 status = "okay"; 245 status = "okay";
246 246
247 mdio { 247 mdio {
248 #address-cells = <1>; 248 #address-cells = <1>;
249 #size-cells = <0>; 249 #size-cells = <0>;
250 250
251 ethphy0: ethernet-phy@0 { 251 ethphy0: ethernet-phy@0 {
252 compatible = "ethernet 252 compatible = "ethernet-phy-ieee802.3-c22";
253 reg = <0>; 253 reg = <0>;
254 ti,rx-internal-delay = 254 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255 ti,tx-internal-delay = 255 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256 tx-fifo-depth = <DP838 256 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257 rx-fifo-depth = <DP838 257 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 }; 258 };
259 }; 259 };
260 }; 260 };
261 261
262 &gpio1 { 262 &gpio1 {
263 gpio-line-names = "", "", "", "", "", 263 gpio-line-names = "", "", "", "", "", "", "", "",
264 "m2_pwr_en", "", "", "", "", " !! 264 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
265 "", "", "", "", "", "", "", "" 265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "" 266 "", "", "", "", "", "", "", "";
267 }; 267 };
268 268
269 &gpio2 { 269 &gpio2 {
270 gpio-line-names = "", "", "", "", "", 270 gpio-line-names = "", "", "", "", "", "", "", "",
271 "uart2_en#", "", "", "", "", " 271 "uart2_en#", "", "", "", "", "", "", "",
272 "", "", "", "", "", "", "", "" 272 "", "", "", "", "", "", "", "",
273 "", "", "", "", "", "", "", "" 273 "", "", "", "", "", "", "", "";
274 }; 274 };
275 275
276 &gpio3 { 276 &gpio3 {
277 gpio-line-names = "", "m2_gdis#", "", 277 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278 "", "", "", "", "", "", "", "" 278 "", "", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "" 279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 280 "", "", "", "", "", "", "", "";
281 }; 281 };
282 282
283 &gpio4 { 283 &gpio4 {
284 gpio-line-names = "", "", "", "", "", 284 gpio-line-names = "", "", "", "", "", "", "", "",
285 "", "", "", "amp_gpio3", "amp_ 285 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286 "lte_pwr#", "lte_rst", "lte_in !! 286 "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
287 "amp_gpio4", "app_gpio1", "vdd <<
288 "", "uart1_term", "uart1_half" 287 "", "uart1_term", "uart1_half", "app_gpio2",
289 "mipi_gpio1", "", "", ""; 288 "mipi_gpio1", "", "", "";
290 }; 289 };
291 290
292 &gpio5 { 291 &gpio5 {
293 gpio-line-names = "", "", "", "mipi_gp 292 gpio-line-names = "", "", "", "mipi_gpio4",
294 "mipi_gpio3", "mipi_gpio2", "" 293 "mipi_gpio3", "mipi_gpio2", "", "",
295 "", "", "", "", "", "", "", "" 294 "", "", "", "", "", "", "", "",
296 "", "", "", "", "", "", "", "" 295 "", "", "", "", "", "", "", "",
297 "", "", "", "", "", "", "", "" 296 "", "", "", "", "", "", "", "";
298 }; 297 };
299 298
300 &i2c1 { 299 &i2c1 {
301 clock-frequency = <100000>; 300 clock-frequency = <100000>;
302 pinctrl-names = "default", "gpio"; !! 301 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c1>; 302 pinctrl-0 = <&pinctrl_i2c1>;
304 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
307 status = "okay"; 303 status = "okay";
308 304
309 gsc: gsc@20 { 305 gsc: gsc@20 {
310 compatible = "gw,gsc"; 306 compatible = "gw,gsc";
311 reg = <0x20>; 307 reg = <0x20>;
312 pinctrl-0 = <&pinctrl_gsc>; 308 pinctrl-0 = <&pinctrl_gsc>;
313 interrupt-parent = <&gpio2>; 309 interrupt-parent = <&gpio2>;
314 interrupts = <6 IRQ_TYPE_EDGE_ 310 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315 interrupt-controller; 311 interrupt-controller;
316 #interrupt-cells = <1>; 312 #interrupt-cells = <1>;
317 #address-cells = <1>; <<
318 #size-cells = <0>; <<
319 313
320 adc { 314 adc {
321 compatible = "gw,gsc-a 315 compatible = "gw,gsc-adc";
322 #address-cells = <1>; 316 #address-cells = <1>;
323 #size-cells = <0>; 317 #size-cells = <0>;
324 318
325 channel@6 { 319 channel@6 {
326 gw,mode = <0>; 320 gw,mode = <0>;
327 reg = <0x06>; 321 reg = <0x06>;
328 label = "temp" 322 label = "temp";
329 }; 323 };
330 324
331 channel@8 { 325 channel@8 {
332 gw,mode = <3>; !! 326 gw,mode = <1>;
333 reg = <0x08>; 327 reg = <0x08>;
334 label = "vdd_b 328 label = "vdd_bat";
335 }; 329 };
336 330
337 channel@82 { 331 channel@82 {
338 gw,mode = <2>; 332 gw,mode = <2>;
339 reg = <0x82>; 333 reg = <0x82>;
340 label = "vin"; 334 label = "vin";
341 gw,voltage-div 335 gw,voltage-divider-ohms = <22100 1000>;
342 gw,voltage-off 336 gw,voltage-offset-microvolt = <700000>;
343 }; 337 };
344 338
345 channel@84 { 339 channel@84 {
346 gw,mode = <2>; 340 gw,mode = <2>;
347 reg = <0x84>; 341 reg = <0x84>;
348 label = "vin_4 342 label = "vin_4p0";
349 gw,voltage-div 343 gw,voltage-divider-ohms = <10000 10000>;
350 }; 344 };
351 345
352 channel@86 { 346 channel@86 {
353 gw,mode = <2>; 347 gw,mode = <2>;
354 reg = <0x86>; 348 reg = <0x86>;
355 label = "vdd_3 349 label = "vdd_3p3";
356 gw,voltage-div 350 gw,voltage-divider-ohms = <10000 10000>;
357 }; 351 };
358 352
359 channel@88 { 353 channel@88 {
360 gw,mode = <2>; 354 gw,mode = <2>;
361 reg = <0x88>; 355 reg = <0x88>;
362 label = "vdd_0 356 label = "vdd_0p9";
363 }; 357 };
364 358
365 channel@8c { 359 channel@8c {
366 gw,mode = <2>; 360 gw,mode = <2>;
367 reg = <0x8c>; 361 reg = <0x8c>;
368 label = "vdd_s 362 label = "vdd_soc";
369 }; 363 };
370 364
371 channel@8e { 365 channel@8e {
372 gw,mode = <2>; 366 gw,mode = <2>;
373 reg = <0x8e>; 367 reg = <0x8e>;
374 label = "vdd_a 368 label = "vdd_arm";
375 }; 369 };
376 370
377 channel@90 { 371 channel@90 {
378 gw,mode = <2>; 372 gw,mode = <2>;
379 reg = <0x90>; 373 reg = <0x90>;
380 label = "vdd_1 374 label = "vdd_1p8";
381 }; 375 };
382 376
383 channel@92 { 377 channel@92 {
384 gw,mode = <2>; 378 gw,mode = <2>;
385 reg = <0x92>; 379 reg = <0x92>;
386 label = "vdd_d 380 label = "vdd_dram";
387 }; 381 };
388 382
389 channel@98 { 383 channel@98 {
390 gw,mode = <2>; 384 gw,mode = <2>;
391 reg = <0x98>; 385 reg = <0x98>;
392 label = "vdd_1 386 label = "vdd_1p0";
393 }; 387 };
394 388
395 channel@9a { 389 channel@9a {
396 gw,mode = <2>; 390 gw,mode = <2>;
397 reg = <0x9a>; 391 reg = <0x9a>;
398 label = "vdd_2 392 label = "vdd_2p5";
399 gw,voltage-div 393 gw,voltage-divider-ohms = <10000 10000>;
400 }; 394 };
401 395
402 channel@9c { 396 channel@9c {
403 gw,mode = <2>; 397 gw,mode = <2>;
404 reg = <0x9c>; 398 reg = <0x9c>;
405 label = "vdd_5 399 label = "vdd_5p0";
406 gw,voltage-div 400 gw,voltage-divider-ohms = <10000 10000>;
407 }; 401 };
408 402
409 channel@a2 { 403 channel@a2 {
410 gw,mode = <2>; 404 gw,mode = <2>;
411 reg = <0xa2>; 405 reg = <0xa2>;
412 label = "vdd_g 406 label = "vdd_gsc";
413 gw,voltage-div 407 gw,voltage-divider-ohms = <10000 10000>;
414 }; 408 };
415 }; 409 };
416 }; 410 };
417 411
418 gpio: gpio@23 { 412 gpio: gpio@23 {
419 compatible = "nxp,pca9555"; 413 compatible = "nxp,pca9555";
420 reg = <0x23>; 414 reg = <0x23>;
421 gpio-controller; 415 gpio-controller;
422 #gpio-cells = <2>; 416 #gpio-cells = <2>;
423 interrupt-parent = <&gsc>; 417 interrupt-parent = <&gsc>;
424 interrupts = <4>; 418 interrupts = <4>;
425 }; 419 };
426 420
427 pmic@4b { 421 pmic@4b {
428 compatible = "rohm,bd71847"; 422 compatible = "rohm,bd71847";
429 reg = <0x4b>; 423 reg = <0x4b>;
430 pinctrl-names = "default"; 424 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_pmic>; 425 pinctrl-0 = <&pinctrl_pmic>;
432 interrupt-parent = <&gpio3>; 426 interrupt-parent = <&gpio3>;
433 interrupts = <8 IRQ_TYPE_LEVEL 427 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
434 rohm,reset-snvs-powered; 428 rohm,reset-snvs-powered;
435 #clock-cells = <0>; 429 #clock-cells = <0>;
436 clocks = <&osc_32k>; !! 430 clocks = <&osc_32k 0>;
437 clock-output-names = "clk-32k- 431 clock-output-names = "clk-32k-out";
438 432
439 regulators { 433 regulators {
440 /* vdd_soc: 0.805-0.90 434 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
441 BUCK1 { 435 BUCK1 {
442 regulator-name 436 regulator-name = "buck1";
443 regulator-min- 437 regulator-min-microvolt = <700000>;
444 regulator-max- 438 regulator-max-microvolt = <1300000>;
445 regulator-boot 439 regulator-boot-on;
446 regulator-alwa 440 regulator-always-on;
447 regulator-ramp 441 regulator-ramp-delay = <1250>;
448 }; 442 };
449 443
450 /* vdd_arm: 0.805-1.0V 444 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
451 buck2: BUCK2 { 445 buck2: BUCK2 {
452 regulator-name 446 regulator-name = "buck2";
453 regulator-min- 447 regulator-min-microvolt = <700000>;
454 regulator-max- 448 regulator-max-microvolt = <1300000>;
455 regulator-boot 449 regulator-boot-on;
456 regulator-alwa 450 regulator-always-on;
457 regulator-ramp 451 regulator-ramp-delay = <1250>;
458 rohm,dvs-run-v 452 rohm,dvs-run-voltage = <1000000>;
459 rohm,dvs-idle- 453 rohm,dvs-idle-voltage = <900000>;
460 }; 454 };
461 455
462 /* vdd_0p9: 0.805-1.0V 456 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
463 BUCK3 { 457 BUCK3 {
464 regulator-name 458 regulator-name = "buck3";
465 regulator-min- 459 regulator-min-microvolt = <700000>;
466 regulator-max- 460 regulator-max-microvolt = <1350000>;
467 regulator-boot 461 regulator-boot-on;
468 regulator-alwa 462 regulator-always-on;
469 }; 463 };
470 464
471 /* vdd_3p3 */ 465 /* vdd_3p3 */
472 BUCK4 { 466 BUCK4 {
473 regulator-name 467 regulator-name = "buck4";
474 regulator-min- 468 regulator-min-microvolt = <3000000>;
475 regulator-max- 469 regulator-max-microvolt = <3300000>;
476 regulator-boot 470 regulator-boot-on;
477 regulator-alwa 471 regulator-always-on;
478 }; 472 };
479 473
480 /* vdd_1p8 */ 474 /* vdd_1p8 */
481 BUCK5 { 475 BUCK5 {
482 regulator-name 476 regulator-name = "buck5";
483 regulator-min- 477 regulator-min-microvolt = <1605000>;
484 regulator-max- 478 regulator-max-microvolt = <1995000>;
485 regulator-boot 479 regulator-boot-on;
486 regulator-alwa 480 regulator-always-on;
487 }; 481 };
488 482
489 /* vdd_dram */ 483 /* vdd_dram */
490 BUCK6 { 484 BUCK6 {
491 regulator-name 485 regulator-name = "buck6";
492 regulator-min- 486 regulator-min-microvolt = <800000>;
493 regulator-max- 487 regulator-max-microvolt = <1400000>;
494 regulator-boot 488 regulator-boot-on;
495 regulator-alwa 489 regulator-always-on;
496 }; 490 };
497 491
498 /* nvcc_snvs_1p8 */ 492 /* nvcc_snvs_1p8 */
499 LDO1 { 493 LDO1 {
500 regulator-name 494 regulator-name = "ldo1";
501 regulator-min- 495 regulator-min-microvolt = <1600000>;
502 regulator-max- 496 regulator-max-microvolt = <1900000>;
503 regulator-boot 497 regulator-boot-on;
504 regulator-alwa 498 regulator-always-on;
505 }; 499 };
506 500
507 /* vdd_snvs_0p8 */ 501 /* vdd_snvs_0p8 */
508 LDO2 { 502 LDO2 {
509 regulator-name 503 regulator-name = "ldo2";
510 regulator-min- 504 regulator-min-microvolt = <800000>;
511 regulator-max- 505 regulator-max-microvolt = <900000>;
512 regulator-boot 506 regulator-boot-on;
513 regulator-alwa 507 regulator-always-on;
514 }; 508 };
515 509
516 /* vdda_1p8 */ 510 /* vdda_1p8 */
517 LDO3 { 511 LDO3 {
518 regulator-name 512 regulator-name = "ldo3";
519 regulator-min- 513 regulator-min-microvolt = <1800000>;
520 regulator-max- 514 regulator-max-microvolt = <3300000>;
521 regulator-boot 515 regulator-boot-on;
522 regulator-alwa 516 regulator-always-on;
523 }; 517 };
524 518
525 LDO4 { 519 LDO4 {
526 regulator-name 520 regulator-name = "ldo4";
527 regulator-min- 521 regulator-min-microvolt = <900000>;
528 regulator-max- 522 regulator-max-microvolt = <1800000>;
529 regulator-boot 523 regulator-boot-on;
530 regulator-alwa 524 regulator-always-on;
531 }; 525 };
532 526
533 LDO6 { 527 LDO6 {
534 regulator-name 528 regulator-name = "ldo6";
535 regulator-min- 529 regulator-min-microvolt = <900000>;
536 regulator-max- 530 regulator-max-microvolt = <1800000>;
537 regulator-boot 531 regulator-boot-on;
538 regulator-alwa 532 regulator-always-on;
539 }; 533 };
540 }; 534 };
541 }; 535 };
542 536
543 eeprom@50 { 537 eeprom@50 {
544 compatible = "atmel,24c02"; 538 compatible = "atmel,24c02";
545 reg = <0x50>; 539 reg = <0x50>;
546 pagesize = <16>; 540 pagesize = <16>;
547 }; 541 };
548 542
549 eeprom@51 { 543 eeprom@51 {
550 compatible = "atmel,24c02"; 544 compatible = "atmel,24c02";
551 reg = <0x51>; 545 reg = <0x51>;
552 pagesize = <16>; 546 pagesize = <16>;
553 }; 547 };
554 548
555 eeprom@52 { 549 eeprom@52 {
556 compatible = "atmel,24c02"; 550 compatible = "atmel,24c02";
557 reg = <0x52>; 551 reg = <0x52>;
558 pagesize = <16>; 552 pagesize = <16>;
559 }; 553 };
560 554
561 eeprom@53 { 555 eeprom@53 {
562 compatible = "atmel,24c02"; 556 compatible = "atmel,24c02";
563 reg = <0x53>; 557 reg = <0x53>;
564 pagesize = <16>; 558 pagesize = <16>;
565 }; 559 };
566 560
567 rtc@68 { 561 rtc@68 {
568 compatible = "dallas,ds1672"; 562 compatible = "dallas,ds1672";
569 reg = <0x68>; 563 reg = <0x68>;
570 }; 564 };
571 }; 565 };
572 566
573 &i2c2 { 567 &i2c2 {
574 clock-frequency = <400000>; 568 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio"; !! 569 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_i2c2>; 570 pinctrl-0 = <&pinctrl_i2c2>;
577 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
580 status = "okay"; 571 status = "okay";
581 572
582 accelerometer@19 { 573 accelerometer@19 {
583 compatible = "st,lis2de12"; 574 compatible = "st,lis2de12";
584 pinctrl-names = "default"; 575 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_accel>; 576 pinctrl-0 = <&pinctrl_accel>;
586 reg = <0x19>; 577 reg = <0x19>;
587 st,drdy-int-pin = <1>; 578 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>; 579 interrupt-parent = <&gpio1>;
589 interrupts = <12 IRQ_TYPE_LEVE 580 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 581 interrupt-names = "INT1";
590 }; 582 };
591 }; 583 };
592 584
593 /* off-board header */ 585 /* off-board header */
594 &i2c3 { 586 &i2c3 {
595 clock-frequency = <400000>; 587 clock-frequency = <400000>;
596 pinctrl-names = "default", "gpio"; !! 588 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_i2c3>; 589 pinctrl-0 = <&pinctrl_i2c3>;
598 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
601 status = "okay"; 590 status = "okay";
602 }; 591 };
603 592
604 /* off-board header */ 593 /* off-board header */
605 &i2c4 { 594 &i2c4 {
606 clock-frequency = <400000>; 595 clock-frequency = <400000>;
607 pinctrl-names = "default", "gpio"; !! 596 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_i2c4>; 597 pinctrl-0 = <&pinctrl_i2c4>;
609 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
612 status = "okay"; 598 status = "okay";
613 }; 599 };
614 600
615 &pcie_phy { 601 &pcie_phy {
616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 602 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
617 fsl,clkreq-unsupported; 603 fsl,clkreq-unsupported;
618 clocks = <&pcie0_refclk>; 604 clocks = <&pcie0_refclk>;
619 clock-names = "ref"; 605 clock-names = "ref";
620 status = "okay"; 606 status = "okay";
621 }; 607 };
622 608
623 &pcie0 { 609 &pcie0 {
624 pinctrl-names = "default"; 610 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pcie0>; 611 pinctrl-0 = <&pinctrl_pcie0>;
626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW 612 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, !! 613 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
628 <&clk IMX8MM_CLK_PCIE1_AUX>; !! 614 <&pcie0_refclk>;
>> 615 clock-names = "pcie", "pcie_aux", "pcie_bus";
629 assigned-clocks = <&clk IMX8MM_CLK_PCI 616 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
630 <&clk IMX8MM_CLK_PCI 617 <&clk IMX8MM_CLK_PCIE1_CTRL>;
631 assigned-clock-rates = <10000000>, <25 618 assigned-clock-rates = <10000000>, <250000000>;
632 assigned-clock-parents = <&clk IMX8MM_ 619 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
633 <&clk IMX8MM_ 620 <&clk IMX8MM_SYS_PLL2_250M>;
634 status = "okay"; 621 status = "okay";
635 622
636 pcie@0,0 { 623 pcie@0,0 {
637 reg = <0x0000 0 0 0 0>; 624 reg = <0x0000 0 0 0 0>;
638 device_type = "pci"; !! 625 #address-cells = <1>;
639 #address-cells = <3>; !! 626 #size-cells = <0>;
640 #size-cells = <2>; <<
641 ranges; <<
642 627
643 eth1: ethernet@0,0 { !! 628 eth1: pcie@1,0 {
644 reg = <0x0000 0 0 0 0> 629 reg = <0x0000 0 0 0 0>;
645 #address-cells = <3>; !! 630 #address-cells = <1>;
646 #size-cells = <2>; !! 631 #size-cells = <0>;
647 ranges; <<
648 632
649 local-mac-address = [0 633 local-mac-address = [00 00 00 00 00 00];
650 }; 634 };
651 }; 635 };
652 }; 636 };
653 637
654 /* off-board header */ 638 /* off-board header */
655 &sai3 { 639 &sai3 {
656 pinctrl-names = "default"; 640 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_sai3>; 641 pinctrl-0 = <&pinctrl_sai3>;
658 assigned-clocks = <&clk IMX8MM_CLK_SAI 642 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
659 assigned-clock-parents = <&clk IMX8MM_ 643 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
660 assigned-clock-rates = <24576000>; 644 assigned-clock-rates = <24576000>;
661 status = "okay"; 645 status = "okay";
662 }; 646 };
663 647
664 /* RS232/RS485/RS422 selectable */ 648 /* RS232/RS485/RS422 selectable */
665 &uart1 { 649 &uart1 {
666 pinctrl-names = "default"; 650 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 651 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
668 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW 652 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
669 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW 653 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
670 status = "okay"; 654 status = "okay";
671 }; 655 };
672 656
673 /* RS232 console */ 657 /* RS232 console */
674 &uart2 { 658 &uart2 {
675 pinctrl-names = "default"; 659 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_uart2>; 660 pinctrl-0 = <&pinctrl_uart2>;
677 status = "okay"; 661 status = "okay";
678 }; 662 };
679 663
680 /* bluetooth HCI */ 664 /* bluetooth HCI */
681 &uart3 { 665 &uart3 {
682 pinctrl-names = "default"; 666 pinctrl-names = "default";
683 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 667 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
684 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 668 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
685 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 669 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
686 status = "okay"; 670 status = "okay";
687 671
688 bluetooth { 672 bluetooth {
689 compatible = "brcm,bcm4330-bt" 673 compatible = "brcm,bcm4330-bt";
690 shutdown-gpios = <&gpio2 12 GP 674 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
691 }; 675 };
692 }; 676 };
693 677
694 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 678 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
695 &uart4 { 679 &uart4 {
696 pinctrl-names = "default"; 680 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_uart4>; 681 pinctrl-0 = <&pinctrl_uart4>;
698 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW> 682 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
699 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW> 683 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
700 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW> 684 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
701 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW> 685 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
702 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW> 686 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
703 status = "okay"; 687 status = "okay";
704 }; 688 };
705 689
706 &usbotg1 { 690 &usbotg1 {
707 dr_mode = "host"; 691 dr_mode = "host";
708 vbus-supply = <®_usb1_vbus>; 692 vbus-supply = <®_usb1_vbus>;
709 disable-over-current; 693 disable-over-current;
710 status = "okay"; 694 status = "okay";
711 }; 695 };
712 696
713 &usbotg2 { 697 &usbotg2 {
714 dr_mode = "host"; 698 dr_mode = "host";
715 disable-over-current; 699 disable-over-current;
716 status = "okay"; 700 status = "okay";
717 }; 701 };
718 702
719 /* SDIO WiFi */ 703 /* SDIO WiFi */
720 &usdhc2 { 704 &usdhc2 {
721 pinctrl-names = "default", "state_100m !! 705 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_usdhc2>; 706 pinctrl-0 = <&pinctrl_usdhc2>;
723 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; <<
724 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; <<
725 bus-width = <4>; 707 bus-width = <4>;
726 non-removable; 708 non-removable;
727 vmmc-supply = <®_wifi>; 709 vmmc-supply = <®_wifi>;
728 #address-cells = <1>; <<
729 #size-cells = <0>; <<
730 status = "okay"; 710 status = "okay";
731 <<
732 wifi@0 { <<
733 compatible = "brcm,bcm43455-fm <<
734 reg = <0>; <<
735 }; <<
736 }; 711 };
737 712
738 /* eMMC */ 713 /* eMMC */
739 &usdhc3 { 714 &usdhc3 {
740 pinctrl-names = "default", "state_100m 715 pinctrl-names = "default", "state_100mhz", "state_200mhz";
741 pinctrl-0 = <&pinctrl_usdhc3>; 716 pinctrl-0 = <&pinctrl_usdhc3>;
742 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 717 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
743 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 718 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
744 bus-width = <8>; 719 bus-width = <8>;
745 non-removable; 720 non-removable;
746 status = "okay"; 721 status = "okay";
747 }; 722 };
748 723
749 &wdog1 { 724 &wdog1 {
750 pinctrl-names = "default"; 725 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_wdog>; 726 pinctrl-0 = <&pinctrl_wdog>;
752 fsl,ext-reset-output; 727 fsl,ext-reset-output;
753 status = "okay"; 728 status = "okay";
754 }; 729 };
755 730
756 &iomuxc { 731 &iomuxc {
757 pinctrl-names = "default"; 732 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_hog>; 733 pinctrl-0 = <&pinctrl_hog>;
759 734
760 pinctrl_hog: hoggrp { 735 pinctrl_hog: hoggrp {
761 fsl,pins = < 736 fsl,pins = <
762 MX8MM_IOMUXC_NAND_CE0_ 737 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
763 MX8MM_IOMUXC_GPIO1_IO0 <<
764 MX8MM_IOMUXC_GPIO1_IO1 738 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
765 MX8MM_IOMUXC_NAND_DATA 739 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
766 MX8MM_IOMUXC_GPIO1_IO1 740 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
767 MX8MM_IOMUXC_SAI1_TXD6 <<
768 MX8MM_IOMUXC_SAI1_TXD5 <<
769 MX8MM_IOMUXC_SAI1_TXD4 <<
770 MX8MM_IOMUXC_SAI1_TXD2 741 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
771 MX8MM_IOMUXC_SAI1_TXD0 742 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
772 MX8MM_IOMUXC_SAI1_TXC_ 743 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
773 MX8MM_IOMUXC_SAI1_MCLK 744 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
774 MX8MM_IOMUXC_SAI2_RXFS 745 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
775 MX8MM_IOMUXC_SAI2_RXC_ <<
776 MX8MM_IOMUXC_SAI2_MCLK 746 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
777 MX8MM_IOMUXC_SD1_DATA6 747 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
778 MX8MM_IOMUXC_SAI3_RXFS 748 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
779 MX8MM_IOMUXC_SPDIF_EXT 749 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
780 MX8MM_IOMUXC_SPDIF_RX_ 750 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
781 MX8MM_IOMUXC_SPDIF_TX_ 751 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
782 >; 752 >;
783 }; 753 };
784 754
785 pinctrl_accel: accelgrp { 755 pinctrl_accel: accelgrp {
786 fsl,pins = < 756 fsl,pins = <
787 MX8MM_IOMUXC_GPIO1_IO1 757 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
788 >; 758 >;
789 }; 759 };
790 760
791 pinctrl_fec1: fec1grp { 761 pinctrl_fec1: fec1grp {
792 fsl,pins = < 762 fsl,pins = <
793 MX8MM_IOMUXC_ENET_MDC_ 763 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
794 MX8MM_IOMUXC_ENET_MDIO 764 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
795 MX8MM_IOMUXC_ENET_TD3_ 765 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
796 MX8MM_IOMUXC_ENET_TD2_ 766 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
797 MX8MM_IOMUXC_ENET_TD1_ 767 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
798 MX8MM_IOMUXC_ENET_TD0_ 768 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
799 MX8MM_IOMUXC_ENET_RD3_ 769 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
800 MX8MM_IOMUXC_ENET_RD2_ 770 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
801 MX8MM_IOMUXC_ENET_RD1_ 771 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
802 MX8MM_IOMUXC_ENET_RD0_ 772 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
803 MX8MM_IOMUXC_ENET_TXC_ 773 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
804 MX8MM_IOMUXC_ENET_RXC_ 774 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
805 MX8MM_IOMUXC_ENET_RX_C 775 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
806 MX8MM_IOMUXC_ENET_TX_C 776 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
807 MX8MM_IOMUXC_GPIO1_IO1 777 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
808 MX8MM_IOMUXC_GPIO1_IO1 778 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
>> 779 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
>> 780 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
809 >; 781 >;
810 }; 782 };
811 783
812 pinctrl_gsc: gscgrp { 784 pinctrl_gsc: gscgrp {
813 fsl,pins = < 785 fsl,pins = <
814 MX8MM_IOMUXC_SD1_DATA4 786 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
815 >; 787 >;
816 }; 788 };
817 789
818 pinctrl_i2c1: i2c1grp { 790 pinctrl_i2c1: i2c1grp {
819 fsl,pins = < 791 fsl,pins = <
820 MX8MM_IOMUXC_I2C1_SCL_ 792 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
821 MX8MM_IOMUXC_I2C1_SDA_ 793 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
822 >; 794 >;
823 }; 795 };
824 796
825 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
826 fsl,pins = < <<
827 MX8MM_IOMUXC_I2C1_SCL_ <<
828 MX8MM_IOMUXC_I2C1_SDA_ <<
829 >; <<
830 }; <<
831 <<
832 pinctrl_i2c2: i2c2grp { 797 pinctrl_i2c2: i2c2grp {
833 fsl,pins = < 798 fsl,pins = <
834 MX8MM_IOMUXC_I2C2_SCL_ 799 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
835 MX8MM_IOMUXC_I2C2_SDA_ 800 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
836 >; 801 >;
837 }; 802 };
838 803
839 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
840 fsl,pins = < <<
841 MX8MM_IOMUXC_I2C2_SCL_ <<
842 MX8MM_IOMUXC_I2C2_SDA_ <<
843 >; <<
844 }; <<
845 <<
846 pinctrl_i2c3: i2c3grp { 804 pinctrl_i2c3: i2c3grp {
847 fsl,pins = < 805 fsl,pins = <
848 MX8MM_IOMUXC_I2C3_SCL_ 806 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
849 MX8MM_IOMUXC_I2C3_SDA_ 807 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
850 >; 808 >;
851 }; 809 };
852 810
853 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
854 fsl,pins = < <<
855 MX8MM_IOMUXC_I2C3_SCL_ <<
856 MX8MM_IOMUXC_I2C3_SDA_ <<
857 >; <<
858 }; <<
859 <<
860 pinctrl_i2c4: i2c4grp { 811 pinctrl_i2c4: i2c4grp {
861 fsl,pins = < 812 fsl,pins = <
862 MX8MM_IOMUXC_I2C4_SCL_ 813 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C4_SDA_ 814 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
864 >; 815 >;
865 }; 816 };
866 817
867 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
868 fsl,pins = < <<
869 MX8MM_IOMUXC_I2C4_SCL_ <<
870 MX8MM_IOMUXC_I2C4_SDA_ <<
871 >; <<
872 }; <<
873 <<
874 pinctrl_gpio_leds: gpioledgrp { 818 pinctrl_gpio_leds: gpioledgrp {
875 fsl,pins = < 819 fsl,pins = <
876 MX8MM_IOMUXC_SAI5_RXD0 820 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
877 MX8MM_IOMUXC_SAI5_RXD2 821 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
878 MX8MM_IOMUXC_SAI5_RXD1 822 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
879 MX8MM_IOMUXC_SAI5_RXC_ 823 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
880 MX8MM_IOMUXC_SAI5_MCLK 824 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
881 >; 825 >;
882 }; 826 };
883 827
884 pinctrl_pcie0: pciegrp { 828 pinctrl_pcie0: pciegrp {
885 fsl,pins = < 829 fsl,pins = <
886 MX8MM_IOMUXC_SAI1_RXD3 830 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
887 >; 831 >;
888 }; 832 };
889 833
890 pinctrl_pmic: pmicgrp { 834 pinctrl_pmic: pmicgrp {
891 fsl,pins = < 835 fsl,pins = <
892 MX8MM_IOMUXC_NAND_DATA 836 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
893 >; 837 >;
894 }; 838 };
895 839
896 pinctrl_pps: ppsgrp { 840 pinctrl_pps: ppsgrp {
897 fsl,pins = < 841 fsl,pins = <
898 MX8MM_IOMUXC_SAI5_RXD3 842 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
899 >; 843 >;
900 }; 844 };
901 845
902 pinctrl_reg_wl: regwlgrp { 846 pinctrl_reg_wl: regwlgrp {
903 fsl,pins = < 847 fsl,pins = <
904 MX8MM_IOMUXC_SD2_RESET 848 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
905 >; 849 >;
906 }; 850 };
907 851
908 pinctrl_reg_usb1: regusb1grp { 852 pinctrl_reg_usb1: regusb1grp {
909 fsl,pins = < 853 fsl,pins = <
910 MX8MM_IOMUXC_SD1_DATA5 854 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
911 >; 855 >;
912 }; 856 };
913 857
914 pinctrl_sai3: sai3grp { 858 pinctrl_sai3: sai3grp {
915 fsl,pins = < 859 fsl,pins = <
916 MX8MM_IOMUXC_SAI3_MCLK 860 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
917 MX8MM_IOMUXC_SAI3_RXD_ 861 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
918 MX8MM_IOMUXC_SAI3_TXC_ 862 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
919 MX8MM_IOMUXC_SAI3_TXD_ 863 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
920 MX8MM_IOMUXC_SAI3_TXFS 864 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
921 >; 865 >;
922 }; 866 };
923 867
924 pinctrl_spi1: spi1grp { 868 pinctrl_spi1: spi1grp {
925 fsl,pins = < 869 fsl,pins = <
926 MX8MM_IOMUXC_ECSPI1_SC 870 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
927 MX8MM_IOMUXC_ECSPI1_MO 871 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
928 MX8MM_IOMUXC_ECSPI1_MI 872 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
929 MX8MM_IOMUXC_ECSPI1_SS 873 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
930 MX8MM_IOMUXC_SD1_DATA1 874 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
931 >; 875 >;
932 }; 876 };
933 877
934 pinctrl_spi2: spi2grp { 878 pinctrl_spi2: spi2grp {
935 fsl,pins = < 879 fsl,pins = <
936 MX8MM_IOMUXC_ECSPI2_SC 880 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
937 MX8MM_IOMUXC_ECSPI2_MO 881 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
938 MX8MM_IOMUXC_ECSPI2_MI 882 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
939 MX8MM_IOMUXC_ECSPI2_SS 883 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
940 >; 884 >;
941 }; 885 };
942 886
943 pinctrl_uart1: uart1grp { 887 pinctrl_uart1: uart1grp {
944 fsl,pins = < 888 fsl,pins = <
945 MX8MM_IOMUXC_UART1_RXD 889 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
946 MX8MM_IOMUXC_UART1_TXD 890 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
947 MX8MM_IOMUXC_SAI1_TXFS 891 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
948 MX8MM_IOMUXC_SAI2_TXFS 892 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
949 >; 893 >;
950 }; 894 };
951 895
952 pinctrl_uart1_gpio: uart1gpiogrp { 896 pinctrl_uart1_gpio: uart1gpiogrp {
953 fsl,pins = < 897 fsl,pins = <
954 MX8MM_IOMUXC_SAI2_TXD0 898 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
955 MX8MM_IOMUXC_SAI2_TXC_ 899 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
956 MX8MM_IOMUXC_SAI2_RXD0 900 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
957 >; 901 >;
958 }; 902 };
959 903
960 pinctrl_uart2: uart2grp { 904 pinctrl_uart2: uart2grp {
961 fsl,pins = < 905 fsl,pins = <
962 MX8MM_IOMUXC_UART2_RXD 906 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
963 MX8MM_IOMUXC_UART2_TXD 907 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
964 >; 908 >;
965 }; 909 };
966 910
967 pinctrl_uart3_gpio: uart3_gpiogrp { 911 pinctrl_uart3_gpio: uart3_gpiogrp {
968 fsl,pins = < 912 fsl,pins = <
969 MX8MM_IOMUXC_SD2_CD_B_ 913 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
970 >; 914 >;
971 }; 915 };
972 916
973 pinctrl_uart3: uart3grp { 917 pinctrl_uart3: uart3grp {
974 fsl,pins = < 918 fsl,pins = <
975 MX8MM_IOMUXC_UART3_RXD 919 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
976 MX8MM_IOMUXC_UART3_TXD 920 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
977 MX8MM_IOMUXC_SD1_CLK_G 921 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
978 MX8MM_IOMUXC_SD1_CMD_G 922 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
979 >; 923 >;
980 }; 924 };
981 925
982 pinctrl_uart4: uart4grp { 926 pinctrl_uart4: uart4grp {
983 fsl,pins = < 927 fsl,pins = <
984 MX8MM_IOMUXC_UART4_RXD 928 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
985 MX8MM_IOMUXC_UART4_TXD 929 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
986 MX8MM_IOMUXC_SAI1_RXC_ 930 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
987 MX8MM_IOMUXC_SAI1_RXD0 931 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
988 MX8MM_IOMUXC_SAI1_RXD1 932 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
989 MX8MM_IOMUXC_SAI1_RXD2 933 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
990 MX8MM_IOMUXC_SAI1_RXD4 934 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
991 MX8MM_IOMUXC_SAI1_RXD5 935 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
992 MX8MM_IOMUXC_SAI1_RXFS 936 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
993 MX8MM_IOMUXC_GPIO1_IO0 937 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
994 >; 938 >;
995 }; 939 };
996 940
997 pinctrl_usdhc2: usdhc2grp { 941 pinctrl_usdhc2: usdhc2grp {
998 fsl,pins = < 942 fsl,pins = <
999 MX8MM_IOMUXC_SD2_CLK_U 943 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1000 MX8MM_IOMUXC_SD2_CMD_ 944 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1001 MX8MM_IOMUXC_SD2_DATA 945 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1002 MX8MM_IOMUXC_SD2_DATA 946 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1003 MX8MM_IOMUXC_SD2_DATA 947 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1004 MX8MM_IOMUXC_SD2_DATA 948 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1005 >; <<
1006 }; <<
1007 <<
1008 pinctrl_usdhc2_100mhz: usdhc2-100mhzg <<
1009 fsl,pins = < <<
1010 MX8MM_IOMUXC_SD2_CLK_ <<
1011 MX8MM_IOMUXC_SD2_CMD_ <<
1012 MX8MM_IOMUXC_SD2_DATA <<
1013 MX8MM_IOMUXC_SD2_DATA <<
1014 MX8MM_IOMUXC_SD2_DATA <<
1015 MX8MM_IOMUXC_SD2_DATA <<
1016 >; <<
1017 }; <<
1018 <<
1019 pinctrl_usdhc2_200mhz: usdhc2-200mhzg <<
1020 fsl,pins = < <<
1021 MX8MM_IOMUXC_SD2_CLK_ <<
1022 MX8MM_IOMUXC_SD2_CMD_ <<
1023 MX8MM_IOMUXC_SD2_DATA <<
1024 MX8MM_IOMUXC_SD2_DATA <<
1025 MX8MM_IOMUXC_SD2_DATA <<
1026 MX8MM_IOMUXC_SD2_DATA <<
1027 >; 949 >;
1028 }; 950 };
1029 951
1030 pinctrl_usdhc3: usdhc3grp { 952 pinctrl_usdhc3: usdhc3grp {
1031 fsl,pins = < 953 fsl,pins = <
1032 MX8MM_IOMUXC_NAND_WE_ 954 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1033 MX8MM_IOMUXC_NAND_WP_ 955 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1034 MX8MM_IOMUXC_NAND_DAT 956 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1035 MX8MM_IOMUXC_NAND_DAT 957 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1036 MX8MM_IOMUXC_NAND_DAT 958 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1037 MX8MM_IOMUXC_NAND_DAT 959 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1038 MX8MM_IOMUXC_NAND_RE_ 960 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1039 MX8MM_IOMUXC_NAND_CE2 961 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1040 MX8MM_IOMUXC_NAND_CE3 962 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1041 MX8MM_IOMUXC_NAND_CLE 963 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1042 MX8MM_IOMUXC_NAND_CE1 964 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1043 >; 965 >;
1044 }; 966 };
1045 967
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 968 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1047 fsl,pins = < 969 fsl,pins = <
1048 MX8MM_IOMUXC_NAND_WE_ 970 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1049 MX8MM_IOMUXC_NAND_WP_ 971 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1050 MX8MM_IOMUXC_NAND_DAT 972 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1051 MX8MM_IOMUXC_NAND_DAT 973 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1052 MX8MM_IOMUXC_NAND_DAT 974 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1053 MX8MM_IOMUXC_NAND_DAT 975 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1054 MX8MM_IOMUXC_NAND_RE_ 976 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1055 MX8MM_IOMUXC_NAND_CE2 977 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1056 MX8MM_IOMUXC_NAND_CE3 978 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1057 MX8MM_IOMUXC_NAND_CLE 979 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1058 MX8MM_IOMUXC_NAND_CE1 980 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1059 >; 981 >;
1060 }; 982 };
1061 983
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 984 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1063 fsl,pins = < 985 fsl,pins = <
1064 MX8MM_IOMUXC_NAND_WE_ 986 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1065 MX8MM_IOMUXC_NAND_WP_ 987 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1066 MX8MM_IOMUXC_NAND_DAT 988 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1067 MX8MM_IOMUXC_NAND_DAT 989 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1068 MX8MM_IOMUXC_NAND_DAT 990 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1069 MX8MM_IOMUXC_NAND_DAT 991 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1070 MX8MM_IOMUXC_NAND_RE_ 992 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1071 MX8MM_IOMUXC_NAND_CE2 993 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1072 MX8MM_IOMUXC_NAND_CE3 994 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1073 MX8MM_IOMUXC_NAND_CLE 995 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1074 MX8MM_IOMUXC_NAND_CE1 996 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1075 >; 997 >;
1076 }; 998 };
1077 999
1078 pinctrl_wdog: wdoggrp { 1000 pinctrl_wdog: wdoggrp {
1079 fsl,pins = < 1001 fsl,pins = <
1080 MX8MM_IOMUXC_GPIO1_IO 1002 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1081 >; 1003 >;
1082 }; 1004 };
1083 }; 1005 };
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