1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 13
14 #include "imx8mm.dtsi" 14 #include "imx8mm.dtsi"
15 15
16 / { 16 / {
17 model = "Gateworks Venice GW7902 i.MX8 17 model = "Gateworks Venice GW7902 i.MX8MM board";
18 compatible = "gw,imx8mm-gw7902", "fsl, 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19 19
20 aliases { 20 aliases {
21 ethernet1 = ð1; 21 ethernet1 = ð1;
22 usb0 = &usbotg1; 22 usb0 = &usbotg1;
23 usb1 = &usbotg2; 23 usb1 = &usbotg2;
24 }; 24 };
25 25
26 chosen { 26 chosen {
27 stdout-path = &uart2; 27 stdout-path = &uart2;
28 }; 28 };
29 29
30 memory@40000000 { 30 memory@40000000 {
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000 0 0x8000 32 reg = <0x0 0x40000000 0 0x80000000>;
33 }; 33 };
34 34
35 can20m: can20m { 35 can20m: can20m {
36 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
37 #clock-cells = <0>; 37 #clock-cells = <0>;
38 clock-frequency = <20000000>; 38 clock-frequency = <20000000>;
39 clock-output-names = "can20m"; 39 clock-output-names = "can20m";
40 }; 40 };
41 41
42 gpio-keys { 42 gpio-keys {
43 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
44 44
45 key-user-pb { 45 key-user-pb {
46 label = "user_pb"; 46 label = "user_pb";
47 gpios = <&gpio 2 GPIO_ 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48 linux,code = <BTN_0>; 48 linux,code = <BTN_0>;
49 }; 49 };
50 50
51 key-user-pb1x { 51 key-user-pb1x {
52 label = "user_pb1x"; 52 label = "user_pb1x";
53 linux,code = <BTN_1>; 53 linux,code = <BTN_1>;
54 interrupt-parent = <&g 54 interrupt-parent = <&gsc>;
55 interrupts = <0>; 55 interrupts = <0>;
56 }; 56 };
57 57
58 key-erased { 58 key-erased {
59 label = "key_erased"; 59 label = "key_erased";
60 linux,code = <BTN_2>; 60 linux,code = <BTN_2>;
61 interrupt-parent = <&g 61 interrupt-parent = <&gsc>;
62 interrupts = <1>; 62 interrupts = <1>;
63 }; 63 };
64 64
65 key-eeprom-wp { 65 key-eeprom-wp {
66 label = "eeprom_wp"; 66 label = "eeprom_wp";
67 linux,code = <BTN_3>; 67 linux,code = <BTN_3>;
68 interrupt-parent = <&g 68 interrupt-parent = <&gsc>;
69 interrupts = <2>; 69 interrupts = <2>;
70 }; 70 };
71 71
72 key-tamper { 72 key-tamper {
73 label = "tamper"; 73 label = "tamper";
74 linux,code = <BTN_4>; 74 linux,code = <BTN_4>;
75 interrupt-parent = <&g 75 interrupt-parent = <&gsc>;
76 interrupts = <5>; 76 interrupts = <5>;
77 }; 77 };
78 78
79 switch-hold { 79 switch-hold {
80 label = "switch_hold"; 80 label = "switch_hold";
81 linux,code = <BTN_5>; 81 linux,code = <BTN_5>;
82 interrupt-parent = <&g 82 interrupt-parent = <&gsc>;
83 interrupts = <7>; 83 interrupts = <7>;
84 }; 84 };
85 }; 85 };
86 86
87 led-controller { 87 led-controller {
88 compatible = "gpio-leds"; 88 compatible = "gpio-leds";
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_gpio_led 90 pinctrl-0 = <&pinctrl_gpio_leds>;
91 91
92 led-0 { 92 led-0 {
93 function = LED_FUNCTIO 93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_ 94 color = <LED_COLOR_ID_GREEN>;
95 label = "panel1"; 95 label = "panel1";
96 gpios = <&gpio3 21 GPI 96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97 default-state = "off"; 97 default-state = "off";
98 }; 98 };
99 99
100 led-1 { 100 led-1 {
101 function = LED_FUNCTIO 101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_ 102 color = <LED_COLOR_ID_GREEN>;
103 label = "panel2"; 103 label = "panel2";
104 gpios = <&gpio3 23 GPI 104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105 default-state = "off"; 105 default-state = "off";
106 }; 106 };
107 107
108 led-2 { 108 led-2 {
109 function = LED_FUNCTIO 109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_ 110 color = <LED_COLOR_ID_GREEN>;
111 label = "panel3"; 111 label = "panel3";
112 gpios = <&gpio3 22 GPI 112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113 default-state = "off"; 113 default-state = "off";
114 }; 114 };
115 115
116 led-3 { 116 led-3 {
117 function = LED_FUNCTIO 117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_ 118 color = <LED_COLOR_ID_GREEN>;
119 label = "panel4"; 119 label = "panel4";
120 gpios = <&gpio3 20 GPI 120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121 default-state = "off"; 121 default-state = "off";
122 }; 122 };
123 123
124 led-4 { 124 led-4 {
125 function = LED_FUNCTIO 125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_ 126 color = <LED_COLOR_ID_GREEN>;
127 label = "panel5"; 127 label = "panel5";
128 gpios = <&gpio3 25 GPI 128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129 default-state = "off"; 129 default-state = "off";
130 }; 130 };
131 }; 131 };
132 132
133 pcie0_refclk: pcie0-refclk { 133 pcie0_refclk: pcie0-refclk {
134 compatible = "fixed-clock"; 134 compatible = "fixed-clock";
135 #clock-cells = <0>; 135 #clock-cells = <0>;
136 clock-frequency = <100000000>; 136 clock-frequency = <100000000>;
137 }; 137 };
138 138
139 pps { 139 pps {
140 compatible = "pps-gpio"; 140 compatible = "pps-gpio";
141 pinctrl-names = "default"; 141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pps>; 142 pinctrl-0 = <&pinctrl_pps>;
143 gpios = <&gpio3 24 GPIO_ACTIVE 143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144 status = "okay"; 144 status = "okay";
145 }; 145 };
146 146
147 reg_3p3v: regulator-3p3v { 147 reg_3p3v: regulator-3p3v {
148 compatible = "regulator-fixed" 148 compatible = "regulator-fixed";
149 regulator-name = "3P3V"; 149 regulator-name = "3P3V";
150 regulator-min-microvolt = <330 150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <330 151 regulator-max-microvolt = <3300000>;
152 regulator-always-on; 152 regulator-always-on;
153 }; 153 };
154 154
155 reg_usb1_vbus: regulator-usb1 { 155 reg_usb1_vbus: regulator-usb1 {
156 compatible = "regulator-fixed" 156 compatible = "regulator-fixed";
157 pinctrl-names = "default"; 157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_usb1 158 pinctrl-0 = <&pinctrl_reg_usb1>;
159 regulator-name = "usb_usb1_vbu 159 regulator-name = "usb_usb1_vbus";
160 gpio = <&gpio2 7 GPIO_ACTIVE_H 160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161 enable-active-high; 161 enable-active-high;
162 regulator-min-microvolt = <500 162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <500 163 regulator-max-microvolt = <5000000>;
164 }; 164 };
165 165
166 reg_wifi: regulator-wifi { 166 reg_wifi: regulator-wifi {
167 compatible = "regulator-fixed" 167 compatible = "regulator-fixed";
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_reg_wl>; 169 pinctrl-0 = <&pinctrl_reg_wl>;
170 regulator-name = "wifi"; 170 regulator-name = "wifi";
171 gpio = <&gpio2 19 GPIO_ACTIVE_ 171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172 enable-active-high; 172 enable-active-high;
173 startup-delay-us = <100>; 173 startup-delay-us = <100>;
174 regulator-min-microvolt = <330 174 regulator-min-microvolt = <3300000>;
175 regulator-max-microvolt = <330 175 regulator-max-microvolt = <3300000>;
176 }; 176 };
177 }; 177 };
178 178
179 &A53_0 { 179 &A53_0 {
180 cpu-supply = <&buck2>; 180 cpu-supply = <&buck2>;
181 }; 181 };
182 182
183 &A53_1 { 183 &A53_1 {
184 cpu-supply = <&buck2>; 184 cpu-supply = <&buck2>;
185 }; 185 };
186 186
187 &A53_2 { 187 &A53_2 {
188 cpu-supply = <&buck2>; 188 cpu-supply = <&buck2>;
189 }; 189 };
190 190
191 &A53_3 { 191 &A53_3 {
192 cpu-supply = <&buck2>; 192 cpu-supply = <&buck2>;
193 }; 193 };
194 194
195 &ddrc { 195 &ddrc {
196 operating-points-v2 = <&ddrc_opp_table 196 operating-points-v2 = <&ddrc_opp_table>;
197 197
198 ddrc_opp_table: opp-table { 198 ddrc_opp_table: opp-table {
199 compatible = "operating-points 199 compatible = "operating-points-v2";
200 200
201 opp-25000000 { 201 opp-25000000 {
202 opp-hz = /bits/ 64 <25 202 opp-hz = /bits/ 64 <25000000>;
203 }; 203 };
204 204
205 opp-100000000 { 205 opp-100000000 {
206 opp-hz = /bits/ 64 <10 206 opp-hz = /bits/ 64 <100000000>;
207 }; 207 };
208 208
209 opp-750000000 { 209 opp-750000000 {
210 opp-hz = /bits/ 64 <75 210 opp-hz = /bits/ 64 <750000000>;
211 }; 211 };
212 }; 212 };
213 }; 213 };
214 214
215 &ecspi1 { 215 &ecspi1 {
216 pinctrl-names = "default"; 216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spi1>; 217 pinctrl-0 = <&pinctrl_spi1>;
218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219 status = "okay"; 219 status = "okay";
220 220
221 can@0 { 221 can@0 {
222 compatible = "microchip,mcp251 222 compatible = "microchip,mcp2515";
223 reg = <0>; 223 reg = <0>;
224 clocks = <&can20m>; 224 clocks = <&can20m>;
225 interrupt-parent = <&gpio2>; 225 interrupt-parent = <&gpio2>;
226 interrupts = <3 IRQ_TYPE_LEVEL 226 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227 spi-max-frequency = <10000000> 227 spi-max-frequency = <10000000>;
228 }; 228 };
229 }; 229 };
230 230
231 /* off-board header */ 231 /* off-board header */
232 &ecspi2 { 232 &ecspi2 {
233 pinctrl-names = "default"; 233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_spi2>; 234 pinctrl-0 = <&pinctrl_spi2>;
235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 235 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236 status = "okay"; 236 status = "okay";
237 }; 237 };
238 238
239 &fec1 { 239 &fec1 {
240 pinctrl-names = "default"; 240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_fec1>; 241 pinctrl-0 = <&pinctrl_fec1>;
242 phy-mode = "rgmii-id"; 242 phy-mode = "rgmii-id";
243 phy-handle = <ðphy0>; 243 phy-handle = <ðphy0>;
244 local-mac-address = [00 00 00 00 00 00 244 local-mac-address = [00 00 00 00 00 00];
245 status = "okay"; 245 status = "okay";
246 246
247 mdio { 247 mdio {
248 #address-cells = <1>; 248 #address-cells = <1>;
249 #size-cells = <0>; 249 #size-cells = <0>;
250 250
251 ethphy0: ethernet-phy@0 { 251 ethphy0: ethernet-phy@0 {
252 compatible = "ethernet 252 compatible = "ethernet-phy-ieee802.3-c22";
253 reg = <0>; 253 reg = <0>;
254 ti,rx-internal-delay = 254 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255 ti,tx-internal-delay = 255 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256 tx-fifo-depth = <DP838 256 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257 rx-fifo-depth = <DP838 257 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 }; 258 };
259 }; 259 };
260 }; 260 };
261 261
262 &gpio1 { 262 &gpio1 {
263 gpio-line-names = "", "", "", "", "", 263 gpio-line-names = "", "", "", "", "", "", "", "",
264 "m2_pwr_en", "", "", "", "", " 264 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
265 "", "", "", "", "", "", "", "" 265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "" 266 "", "", "", "", "", "", "", "";
267 }; 267 };
268 268
269 &gpio2 { 269 &gpio2 {
270 gpio-line-names = "", "", "", "", "", 270 gpio-line-names = "", "", "", "", "", "", "", "",
271 "uart2_en#", "", "", "", "", " 271 "uart2_en#", "", "", "", "", "", "", "",
272 "", "", "", "", "", "", "", "" 272 "", "", "", "", "", "", "", "",
273 "", "", "", "", "", "", "", "" 273 "", "", "", "", "", "", "", "";
274 }; 274 };
275 275
276 &gpio3 { 276 &gpio3 {
277 gpio-line-names = "", "m2_gdis#", "", 277 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278 "", "", "", "", "", "", "", "" 278 "", "", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "" 279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 280 "", "", "", "", "", "", "", "";
281 }; 281 };
282 282
283 &gpio4 { 283 &gpio4 {
284 gpio-line-names = "", "", "", "", "", 284 gpio-line-names = "", "", "", "", "", "", "", "",
285 "", "", "", "amp_gpio3", "amp_ 285 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286 "lte_pwr#", "lte_rst", "lte_in 286 "lte_pwr#", "lte_rst", "lte_int", "",
287 "amp_gpio4", "app_gpio1", "vdd 287 "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
288 "", "uart1_term", "uart1_half" 288 "", "uart1_term", "uart1_half", "app_gpio2",
289 "mipi_gpio1", "", "", ""; 289 "mipi_gpio1", "", "", "";
290 }; 290 };
291 291
292 &gpio5 { 292 &gpio5 {
293 gpio-line-names = "", "", "", "mipi_gp 293 gpio-line-names = "", "", "", "mipi_gpio4",
294 "mipi_gpio3", "mipi_gpio2", "" 294 "mipi_gpio3", "mipi_gpio2", "", "",
295 "", "", "", "", "", "", "", "" 295 "", "", "", "", "", "", "", "",
296 "", "", "", "", "", "", "", "" 296 "", "", "", "", "", "", "", "",
297 "", "", "", "", "", "", "", "" 297 "", "", "", "", "", "", "", "";
298 }; 298 };
299 299
300 &i2c1 { 300 &i2c1 {
301 clock-frequency = <100000>; 301 clock-frequency = <100000>;
302 pinctrl-names = "default", "gpio"; 302 pinctrl-names = "default", "gpio";
303 pinctrl-0 = <&pinctrl_i2c1>; 303 pinctrl-0 = <&pinctrl_i2c1>;
304 pinctrl-1 = <&pinctrl_i2c1_gpio>; 304 pinctrl-1 = <&pinctrl_i2c1_gpio>;
305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
307 status = "okay"; 307 status = "okay";
308 308
309 gsc: gsc@20 { 309 gsc: gsc@20 {
310 compatible = "gw,gsc"; 310 compatible = "gw,gsc";
311 reg = <0x20>; 311 reg = <0x20>;
312 pinctrl-0 = <&pinctrl_gsc>; 312 pinctrl-0 = <&pinctrl_gsc>;
313 interrupt-parent = <&gpio2>; 313 interrupt-parent = <&gpio2>;
314 interrupts = <6 IRQ_TYPE_EDGE_ 314 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315 interrupt-controller; 315 interrupt-controller;
316 #interrupt-cells = <1>; 316 #interrupt-cells = <1>;
317 #address-cells = <1>; <<
318 #size-cells = <0>; <<
319 317
320 adc { 318 adc {
321 compatible = "gw,gsc-a 319 compatible = "gw,gsc-adc";
322 #address-cells = <1>; 320 #address-cells = <1>;
323 #size-cells = <0>; 321 #size-cells = <0>;
324 322
325 channel@6 { 323 channel@6 {
326 gw,mode = <0>; 324 gw,mode = <0>;
327 reg = <0x06>; 325 reg = <0x06>;
328 label = "temp" 326 label = "temp";
329 }; 327 };
330 328
331 channel@8 { 329 channel@8 {
332 gw,mode = <3>; 330 gw,mode = <3>;
333 reg = <0x08>; 331 reg = <0x08>;
334 label = "vdd_b 332 label = "vdd_bat";
335 }; 333 };
336 334
337 channel@82 { 335 channel@82 {
338 gw,mode = <2>; 336 gw,mode = <2>;
339 reg = <0x82>; 337 reg = <0x82>;
340 label = "vin"; 338 label = "vin";
341 gw,voltage-div 339 gw,voltage-divider-ohms = <22100 1000>;
342 gw,voltage-off 340 gw,voltage-offset-microvolt = <700000>;
343 }; 341 };
344 342
345 channel@84 { 343 channel@84 {
346 gw,mode = <2>; 344 gw,mode = <2>;
347 reg = <0x84>; 345 reg = <0x84>;
348 label = "vin_4 346 label = "vin_4p0";
349 gw,voltage-div 347 gw,voltage-divider-ohms = <10000 10000>;
350 }; 348 };
351 349
352 channel@86 { 350 channel@86 {
353 gw,mode = <2>; 351 gw,mode = <2>;
354 reg = <0x86>; 352 reg = <0x86>;
355 label = "vdd_3 353 label = "vdd_3p3";
356 gw,voltage-div 354 gw,voltage-divider-ohms = <10000 10000>;
357 }; 355 };
358 356
359 channel@88 { 357 channel@88 {
360 gw,mode = <2>; 358 gw,mode = <2>;
361 reg = <0x88>; 359 reg = <0x88>;
362 label = "vdd_0 360 label = "vdd_0p9";
363 }; 361 };
364 362
365 channel@8c { 363 channel@8c {
366 gw,mode = <2>; 364 gw,mode = <2>;
367 reg = <0x8c>; 365 reg = <0x8c>;
368 label = "vdd_s 366 label = "vdd_soc";
369 }; 367 };
370 368
371 channel@8e { 369 channel@8e {
372 gw,mode = <2>; 370 gw,mode = <2>;
373 reg = <0x8e>; 371 reg = <0x8e>;
374 label = "vdd_a 372 label = "vdd_arm";
375 }; 373 };
376 374
377 channel@90 { 375 channel@90 {
378 gw,mode = <2>; 376 gw,mode = <2>;
379 reg = <0x90>; 377 reg = <0x90>;
380 label = "vdd_1 378 label = "vdd_1p8";
381 }; 379 };
382 380
383 channel@92 { 381 channel@92 {
384 gw,mode = <2>; 382 gw,mode = <2>;
385 reg = <0x92>; 383 reg = <0x92>;
386 label = "vdd_d 384 label = "vdd_dram";
387 }; 385 };
388 386
389 channel@98 { 387 channel@98 {
390 gw,mode = <2>; 388 gw,mode = <2>;
391 reg = <0x98>; 389 reg = <0x98>;
392 label = "vdd_1 390 label = "vdd_1p0";
393 }; 391 };
394 392
395 channel@9a { 393 channel@9a {
396 gw,mode = <2>; 394 gw,mode = <2>;
397 reg = <0x9a>; 395 reg = <0x9a>;
398 label = "vdd_2 396 label = "vdd_2p5";
399 gw,voltage-div 397 gw,voltage-divider-ohms = <10000 10000>;
400 }; 398 };
401 399
402 channel@9c { 400 channel@9c {
403 gw,mode = <2>; 401 gw,mode = <2>;
404 reg = <0x9c>; 402 reg = <0x9c>;
405 label = "vdd_5 403 label = "vdd_5p0";
406 gw,voltage-div 404 gw,voltage-divider-ohms = <10000 10000>;
407 }; 405 };
408 406
409 channel@a2 { 407 channel@a2 {
410 gw,mode = <2>; 408 gw,mode = <2>;
411 reg = <0xa2>; 409 reg = <0xa2>;
412 label = "vdd_g 410 label = "vdd_gsc";
413 gw,voltage-div 411 gw,voltage-divider-ohms = <10000 10000>;
414 }; 412 };
415 }; 413 };
416 }; 414 };
417 415
418 gpio: gpio@23 { 416 gpio: gpio@23 {
419 compatible = "nxp,pca9555"; 417 compatible = "nxp,pca9555";
420 reg = <0x23>; 418 reg = <0x23>;
421 gpio-controller; 419 gpio-controller;
422 #gpio-cells = <2>; 420 #gpio-cells = <2>;
423 interrupt-parent = <&gsc>; 421 interrupt-parent = <&gsc>;
424 interrupts = <4>; 422 interrupts = <4>;
425 }; 423 };
426 424
427 pmic@4b { 425 pmic@4b {
428 compatible = "rohm,bd71847"; 426 compatible = "rohm,bd71847";
429 reg = <0x4b>; 427 reg = <0x4b>;
430 pinctrl-names = "default"; 428 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_pmic>; 429 pinctrl-0 = <&pinctrl_pmic>;
432 interrupt-parent = <&gpio3>; 430 interrupt-parent = <&gpio3>;
433 interrupts = <8 IRQ_TYPE_LEVEL 431 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
434 rohm,reset-snvs-powered; 432 rohm,reset-snvs-powered;
435 #clock-cells = <0>; 433 #clock-cells = <0>;
436 clocks = <&osc_32k>; 434 clocks = <&osc_32k>;
437 clock-output-names = "clk-32k- 435 clock-output-names = "clk-32k-out";
438 436
439 regulators { 437 regulators {
440 /* vdd_soc: 0.805-0.90 438 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
441 BUCK1 { 439 BUCK1 {
442 regulator-name 440 regulator-name = "buck1";
443 regulator-min- 441 regulator-min-microvolt = <700000>;
444 regulator-max- 442 regulator-max-microvolt = <1300000>;
445 regulator-boot 443 regulator-boot-on;
446 regulator-alwa 444 regulator-always-on;
447 regulator-ramp 445 regulator-ramp-delay = <1250>;
448 }; 446 };
449 447
450 /* vdd_arm: 0.805-1.0V 448 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
451 buck2: BUCK2 { 449 buck2: BUCK2 {
452 regulator-name 450 regulator-name = "buck2";
453 regulator-min- 451 regulator-min-microvolt = <700000>;
454 regulator-max- 452 regulator-max-microvolt = <1300000>;
455 regulator-boot 453 regulator-boot-on;
456 regulator-alwa 454 regulator-always-on;
457 regulator-ramp 455 regulator-ramp-delay = <1250>;
458 rohm,dvs-run-v 456 rohm,dvs-run-voltage = <1000000>;
459 rohm,dvs-idle- 457 rohm,dvs-idle-voltage = <900000>;
460 }; 458 };
461 459
462 /* vdd_0p9: 0.805-1.0V 460 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
463 BUCK3 { 461 BUCK3 {
464 regulator-name 462 regulator-name = "buck3";
465 regulator-min- 463 regulator-min-microvolt = <700000>;
466 regulator-max- 464 regulator-max-microvolt = <1350000>;
467 regulator-boot 465 regulator-boot-on;
468 regulator-alwa 466 regulator-always-on;
469 }; 467 };
470 468
471 /* vdd_3p3 */ 469 /* vdd_3p3 */
472 BUCK4 { 470 BUCK4 {
473 regulator-name 471 regulator-name = "buck4";
474 regulator-min- 472 regulator-min-microvolt = <3000000>;
475 regulator-max- 473 regulator-max-microvolt = <3300000>;
476 regulator-boot 474 regulator-boot-on;
477 regulator-alwa 475 regulator-always-on;
478 }; 476 };
479 477
480 /* vdd_1p8 */ 478 /* vdd_1p8 */
481 BUCK5 { 479 BUCK5 {
482 regulator-name 480 regulator-name = "buck5";
483 regulator-min- 481 regulator-min-microvolt = <1605000>;
484 regulator-max- 482 regulator-max-microvolt = <1995000>;
485 regulator-boot 483 regulator-boot-on;
486 regulator-alwa 484 regulator-always-on;
487 }; 485 };
488 486
489 /* vdd_dram */ 487 /* vdd_dram */
490 BUCK6 { 488 BUCK6 {
491 regulator-name 489 regulator-name = "buck6";
492 regulator-min- 490 regulator-min-microvolt = <800000>;
493 regulator-max- 491 regulator-max-microvolt = <1400000>;
494 regulator-boot 492 regulator-boot-on;
495 regulator-alwa 493 regulator-always-on;
496 }; 494 };
497 495
498 /* nvcc_snvs_1p8 */ 496 /* nvcc_snvs_1p8 */
499 LDO1 { 497 LDO1 {
500 regulator-name 498 regulator-name = "ldo1";
501 regulator-min- 499 regulator-min-microvolt = <1600000>;
502 regulator-max- 500 regulator-max-microvolt = <1900000>;
503 regulator-boot 501 regulator-boot-on;
504 regulator-alwa 502 regulator-always-on;
505 }; 503 };
506 504
507 /* vdd_snvs_0p8 */ 505 /* vdd_snvs_0p8 */
508 LDO2 { 506 LDO2 {
509 regulator-name 507 regulator-name = "ldo2";
510 regulator-min- 508 regulator-min-microvolt = <800000>;
511 regulator-max- 509 regulator-max-microvolt = <900000>;
512 regulator-boot 510 regulator-boot-on;
513 regulator-alwa 511 regulator-always-on;
514 }; 512 };
515 513
516 /* vdda_1p8 */ 514 /* vdda_1p8 */
517 LDO3 { 515 LDO3 {
518 regulator-name 516 regulator-name = "ldo3";
519 regulator-min- 517 regulator-min-microvolt = <1800000>;
520 regulator-max- 518 regulator-max-microvolt = <3300000>;
521 regulator-boot 519 regulator-boot-on;
522 regulator-alwa 520 regulator-always-on;
523 }; 521 };
524 522
525 LDO4 { 523 LDO4 {
526 regulator-name 524 regulator-name = "ldo4";
527 regulator-min- 525 regulator-min-microvolt = <900000>;
528 regulator-max- 526 regulator-max-microvolt = <1800000>;
529 regulator-boot 527 regulator-boot-on;
530 regulator-alwa 528 regulator-always-on;
531 }; 529 };
532 530
533 LDO6 { 531 LDO6 {
534 regulator-name 532 regulator-name = "ldo6";
535 regulator-min- 533 regulator-min-microvolt = <900000>;
536 regulator-max- 534 regulator-max-microvolt = <1800000>;
537 regulator-boot 535 regulator-boot-on;
538 regulator-alwa 536 regulator-always-on;
539 }; 537 };
540 }; 538 };
541 }; 539 };
542 540
543 eeprom@50 { 541 eeprom@50 {
544 compatible = "atmel,24c02"; 542 compatible = "atmel,24c02";
545 reg = <0x50>; 543 reg = <0x50>;
546 pagesize = <16>; 544 pagesize = <16>;
547 }; 545 };
548 546
549 eeprom@51 { 547 eeprom@51 {
550 compatible = "atmel,24c02"; 548 compatible = "atmel,24c02";
551 reg = <0x51>; 549 reg = <0x51>;
552 pagesize = <16>; 550 pagesize = <16>;
553 }; 551 };
554 552
555 eeprom@52 { 553 eeprom@52 {
556 compatible = "atmel,24c02"; 554 compatible = "atmel,24c02";
557 reg = <0x52>; 555 reg = <0x52>;
558 pagesize = <16>; 556 pagesize = <16>;
559 }; 557 };
560 558
561 eeprom@53 { 559 eeprom@53 {
562 compatible = "atmel,24c02"; 560 compatible = "atmel,24c02";
563 reg = <0x53>; 561 reg = <0x53>;
564 pagesize = <16>; 562 pagesize = <16>;
565 }; 563 };
566 564
567 rtc@68 { 565 rtc@68 {
568 compatible = "dallas,ds1672"; 566 compatible = "dallas,ds1672";
569 reg = <0x68>; 567 reg = <0x68>;
570 }; 568 };
571 }; 569 };
572 570
573 &i2c2 { 571 &i2c2 {
574 clock-frequency = <400000>; 572 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio"; 573 pinctrl-names = "default", "gpio";
576 pinctrl-0 = <&pinctrl_i2c2>; 574 pinctrl-0 = <&pinctrl_i2c2>;
577 pinctrl-1 = <&pinctrl_i2c2_gpio>; 575 pinctrl-1 = <&pinctrl_i2c2_gpio>;
578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
580 status = "okay"; 578 status = "okay";
581 579
582 accelerometer@19 { 580 accelerometer@19 {
583 compatible = "st,lis2de12"; 581 compatible = "st,lis2de12";
584 pinctrl-names = "default"; 582 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_accel>; 583 pinctrl-0 = <&pinctrl_accel>;
586 reg = <0x19>; 584 reg = <0x19>;
587 st,drdy-int-pin = <1>; 585 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>; 586 interrupt-parent = <&gpio1>;
589 interrupts = <12 IRQ_TYPE_LEVE 587 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 588 interrupt-names = "INT1";
590 }; 589 };
591 }; 590 };
592 591
593 /* off-board header */ 592 /* off-board header */
594 &i2c3 { 593 &i2c3 {
595 clock-frequency = <400000>; 594 clock-frequency = <400000>;
596 pinctrl-names = "default", "gpio"; 595 pinctrl-names = "default", "gpio";
597 pinctrl-0 = <&pinctrl_i2c3>; 596 pinctrl-0 = <&pinctrl_i2c3>;
598 pinctrl-1 = <&pinctrl_i2c3_gpio>; 597 pinctrl-1 = <&pinctrl_i2c3_gpio>;
599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 598 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 599 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
601 status = "okay"; 600 status = "okay";
602 }; 601 };
603 602
604 /* off-board header */ 603 /* off-board header */
605 &i2c4 { 604 &i2c4 {
606 clock-frequency = <400000>; 605 clock-frequency = <400000>;
607 pinctrl-names = "default", "gpio"; 606 pinctrl-names = "default", "gpio";
608 pinctrl-0 = <&pinctrl_i2c4>; 607 pinctrl-0 = <&pinctrl_i2c4>;
609 pinctrl-1 = <&pinctrl_i2c4_gpio>; 608 pinctrl-1 = <&pinctrl_i2c4_gpio>;
610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 609 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 610 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
612 status = "okay"; 611 status = "okay";
613 }; 612 };
614 613
615 &pcie_phy { 614 &pcie_phy {
616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 615 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
617 fsl,clkreq-unsupported; 616 fsl,clkreq-unsupported;
618 clocks = <&pcie0_refclk>; 617 clocks = <&pcie0_refclk>;
619 clock-names = "ref"; 618 clock-names = "ref";
620 status = "okay"; 619 status = "okay";
621 }; 620 };
622 621
623 &pcie0 { 622 &pcie0 {
624 pinctrl-names = "default"; 623 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_pcie0>; 624 pinctrl-0 = <&pinctrl_pcie0>;
626 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW 625 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 626 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
628 <&clk IMX8MM_CLK_PCIE1_AUX>; 627 <&clk IMX8MM_CLK_PCIE1_AUX>;
629 assigned-clocks = <&clk IMX8MM_CLK_PCI 628 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
630 <&clk IMX8MM_CLK_PCI 629 <&clk IMX8MM_CLK_PCIE1_CTRL>;
631 assigned-clock-rates = <10000000>, <25 630 assigned-clock-rates = <10000000>, <250000000>;
632 assigned-clock-parents = <&clk IMX8MM_ 631 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
633 <&clk IMX8MM_ 632 <&clk IMX8MM_SYS_PLL2_250M>;
634 status = "okay"; 633 status = "okay";
635 634
636 pcie@0,0 { 635 pcie@0,0 {
637 reg = <0x0000 0 0 0 0>; 636 reg = <0x0000 0 0 0 0>;
638 device_type = "pci"; !! 637 #address-cells = <1>;
639 #address-cells = <3>; !! 638 #size-cells = <0>;
640 #size-cells = <2>; <<
641 ranges; <<
642 639
643 eth1: ethernet@0,0 { !! 640 eth1: pcie@1,0 {
644 reg = <0x0000 0 0 0 0> 641 reg = <0x0000 0 0 0 0>;
645 #address-cells = <3>; !! 642 #address-cells = <1>;
646 #size-cells = <2>; !! 643 #size-cells = <0>;
647 ranges; <<
648 644
649 local-mac-address = [0 645 local-mac-address = [00 00 00 00 00 00];
650 }; 646 };
651 }; 647 };
652 }; 648 };
653 649
654 /* off-board header */ 650 /* off-board header */
655 &sai3 { 651 &sai3 {
656 pinctrl-names = "default"; 652 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_sai3>; 653 pinctrl-0 = <&pinctrl_sai3>;
658 assigned-clocks = <&clk IMX8MM_CLK_SAI 654 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
659 assigned-clock-parents = <&clk IMX8MM_ 655 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
660 assigned-clock-rates = <24576000>; 656 assigned-clock-rates = <24576000>;
661 status = "okay"; 657 status = "okay";
662 }; 658 };
663 659
664 /* RS232/RS485/RS422 selectable */ 660 /* RS232/RS485/RS422 selectable */
665 &uart1 { 661 &uart1 {
666 pinctrl-names = "default"; 662 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 663 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
668 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW 664 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
669 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW 665 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
670 status = "okay"; 666 status = "okay";
671 }; 667 };
672 668
673 /* RS232 console */ 669 /* RS232 console */
674 &uart2 { 670 &uart2 {
675 pinctrl-names = "default"; 671 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_uart2>; 672 pinctrl-0 = <&pinctrl_uart2>;
677 status = "okay"; 673 status = "okay";
678 }; 674 };
679 675
680 /* bluetooth HCI */ 676 /* bluetooth HCI */
681 &uart3 { 677 &uart3 {
682 pinctrl-names = "default"; 678 pinctrl-names = "default";
683 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 679 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
684 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 680 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
685 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 681 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
686 status = "okay"; 682 status = "okay";
687 683
688 bluetooth { 684 bluetooth {
689 compatible = "brcm,bcm4330-bt" 685 compatible = "brcm,bcm4330-bt";
690 shutdown-gpios = <&gpio2 12 GP 686 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
691 }; 687 };
692 }; 688 };
693 689
694 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 690 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
695 &uart4 { 691 &uart4 {
696 pinctrl-names = "default"; 692 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_uart4>; 693 pinctrl-0 = <&pinctrl_uart4>;
698 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW> 694 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
699 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW> 695 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
700 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW> 696 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
701 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW> 697 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
702 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW> 698 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
703 status = "okay"; 699 status = "okay";
704 }; 700 };
705 701
706 &usbotg1 { 702 &usbotg1 {
707 dr_mode = "host"; 703 dr_mode = "host";
708 vbus-supply = <®_usb1_vbus>; 704 vbus-supply = <®_usb1_vbus>;
709 disable-over-current; 705 disable-over-current;
710 status = "okay"; 706 status = "okay";
711 }; 707 };
712 708
713 &usbotg2 { 709 &usbotg2 {
714 dr_mode = "host"; 710 dr_mode = "host";
715 disable-over-current; 711 disable-over-current;
716 status = "okay"; 712 status = "okay";
717 }; 713 };
718 714
719 /* SDIO WiFi */ 715 /* SDIO WiFi */
720 &usdhc2 { 716 &usdhc2 {
721 pinctrl-names = "default", "state_100m 717 pinctrl-names = "default", "state_100mhz", "state_200mhz";
722 pinctrl-0 = <&pinctrl_usdhc2>; 718 pinctrl-0 = <&pinctrl_usdhc2>;
723 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 719 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
724 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 720 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
725 bus-width = <4>; 721 bus-width = <4>;
726 non-removable; 722 non-removable;
727 vmmc-supply = <®_wifi>; 723 vmmc-supply = <®_wifi>;
728 #address-cells = <1>; 724 #address-cells = <1>;
729 #size-cells = <0>; 725 #size-cells = <0>;
730 status = "okay"; 726 status = "okay";
731 727
732 wifi@0 { 728 wifi@0 {
733 compatible = "brcm,bcm43455-fm 729 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
734 reg = <0>; 730 reg = <0>;
735 }; 731 };
736 }; 732 };
737 733
738 /* eMMC */ 734 /* eMMC */
739 &usdhc3 { 735 &usdhc3 {
740 pinctrl-names = "default", "state_100m 736 pinctrl-names = "default", "state_100mhz", "state_200mhz";
741 pinctrl-0 = <&pinctrl_usdhc3>; 737 pinctrl-0 = <&pinctrl_usdhc3>;
742 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 738 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
743 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 739 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
744 bus-width = <8>; 740 bus-width = <8>;
745 non-removable; 741 non-removable;
746 status = "okay"; 742 status = "okay";
747 }; 743 };
748 744
749 &wdog1 { 745 &wdog1 {
750 pinctrl-names = "default"; 746 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_wdog>; 747 pinctrl-0 = <&pinctrl_wdog>;
752 fsl,ext-reset-output; 748 fsl,ext-reset-output;
753 status = "okay"; 749 status = "okay";
754 }; 750 };
755 751
756 &iomuxc { 752 &iomuxc {
757 pinctrl-names = "default"; 753 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_hog>; 754 pinctrl-0 = <&pinctrl_hog>;
759 755
760 pinctrl_hog: hoggrp { 756 pinctrl_hog: hoggrp {
761 fsl,pins = < 757 fsl,pins = <
762 MX8MM_IOMUXC_NAND_CE0_ 758 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
763 MX8MM_IOMUXC_GPIO1_IO0 759 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
764 MX8MM_IOMUXC_GPIO1_IO1 760 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
765 MX8MM_IOMUXC_NAND_DATA 761 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
766 MX8MM_IOMUXC_GPIO1_IO1 762 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
767 MX8MM_IOMUXC_SAI1_TXD6 763 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
768 MX8MM_IOMUXC_SAI1_TXD5 764 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
769 MX8MM_IOMUXC_SAI1_TXD4 765 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
770 MX8MM_IOMUXC_SAI1_TXD2 766 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
771 MX8MM_IOMUXC_SAI1_TXD0 767 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
772 MX8MM_IOMUXC_SAI1_TXC_ 768 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
773 MX8MM_IOMUXC_SAI1_MCLK 769 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
774 MX8MM_IOMUXC_SAI2_RXFS 770 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
775 MX8MM_IOMUXC_SAI2_RXC_ 771 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
776 MX8MM_IOMUXC_SAI2_MCLK 772 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
777 MX8MM_IOMUXC_SD1_DATA6 773 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
778 MX8MM_IOMUXC_SAI3_RXFS 774 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
779 MX8MM_IOMUXC_SPDIF_EXT 775 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
780 MX8MM_IOMUXC_SPDIF_RX_ 776 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
781 MX8MM_IOMUXC_SPDIF_TX_ 777 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
782 >; 778 >;
783 }; 779 };
784 780
785 pinctrl_accel: accelgrp { 781 pinctrl_accel: accelgrp {
786 fsl,pins = < 782 fsl,pins = <
787 MX8MM_IOMUXC_GPIO1_IO1 783 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
788 >; 784 >;
789 }; 785 };
790 786
791 pinctrl_fec1: fec1grp { 787 pinctrl_fec1: fec1grp {
792 fsl,pins = < 788 fsl,pins = <
793 MX8MM_IOMUXC_ENET_MDC_ 789 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
794 MX8MM_IOMUXC_ENET_MDIO 790 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
795 MX8MM_IOMUXC_ENET_TD3_ 791 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
796 MX8MM_IOMUXC_ENET_TD2_ 792 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
797 MX8MM_IOMUXC_ENET_TD1_ 793 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
798 MX8MM_IOMUXC_ENET_TD0_ 794 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
799 MX8MM_IOMUXC_ENET_RD3_ 795 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
800 MX8MM_IOMUXC_ENET_RD2_ 796 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
801 MX8MM_IOMUXC_ENET_RD1_ 797 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
802 MX8MM_IOMUXC_ENET_RD0_ 798 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
803 MX8MM_IOMUXC_ENET_TXC_ 799 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
804 MX8MM_IOMUXC_ENET_RXC_ 800 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
805 MX8MM_IOMUXC_ENET_RX_C 801 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
806 MX8MM_IOMUXC_ENET_TX_C 802 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
807 MX8MM_IOMUXC_GPIO1_IO1 803 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
808 MX8MM_IOMUXC_GPIO1_IO1 804 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
809 >; 805 >;
810 }; 806 };
811 807
812 pinctrl_gsc: gscgrp { 808 pinctrl_gsc: gscgrp {
813 fsl,pins = < 809 fsl,pins = <
814 MX8MM_IOMUXC_SD1_DATA4 810 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
815 >; 811 >;
816 }; 812 };
817 813
818 pinctrl_i2c1: i2c1grp { 814 pinctrl_i2c1: i2c1grp {
819 fsl,pins = < 815 fsl,pins = <
820 MX8MM_IOMUXC_I2C1_SCL_ 816 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
821 MX8MM_IOMUXC_I2C1_SDA_ 817 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
822 >; 818 >;
823 }; 819 };
824 820
825 pinctrl_i2c1_gpio: i2c1gpiogrp { 821 pinctrl_i2c1_gpio: i2c1gpiogrp {
826 fsl,pins = < 822 fsl,pins = <
827 MX8MM_IOMUXC_I2C1_SCL_ 823 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
828 MX8MM_IOMUXC_I2C1_SDA_ 824 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
829 >; 825 >;
830 }; 826 };
831 827
832 pinctrl_i2c2: i2c2grp { 828 pinctrl_i2c2: i2c2grp {
833 fsl,pins = < 829 fsl,pins = <
834 MX8MM_IOMUXC_I2C2_SCL_ 830 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
835 MX8MM_IOMUXC_I2C2_SDA_ 831 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
836 >; 832 >;
837 }; 833 };
838 834
839 pinctrl_i2c2_gpio: i2c2gpiogrp { 835 pinctrl_i2c2_gpio: i2c2gpiogrp {
840 fsl,pins = < 836 fsl,pins = <
841 MX8MM_IOMUXC_I2C2_SCL_ 837 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
842 MX8MM_IOMUXC_I2C2_SDA_ 838 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
843 >; 839 >;
844 }; 840 };
845 841
846 pinctrl_i2c3: i2c3grp { 842 pinctrl_i2c3: i2c3grp {
847 fsl,pins = < 843 fsl,pins = <
848 MX8MM_IOMUXC_I2C3_SCL_ 844 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
849 MX8MM_IOMUXC_I2C3_SDA_ 845 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
850 >; 846 >;
851 }; 847 };
852 848
853 pinctrl_i2c3_gpio: i2c3gpiogrp { 849 pinctrl_i2c3_gpio: i2c3gpiogrp {
854 fsl,pins = < 850 fsl,pins = <
855 MX8MM_IOMUXC_I2C3_SCL_ 851 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
856 MX8MM_IOMUXC_I2C3_SDA_ 852 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
857 >; 853 >;
858 }; 854 };
859 855
860 pinctrl_i2c4: i2c4grp { 856 pinctrl_i2c4: i2c4grp {
861 fsl,pins = < 857 fsl,pins = <
862 MX8MM_IOMUXC_I2C4_SCL_ 858 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
863 MX8MM_IOMUXC_I2C4_SDA_ 859 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
864 >; 860 >;
865 }; 861 };
866 862
867 pinctrl_i2c4_gpio: i2c4gpiogrp { 863 pinctrl_i2c4_gpio: i2c4gpiogrp {
868 fsl,pins = < 864 fsl,pins = <
869 MX8MM_IOMUXC_I2C4_SCL_ 865 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
870 MX8MM_IOMUXC_I2C4_SDA_ 866 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
871 >; 867 >;
872 }; 868 };
873 869
874 pinctrl_gpio_leds: gpioledgrp { 870 pinctrl_gpio_leds: gpioledgrp {
875 fsl,pins = < 871 fsl,pins = <
876 MX8MM_IOMUXC_SAI5_RXD0 872 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
877 MX8MM_IOMUXC_SAI5_RXD2 873 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
878 MX8MM_IOMUXC_SAI5_RXD1 874 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
879 MX8MM_IOMUXC_SAI5_RXC_ 875 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
880 MX8MM_IOMUXC_SAI5_MCLK 876 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
881 >; 877 >;
882 }; 878 };
883 879
884 pinctrl_pcie0: pciegrp { 880 pinctrl_pcie0: pciegrp {
885 fsl,pins = < 881 fsl,pins = <
886 MX8MM_IOMUXC_SAI1_RXD3 882 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
887 >; 883 >;
888 }; 884 };
889 885
890 pinctrl_pmic: pmicgrp { 886 pinctrl_pmic: pmicgrp {
891 fsl,pins = < 887 fsl,pins = <
892 MX8MM_IOMUXC_NAND_DATA 888 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
893 >; 889 >;
894 }; 890 };
895 891
896 pinctrl_pps: ppsgrp { 892 pinctrl_pps: ppsgrp {
897 fsl,pins = < 893 fsl,pins = <
898 MX8MM_IOMUXC_SAI5_RXD3 894 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
899 >; 895 >;
900 }; 896 };
901 897
902 pinctrl_reg_wl: regwlgrp { 898 pinctrl_reg_wl: regwlgrp {
903 fsl,pins = < 899 fsl,pins = <
904 MX8MM_IOMUXC_SD2_RESET 900 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
905 >; 901 >;
906 }; 902 };
907 903
908 pinctrl_reg_usb1: regusb1grp { 904 pinctrl_reg_usb1: regusb1grp {
909 fsl,pins = < 905 fsl,pins = <
910 MX8MM_IOMUXC_SD1_DATA5 906 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
911 >; 907 >;
912 }; 908 };
913 909
914 pinctrl_sai3: sai3grp { 910 pinctrl_sai3: sai3grp {
915 fsl,pins = < 911 fsl,pins = <
916 MX8MM_IOMUXC_SAI3_MCLK 912 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
917 MX8MM_IOMUXC_SAI3_RXD_ 913 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
918 MX8MM_IOMUXC_SAI3_TXC_ 914 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
919 MX8MM_IOMUXC_SAI3_TXD_ 915 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
920 MX8MM_IOMUXC_SAI3_TXFS 916 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
921 >; 917 >;
922 }; 918 };
923 919
924 pinctrl_spi1: spi1grp { 920 pinctrl_spi1: spi1grp {
925 fsl,pins = < 921 fsl,pins = <
926 MX8MM_IOMUXC_ECSPI1_SC 922 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
927 MX8MM_IOMUXC_ECSPI1_MO 923 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
928 MX8MM_IOMUXC_ECSPI1_MI 924 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
929 MX8MM_IOMUXC_ECSPI1_SS 925 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
930 MX8MM_IOMUXC_SD1_DATA1 926 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
931 >; 927 >;
932 }; 928 };
933 929
934 pinctrl_spi2: spi2grp { 930 pinctrl_spi2: spi2grp {
935 fsl,pins = < 931 fsl,pins = <
936 MX8MM_IOMUXC_ECSPI2_SC 932 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
937 MX8MM_IOMUXC_ECSPI2_MO 933 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
938 MX8MM_IOMUXC_ECSPI2_MI 934 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
939 MX8MM_IOMUXC_ECSPI2_SS 935 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
940 >; 936 >;
941 }; 937 };
942 938
943 pinctrl_uart1: uart1grp { 939 pinctrl_uart1: uart1grp {
944 fsl,pins = < 940 fsl,pins = <
945 MX8MM_IOMUXC_UART1_RXD 941 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
946 MX8MM_IOMUXC_UART1_TXD 942 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
947 MX8MM_IOMUXC_SAI1_TXFS 943 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
948 MX8MM_IOMUXC_SAI2_TXFS 944 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
949 >; 945 >;
950 }; 946 };
951 947
952 pinctrl_uart1_gpio: uart1gpiogrp { 948 pinctrl_uart1_gpio: uart1gpiogrp {
953 fsl,pins = < 949 fsl,pins = <
954 MX8MM_IOMUXC_SAI2_TXD0 950 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
955 MX8MM_IOMUXC_SAI2_TXC_ 951 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
956 MX8MM_IOMUXC_SAI2_RXD0 952 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
957 >; 953 >;
958 }; 954 };
959 955
960 pinctrl_uart2: uart2grp { 956 pinctrl_uart2: uart2grp {
961 fsl,pins = < 957 fsl,pins = <
962 MX8MM_IOMUXC_UART2_RXD 958 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
963 MX8MM_IOMUXC_UART2_TXD 959 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
964 >; 960 >;
965 }; 961 };
966 962
967 pinctrl_uart3_gpio: uart3_gpiogrp { 963 pinctrl_uart3_gpio: uart3_gpiogrp {
968 fsl,pins = < 964 fsl,pins = <
969 MX8MM_IOMUXC_SD2_CD_B_ 965 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
970 >; 966 >;
971 }; 967 };
972 968
973 pinctrl_uart3: uart3grp { 969 pinctrl_uart3: uart3grp {
974 fsl,pins = < 970 fsl,pins = <
975 MX8MM_IOMUXC_UART3_RXD 971 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
976 MX8MM_IOMUXC_UART3_TXD 972 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
977 MX8MM_IOMUXC_SD1_CLK_G 973 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
978 MX8MM_IOMUXC_SD1_CMD_G 974 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
979 >; 975 >;
980 }; 976 };
981 977
982 pinctrl_uart4: uart4grp { 978 pinctrl_uart4: uart4grp {
983 fsl,pins = < 979 fsl,pins = <
984 MX8MM_IOMUXC_UART4_RXD 980 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
985 MX8MM_IOMUXC_UART4_TXD 981 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
986 MX8MM_IOMUXC_SAI1_RXC_ 982 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
987 MX8MM_IOMUXC_SAI1_RXD0 983 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
988 MX8MM_IOMUXC_SAI1_RXD1 984 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
989 MX8MM_IOMUXC_SAI1_RXD2 985 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
990 MX8MM_IOMUXC_SAI1_RXD4 986 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
991 MX8MM_IOMUXC_SAI1_RXD5 987 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
992 MX8MM_IOMUXC_SAI1_RXFS 988 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
993 MX8MM_IOMUXC_GPIO1_IO0 989 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
994 >; 990 >;
995 }; 991 };
996 992
997 pinctrl_usdhc2: usdhc2grp { 993 pinctrl_usdhc2: usdhc2grp {
998 fsl,pins = < 994 fsl,pins = <
999 MX8MM_IOMUXC_SD2_CLK_U 995 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1000 MX8MM_IOMUXC_SD2_CMD_ 996 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1001 MX8MM_IOMUXC_SD2_DATA 997 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1002 MX8MM_IOMUXC_SD2_DATA 998 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1003 MX8MM_IOMUXC_SD2_DATA 999 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1004 MX8MM_IOMUXC_SD2_DATA 1000 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1005 >; 1001 >;
1006 }; 1002 };
1007 1003
1008 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1004 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1009 fsl,pins = < 1005 fsl,pins = <
1010 MX8MM_IOMUXC_SD2_CLK_ 1006 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1011 MX8MM_IOMUXC_SD2_CMD_ 1007 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1012 MX8MM_IOMUXC_SD2_DATA 1008 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1013 MX8MM_IOMUXC_SD2_DATA 1009 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1014 MX8MM_IOMUXC_SD2_DATA 1010 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1015 MX8MM_IOMUXC_SD2_DATA 1011 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1016 >; 1012 >;
1017 }; 1013 };
1018 1014
1019 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1015 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1020 fsl,pins = < 1016 fsl,pins = <
1021 MX8MM_IOMUXC_SD2_CLK_ 1017 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1022 MX8MM_IOMUXC_SD2_CMD_ 1018 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1023 MX8MM_IOMUXC_SD2_DATA 1019 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1024 MX8MM_IOMUXC_SD2_DATA 1020 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1025 MX8MM_IOMUXC_SD2_DATA 1021 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1026 MX8MM_IOMUXC_SD2_DATA 1022 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1027 >; 1023 >;
1028 }; 1024 };
1029 1025
1030 pinctrl_usdhc3: usdhc3grp { 1026 pinctrl_usdhc3: usdhc3grp {
1031 fsl,pins = < 1027 fsl,pins = <
1032 MX8MM_IOMUXC_NAND_WE_ 1028 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1033 MX8MM_IOMUXC_NAND_WP_ 1029 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1034 MX8MM_IOMUXC_NAND_DAT 1030 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1035 MX8MM_IOMUXC_NAND_DAT 1031 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1036 MX8MM_IOMUXC_NAND_DAT 1032 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1037 MX8MM_IOMUXC_NAND_DAT 1033 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1038 MX8MM_IOMUXC_NAND_RE_ 1034 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1039 MX8MM_IOMUXC_NAND_CE2 1035 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1040 MX8MM_IOMUXC_NAND_CE3 1036 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1041 MX8MM_IOMUXC_NAND_CLE 1037 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1042 MX8MM_IOMUXC_NAND_CE1 1038 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1043 >; 1039 >;
1044 }; 1040 };
1045 1041
1046 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1042 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1047 fsl,pins = < 1043 fsl,pins = <
1048 MX8MM_IOMUXC_NAND_WE_ 1044 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1049 MX8MM_IOMUXC_NAND_WP_ 1045 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1050 MX8MM_IOMUXC_NAND_DAT 1046 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1051 MX8MM_IOMUXC_NAND_DAT 1047 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1052 MX8MM_IOMUXC_NAND_DAT 1048 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1053 MX8MM_IOMUXC_NAND_DAT 1049 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1054 MX8MM_IOMUXC_NAND_RE_ 1050 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1055 MX8MM_IOMUXC_NAND_CE2 1051 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1056 MX8MM_IOMUXC_NAND_CE3 1052 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1057 MX8MM_IOMUXC_NAND_CLE 1053 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1058 MX8MM_IOMUXC_NAND_CE1 1054 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1059 >; 1055 >;
1060 }; 1056 };
1061 1057
1062 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1058 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1063 fsl,pins = < 1059 fsl,pins = <
1064 MX8MM_IOMUXC_NAND_WE_ 1060 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1065 MX8MM_IOMUXC_NAND_WP_ 1061 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1066 MX8MM_IOMUXC_NAND_DAT 1062 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1067 MX8MM_IOMUXC_NAND_DAT 1063 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1068 MX8MM_IOMUXC_NAND_DAT 1064 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1069 MX8MM_IOMUXC_NAND_DAT 1065 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1070 MX8MM_IOMUXC_NAND_RE_ 1066 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1071 MX8MM_IOMUXC_NAND_CE2 1067 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1072 MX8MM_IOMUXC_NAND_CE3 1068 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1073 MX8MM_IOMUXC_NAND_CLE 1069 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1074 MX8MM_IOMUXC_NAND_CE1 1070 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1075 >; 1071 >;
1076 }; 1072 };
1077 1073
1078 pinctrl_wdog: wdoggrp { 1074 pinctrl_wdog: wdoggrp {
1079 fsl,pins = < 1075 fsl,pins = <
1080 MX8MM_IOMUXC_GPIO1_IO 1076 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1081 >; 1077 >;
1082 }; 1078 };
1083 }; 1079 };
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