1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12
13 #include "imx8mm.dtsi"
14
15 / {
16 model = "Gateworks Venice GW7903 i.MX8
17 compatible = "gw,imx8mm-gw7903", "fsl,
18
19 aliases {
20 ethernet0 = &fec1;
21 usb0 = &usbotg1;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x8000
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35
36 key-user-pb {
37 label = "user_pb";
38 gpios = <&gpio 2 GPIO_
39 linux,code = <BTN_0>;
40 };
41
42 key-user-pb1x {
43 label = "user_pb1x";
44 linux,code = <BTN_1>;
45 interrupt-parent = <&g
46 interrupts = <0>;
47 };
48
49 key-erased {
50 label = "key_erased";
51 linux,code = <BTN_2>;
52 interrupt-parent = <&g
53 interrupts = <1>;
54 };
55
56 key-eeprom-wp {
57 label = "eeprom_wp";
58 linux,code = <BTN_3>;
59 interrupt-parent = <&g
60 interrupts = <2>;
61 };
62
63 switch-hold {
64 label = "switch_hold";
65 linux,code = <BTN_5>;
66 interrupt-parent = <&g
67 interrupts = <7>;
68 };
69 };
70
71 led-controller {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_led
75
76 led-0 {
77 function = LED_FUNCTIO
78 color = <LED_COLOR_ID_
79 label = "led01_red";
80 gpios = <&gpio5 5 GPIO
81 default-state = "off";
82 };
83
84 led-1 {
85 function = LED_FUNCTIO
86 color = <LED_COLOR_ID_
87 label = "led01_grn";
88 gpios = <&gpio4 30 GPI
89 default-state = "off";
90 };
91
92 led-2 {
93 function = LED_FUNCTIO
94 color = <LED_COLOR_ID_
95 label = "led02_red";
96 gpios = <&gpio5 2 GPIO
97 default-state = "off";
98 };
99
100 led-3 {
101 function = LED_FUNCTIO
102 color = <LED_COLOR_ID_
103 label = "led02_grn";
104 gpios = <&gpio1 14 GPI
105 default-state = "off";
106 };
107
108 led-4 {
109 function = LED_FUNCTIO
110 color = <LED_COLOR_ID_
111 label = "led03_red";
112 gpios = <&gpio1 9 GPIO
113 default-state = "off";
114 };
115
116 led-5 {
117 function = LED_FUNCTIO
118 color = <LED_COLOR_ID_
119 label = "led03_grn";
120 gpios = <&gpio5 3 GPIO
121 default-state = "off";
122 };
123
124 led-6 {
125 function = LED_FUNCTIO
126 color = <LED_COLOR_ID_
127 label = "led04_red";
128 gpios = <&gpio4 29 GPI
129 default-state = "off";
130 };
131
132 led-7 {
133 function = LED_FUNCTIO
134 color = <LED_COLOR_ID_
135 label = "led04_grn";
136 gpios = <&gpio4 28 GPI
137 default-state = "off";
138 };
139
140 led-8 {
141 function = LED_FUNCTIO
142 color = <LED_COLOR_ID_
143 label = "led05_red";
144 gpios = <&gpio1 13 GPI
145 default-state = "off";
146 };
147
148 led-9 {
149 function = LED_FUNCTIO
150 color = <LED_COLOR_ID_
151 label = "led05_grn";
152 gpios = <&gpio4 31 GPI
153 default-state = "off";
154 };
155
156 led-a {
157 function = LED_FUNCTIO
158 color = <LED_COLOR_ID_
159 label = "led06_red";
160 gpios = <&gpio5 4 GPIO
161 default-state = "off";
162 };
163
164 led-b {
165 function = LED_FUNCTIO
166 color = <LED_COLOR_ID_
167 label = "led06_grn";
168 gpios = <&gpio1 8 GPIO
169 default-state = "off";
170 };
171 };
172
173 pcie0_refclk: pcie0-refclk {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <100000000>;
177 };
178
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed"
181 regulator-name = "3P3V";
182 regulator-min-microvolt = <330
183 regulator-max-microvolt = <330
184 regulator-always-on;
185 };
186 };
187
188 &A53_0 {
189 cpu-supply = <&buck2>;
190 };
191
192 &A53_1 {
193 cpu-supply = <&buck2>;
194 };
195
196 &A53_2 {
197 cpu-supply = <&buck2>;
198 };
199
200 &A53_3 {
201 cpu-supply = <&buck2>;
202 };
203
204 &ddrc {
205 operating-points-v2 = <&ddrc_opp_table
206
207 ddrc_opp_table: opp-table {
208 compatible = "operating-points
209
210 opp-25000000 {
211 opp-hz = /bits/ 64 <25
212 };
213
214 opp-100000000 {
215 opp-hz = /bits/ 64 <10
216 };
217
218 opp-750000000 {
219 opp-hz = /bits/ 64 <75
220 };
221 };
222 };
223
224 &fec1 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_fec1>;
227 phy-mode = "rgmii-id";
228 phy-handle = <ðphy0>;
229 local-mac-address = [00 00 00 00 00 00
230 status = "okay";
231
232 mdio {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 ethphy0: ethernet-phy@0 {
237 compatible = "ethernet
238 reg = <0>;
239 rx-internal-delay-ps =
240 tx-internal-delay-ps =
241 };
242 };
243 };
244
245 &gpio1 {
246 gpio-line-names = "", "", "", "", "",
247 "", "", "rs422_en#", "rs485_en
248 "", "", "", "", "", "", "", ""
249 "", "", "", "", "", "", "", ""
250 };
251
252 &gpio2 {
253 gpio-line-names = "dig2_in", "dig2_out
254 "dig1_out#", "dig1_in", "", ""
255 "", "", "", "", "", "", "", ""
256 "", "", "", "", "", "", "", ""
257 };
258
259 &gpio5 {
260 gpio-line-names = "", "", "", "", "",
261 "sim2_det#", "sim2_sel", "", "
262 "", "", "", "", "", "", "", ""
263 "", "", "", "", "", "", "", ""
264 };
265
266 &i2c1 {
267 clock-frequency = <100000>;
268 pinctrl-names = "default", "gpio";
269 pinctrl-0 = <&pinctrl_i2c1>;
270 pinctrl-1 = <&pinctrl_i2c1_gpio>;
271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI
272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI
273 status = "okay";
274
275 gsc: gsc@20 {
276 compatible = "gw,gsc";
277 reg = <0x20>;
278 pinctrl-0 = <&pinctrl_gsc>;
279 interrupt-parent = <&gpio4>;
280 interrupts = <26 IRQ_TYPE_EDGE
281 interrupt-controller;
282 #interrupt-cells = <1>;
283 #address-cells = <1>;
284 #size-cells = <0>;
285
286 adc {
287 compatible = "gw,gsc-a
288 #address-cells = <1>;
289 #size-cells = <0>;
290
291 channel@6 {
292 gw,mode = <0>;
293 reg = <0x06>;
294 label = "temp"
295 };
296
297 channel@8 {
298 gw,mode = <3>;
299 reg = <0x08>;
300 label = "vdd_b
301 };
302
303 channel@82 {
304 gw,mode = <2>;
305 reg = <0x82>;
306 label = "vin";
307 gw,voltage-div
308 gw,voltage-off
309 };
310
311 channel@84 {
312 gw,mode = <2>;
313 reg = <0x84>;
314 label = "vdd_5
315 gw,voltage-div
316 };
317
318 channel@86 {
319 gw,mode = <2>;
320 reg = <0x86>;
321 label = "vdd_3
322 gw,voltage-div
323 };
324
325 channel@88 {
326 gw,mode = <2>;
327 reg = <0x88>;
328 label = "vdd_0
329 };
330
331 channel@8c {
332 gw,mode = <2>;
333 reg = <0x8c>;
334 label = "vdd_s
335 };
336
337 channel@8e {
338 gw,mode = <2>;
339 reg = <0x8e>;
340 label = "vdd_a
341 };
342
343 channel@90 {
344 gw,mode = <2>;
345 reg = <0x90>;
346 label = "vdd_1
347 };
348
349 channel@92 {
350 gw,mode = <2>;
351 reg = <0x92>;
352 label = "vdd_d
353 };
354
355 channel@a2 {
356 gw,mode = <2>;
357 reg = <0xa2>;
358 label = "vdd_g
359 gw,voltage-div
360 };
361 };
362 };
363
364 gpio: gpio@23 {
365 compatible = "nxp,pca9555";
366 reg = <0x23>;
367 gpio-controller;
368 #gpio-cells = <2>;
369 interrupt-parent = <&gsc>;
370 interrupts = <4>;
371 };
372
373 eeprom@50 {
374 compatible = "atmel,24c02";
375 reg = <0x50>;
376 pagesize = <16>;
377 };
378
379 eeprom@51 {
380 compatible = "atmel,24c02";
381 reg = <0x51>;
382 pagesize = <16>;
383 };
384
385 eeprom@52 {
386 compatible = "atmel,24c02";
387 reg = <0x52>;
388 pagesize = <16>;
389 };
390
391 eeprom@53 {
392 compatible = "atmel,24c02";
393 reg = <0x53>;
394 pagesize = <16>;
395 };
396
397 rtc@68 {
398 compatible = "dallas,ds1672";
399 reg = <0x68>;
400 };
401 };
402
403 &i2c2 {
404 clock-frequency = <400000>;
405 pinctrl-names = "default", "gpio";
406 pinctrl-0 = <&pinctrl_i2c2>;
407 pinctrl-1 = <&pinctrl_i2c2_gpio>;
408 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI
409 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI
410 status = "okay";
411
412 pmic@4b {
413 compatible = "rohm,bd71847";
414 reg = <0x4b>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pmic>;
417 interrupt-parent = <&gpio3>;
418 interrupts = <8 IRQ_TYPE_LEVEL
419 rohm,reset-snvs-powered;
420 #clock-cells = <0>;
421 clocks = <&osc_32k>;
422 clock-output-names = "clk-32k-
423
424 regulators {
425 /* vdd_soc: 0.805-0.90
426 BUCK1 {
427 regulator-name
428 regulator-min-
429 regulator-max-
430 regulator-boot
431 regulator-alwa
432 regulator-ramp
433 };
434
435 /* vdd_arm: 0.805-1.0V
436 buck2: BUCK2 {
437 regulator-name
438 regulator-min-
439 regulator-max-
440 regulator-boot
441 regulator-alwa
442 regulator-ramp
443 rohm,dvs-run-v
444 rohm,dvs-idle-
445 };
446
447 /* vdd_0p9: 0.805-1.0V
448 BUCK3 {
449 regulator-name
450 regulator-min-
451 regulator-max-
452 regulator-boot
453 regulator-alwa
454 };
455
456 /* vdd_3p3 */
457 BUCK4 {
458 regulator-name
459 regulator-min-
460 regulator-max-
461 regulator-boot
462 regulator-alwa
463 };
464
465 /* vdd_1p8 */
466 BUCK5 {
467 regulator-name
468 regulator-min-
469 regulator-max-
470 regulator-boot
471 regulator-alwa
472 };
473
474 /* vdd_dram */
475 BUCK6 {
476 regulator-name
477 regulator-min-
478 regulator-max-
479 regulator-boot
480 regulator-alwa
481 };
482
483 /* nvcc_snvs_1p8 */
484 LDO1 {
485 regulator-name
486 regulator-min-
487 regulator-max-
488 regulator-boot
489 regulator-alwa
490 };
491
492 /* vdd_snvs_0p8 */
493 LDO2 {
494 regulator-name
495 regulator-min-
496 regulator-max-
497 regulator-boot
498 regulator-alwa
499 };
500
501 /* vdda_1p8 */
502 LDO3 {
503 regulator-name
504 regulator-min-
505 regulator-max-
506 regulator-boot
507 regulator-alwa
508 };
509
510 LDO4 {
511 regulator-name
512 regulator-min-
513 regulator-max-
514 regulator-boot
515 regulator-alwa
516 };
517
518 LDO6 {
519 regulator-name
520 regulator-min-
521 regulator-max-
522 regulator-boot
523 regulator-alwa
524 };
525 };
526 };
527 };
528
529 &i2c3 {
530 clock-frequency = <400000>;
531 pinctrl-names = "default", "gpio";
532 pinctrl-0 = <&pinctrl_i2c3>;
533 pinctrl-1 = <&pinctrl_i2c3_gpio>;
534 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI
535 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI
536 status = "okay";
537
538 accelerometer@19 {
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_accel>;
541 compatible = "st,lis2de12";
542 reg = <0x19>;
543 st,drdy-int-pin = <1>;
544 interrupt-parent = <&gpio1>;
545 interrupts = <15 IRQ_TYPE_LEVE
546 };
547 };
548
549 &pcie_phy {
550 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL
551 fsl,clkreq-unsupported;
552 clocks = <&pcie0_refclk>;
553 clock-names = "ref";
554 status = "okay";
555 };
556
557 &pcie0 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_pcie0>;
560 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LO
561 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
562 <&clk IMX8MM_CLK_PCIE1_AUX>;
563 assigned-clocks = <&clk IMX8MM_CLK_PCI
564 <&clk IMX8MM_CLK_PCI
565 assigned-clock-rates = <10000000>, <25
566 assigned-clock-parents = <&clk IMX8MM_
567 <&clk IMX8MM_
568 status = "okay";
569 };
570
571 &disp_blk_ctrl {
572 status = "disabled";
573 };
574
575 &pgc_mipi {
576 status = "disabled";
577 };
578
579 /* off-board RS232/RS485/RS422 */
580 &uart1 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart1>;
583 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>
584 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>
585 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>
586 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>
587 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW
588 status = "okay";
589 };
590
591 /* console */
592 &uart2 {
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_uart2>;
595 status = "okay";
596 };
597
598 &usbotg1 {
599 dr_mode = "host";
600 disable-over-current;
601 status = "okay";
602 };
603
604 /* microSD */
605 &usdhc2 {
606 pinctrl-names = "default", "state_100m
607 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
608 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
611 bus-width = <4>;
612 vmmc-supply = <®_3p3v>;
613 status = "okay";
614 };
615
616 /* eMMC */
617 &usdhc3 {
618 pinctrl-names = "default", "state_100m
619 pinctrl-0 = <&pinctrl_usdhc3>;
620 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
621 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
622 bus-width = <8>;
623 non-removable;
624 status = "okay";
625 };
626
627 &wdog1 {
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_wdog>;
630 fsl,ext-reset-output;
631 status = "okay";
632 };
633
634 &iomuxc {
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_hog>;
637
638 pinctrl_hog: hoggrp {
639 fsl,pins = <
640 MX8MM_IOMUXC_GPIO1_IO1
641 MX8MM_IOMUXC_GPIO1_IO1
642 MX8MM_IOMUXC_GPIO1_IO1
643 MX8MM_IOMUXC_SD1_DATA7
644 MX8MM_IOMUXC_SD1_DATA6
645 MX8MM_IOMUXC_SD1_DATA4
646 MX8MM_IOMUXC_SD1_DATA0
647 MX8MM_IOMUXC_SD1_CLK_G
648 MX8MM_IOMUXC_SD1_CMD_G
649 MX8MM_IOMUXC_ECSPI1_MO
650 MX8MM_IOMUXC_ECSPI1_MI
651 MX8MM_IOMUXC_ECSPI1_SS
652 MX8MM_IOMUXC_ECSPI2_MI
653 >;
654 };
655
656 pinctrl_accel: accelgrp {
657 fsl,pins = <
658 MX8MM_IOMUXC_GPIO1_IO1
659 >;
660 };
661
662 pinctrl_fec1: fec1grp {
663 fsl,pins = <
664 MX8MM_IOMUXC_ENET_MDC_
665 MX8MM_IOMUXC_ENET_MDIO
666 MX8MM_IOMUXC_ENET_TD3_
667 MX8MM_IOMUXC_ENET_TD2_
668 MX8MM_IOMUXC_ENET_TD1_
669 MX8MM_IOMUXC_ENET_TD0_
670 MX8MM_IOMUXC_ENET_RD3_
671 MX8MM_IOMUXC_ENET_RD2_
672 MX8MM_IOMUXC_ENET_RD1_
673 MX8MM_IOMUXC_ENET_RD0_
674 MX8MM_IOMUXC_ENET_TXC_
675 MX8MM_IOMUXC_ENET_RXC_
676 MX8MM_IOMUXC_ENET_RX_C
677 MX8MM_IOMUXC_ENET_TX_C
678 MX8MM_IOMUXC_SAI2_TXFS
679 MX8MM_IOMUXC_SAI2_TXC_
680 >;
681 };
682
683 pinctrl_gsc: gscgrp {
684 fsl,pins = <
685 MX8MM_IOMUXC_SAI2_TXD0
686 >;
687 };
688
689 pinctrl_i2c1: i2c1grp {
690 fsl,pins = <
691 MX8MM_IOMUXC_I2C1_SCL_
692 MX8MM_IOMUXC_I2C1_SDA_
693 >;
694 };
695
696 pinctrl_i2c1_gpio: i2c1gpiogrp {
697 fsl,pins = <
698 MX8MM_IOMUXC_I2C1_SCL_
699 MX8MM_IOMUXC_I2C1_SDA_
700 >;
701 };
702
703 pinctrl_i2c2: i2c2grp {
704 fsl,pins = <
705 MX8MM_IOMUXC_I2C2_SCL_
706 MX8MM_IOMUXC_I2C2_SDA_
707 >;
708 };
709
710 pinctrl_i2c2_gpio: i2c2gpiogrp {
711 fsl,pins = <
712 MX8MM_IOMUXC_I2C2_SCL_
713 MX8MM_IOMUXC_I2C2_SDA_
714 >;
715 };
716
717 pinctrl_i2c3: i2c3grp {
718 fsl,pins = <
719 MX8MM_IOMUXC_I2C3_SCL_
720 MX8MM_IOMUXC_I2C3_SDA_
721 >;
722 };
723
724 pinctrl_i2c3_gpio: i2c3gpiogrp {
725 fsl,pins = <
726 MX8MM_IOMUXC_I2C3_SCL_
727 MX8MM_IOMUXC_I2C3_SDA_
728 >;
729 };
730
731 pinctrl_gpio_leds: gpioledgrp {
732 fsl,pins = <
733 MX8MM_IOMUXC_SPDIF_EXT
734 MX8MM_IOMUXC_SAI3_RXD_
735 MX8MM_IOMUXC_SAI3_MCLK
736 MX8MM_IOMUXC_GPIO1_IO1
737 MX8MM_IOMUXC_GPIO1_IO0
738 MX8MM_IOMUXC_SPDIF_TX_
739 MX8MM_IOMUXC_SAI3_RXC_
740 MX8MM_IOMUXC_SAI3_RXFS
741 MX8MM_IOMUXC_GPIO1_IO1
742 MX8MM_IOMUXC_SAI3_TXFS
743 MX8MM_IOMUXC_SPDIF_RX_
744 MX8MM_IOMUXC_GPIO1_IO0
745 >;
746 };
747
748 pinctrl_pcie0: pciegrp {
749 fsl,pins = <
750 MX8MM_IOMUXC_ECSPI2_MO
751 >;
752 };
753
754 pinctrl_pmic: pmicgrp {
755 fsl,pins = <
756 MX8MM_IOMUXC_NAND_DATA
757 >;
758 };
759
760 pinctrl_uart1: uart1grp {
761 fsl,pins = <
762 MX8MM_IOMUXC_UART1_RXD
763 MX8MM_IOMUXC_UART1_TXD
764 MX8MM_IOMUXC_GPIO1_IO0
765 MX8MM_IOMUXC_GPIO1_IO0
766 MX8MM_IOMUXC_GPIO1_IO0
767 MX8MM_IOMUXC_GPIO1_IO0
768 MX8MM_IOMUXC_SAI5_RXD3
769 >;
770 };
771
772 pinctrl_uart2: uart2grp {
773 fsl,pins = <
774 MX8MM_IOMUXC_UART2_RXD
775 MX8MM_IOMUXC_UART2_TXD
776 >;
777 };
778
779 pinctrl_usdhc2: usdhc2grp {
780 fsl,pins = <
781 MX8MM_IOMUXC_SD2_CLK_U
782 MX8MM_IOMUXC_SD2_CMD_U
783 MX8MM_IOMUXC_SD2_DATA0
784 MX8MM_IOMUXC_SD2_DATA1
785 MX8MM_IOMUXC_SD2_DATA2
786 MX8MM_IOMUXC_SD2_DATA3
787 >;
788 };
789
790 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
791 fsl,pins = <
792 MX8MM_IOMUXC_SD2_CLK_U
793 MX8MM_IOMUXC_SD2_CMD_U
794 MX8MM_IOMUXC_SD2_DATA0
795 MX8MM_IOMUXC_SD2_DATA1
796 MX8MM_IOMUXC_SD2_DATA2
797 MX8MM_IOMUXC_SD2_DATA3
798 >;
799 };
800
801 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
802 fsl,pins = <
803 MX8MM_IOMUXC_SD2_CLK_U
804 MX8MM_IOMUXC_SD2_CMD_U
805 MX8MM_IOMUXC_SD2_DATA0
806 MX8MM_IOMUXC_SD2_DATA1
807 MX8MM_IOMUXC_SD2_DATA2
808 MX8MM_IOMUXC_SD2_DATA3
809 >;
810 };
811
812 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
813 fsl,pins = <
814 MX8MM_IOMUXC_SD2_CD_B_
815 MX8MM_IOMUXC_GPIO1_IO0
816 >;
817 };
818
819 pinctrl_usdhc3: usdhc3grp {
820 fsl,pins = <
821 MX8MM_IOMUXC_NAND_WE_B
822 MX8MM_IOMUXC_NAND_WP_B
823 MX8MM_IOMUXC_NAND_DATA
824 MX8MM_IOMUXC_NAND_DATA
825 MX8MM_IOMUXC_NAND_DATA
826 MX8MM_IOMUXC_NAND_DATA
827 MX8MM_IOMUXC_NAND_RE_B
828 MX8MM_IOMUXC_NAND_CE2_
829 MX8MM_IOMUXC_NAND_CE3_
830 MX8MM_IOMUXC_NAND_CLE_
831 MX8MM_IOMUXC_NAND_CE1_
832 >;
833 };
834
835 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr
836 fsl,pins = <
837 MX8MM_IOMUXC_NAND_WE_B
838 MX8MM_IOMUXC_NAND_WP_B
839 MX8MM_IOMUXC_NAND_DATA
840 MX8MM_IOMUXC_NAND_DATA
841 MX8MM_IOMUXC_NAND_DATA
842 MX8MM_IOMUXC_NAND_DATA
843 MX8MM_IOMUXC_NAND_RE_B
844 MX8MM_IOMUXC_NAND_CE2_
845 MX8MM_IOMUXC_NAND_CE3_
846 MX8MM_IOMUXC_NAND_CLE_
847 MX8MM_IOMUXC_NAND_CE1_
848 >;
849 };
850
851 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr
852 fsl,pins = <
853 MX8MM_IOMUXC_NAND_WE_B
854 MX8MM_IOMUXC_NAND_WP_B
855 MX8MM_IOMUXC_NAND_DATA
856 MX8MM_IOMUXC_NAND_DATA
857 MX8MM_IOMUXC_NAND_DATA
858 MX8MM_IOMUXC_NAND_DATA
859 MX8MM_IOMUXC_NAND_RE_B
860 MX8MM_IOMUXC_NAND_CE2_
861 MX8MM_IOMUXC_NAND_CE3_
862 MX8MM_IOMUXC_NAND_CLE_
863 MX8MM_IOMUXC_NAND_CE1_
864 >;
865 };
866
867 pinctrl_wdog: wdoggrp {
868 fsl,pins = <
869 MX8MM_IOMUXC_GPIO1_IO0
870 >;
871 };
872 };
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