1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Gateworks Corporation 3 * Copyright 2022 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 12
13 #include "imx8mm.dtsi" 13 #include "imx8mm.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7903 i.MX8 16 model = "Gateworks Venice GW7903 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7903", "fsl, 17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
18 18
19 aliases { 19 aliases {
20 ethernet0 = &fec1; 20 ethernet0 = &fec1;
21 usb0 = &usbotg1; 21 usb0 = &usbotg1;
22 }; 22 };
23 23
24 chosen { 24 chosen {
25 stdout-path = &uart2; 25 stdout-path = &uart2;
26 }; 26 };
27 27
28 memory@40000000 { 28 memory@40000000 {
29 device_type = "memory"; 29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x8000 30 reg = <0x0 0x40000000 0 0x80000000>;
31 }; 31 };
32 32
33 gpio-keys { 33 gpio-keys {
34 compatible = "gpio-keys"; 34 compatible = "gpio-keys";
35 35
36 key-user-pb { 36 key-user-pb {
37 label = "user_pb"; 37 label = "user_pb";
38 gpios = <&gpio 2 GPIO_ 38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
39 linux,code = <BTN_0>; 39 linux,code = <BTN_0>;
40 }; 40 };
41 41
42 key-user-pb1x { 42 key-user-pb1x {
43 label = "user_pb1x"; 43 label = "user_pb1x";
44 linux,code = <BTN_1>; 44 linux,code = <BTN_1>;
45 interrupt-parent = <&g 45 interrupt-parent = <&gsc>;
46 interrupts = <0>; 46 interrupts = <0>;
47 }; 47 };
48 48
49 key-erased { 49 key-erased {
50 label = "key_erased"; 50 label = "key_erased";
51 linux,code = <BTN_2>; 51 linux,code = <BTN_2>;
52 interrupt-parent = <&g 52 interrupt-parent = <&gsc>;
53 interrupts = <1>; 53 interrupts = <1>;
54 }; 54 };
55 55
56 key-eeprom-wp { 56 key-eeprom-wp {
57 label = "eeprom_wp"; 57 label = "eeprom_wp";
58 linux,code = <BTN_3>; 58 linux,code = <BTN_3>;
59 interrupt-parent = <&g 59 interrupt-parent = <&gsc>;
60 interrupts = <2>; 60 interrupts = <2>;
61 }; 61 };
62 62
63 switch-hold { 63 switch-hold {
64 label = "switch_hold"; 64 label = "switch_hold";
65 linux,code = <BTN_5>; 65 linux,code = <BTN_5>;
66 interrupt-parent = <&g 66 interrupt-parent = <&gsc>;
67 interrupts = <7>; 67 interrupts = <7>;
68 }; 68 };
69 }; 69 };
70 70
71 led-controller { 71 led-controller {
72 compatible = "gpio-leds"; 72 compatible = "gpio-leds";
73 pinctrl-names = "default"; 73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_led 74 pinctrl-0 = <&pinctrl_gpio_leds>;
75 75
76 led-0 { 76 led-0 {
77 function = LED_FUNCTIO 77 function = LED_FUNCTION_STATUS;
78 color = <LED_COLOR_ID_ 78 color = <LED_COLOR_ID_RED>;
79 label = "led01_red"; 79 label = "led01_red";
80 gpios = <&gpio5 5 GPIO 80 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
81 default-state = "off"; 81 default-state = "off";
82 }; 82 };
83 83
84 led-1 { 84 led-1 {
85 function = LED_FUNCTIO 85 function = LED_FUNCTION_STATUS;
86 color = <LED_COLOR_ID_ 86 color = <LED_COLOR_ID_GREEN>;
87 label = "led01_grn"; 87 label = "led01_grn";
88 gpios = <&gpio4 30 GPI 88 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
89 default-state = "off"; 89 default-state = "off";
90 }; 90 };
91 91
92 led-2 { 92 led-2 {
93 function = LED_FUNCTIO 93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_ 94 color = <LED_COLOR_ID_RED>;
95 label = "led02_red"; 95 label = "led02_red";
96 gpios = <&gpio5 2 GPIO 96 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
97 default-state = "off"; 97 default-state = "off";
98 }; 98 };
99 99
100 led-3 { 100 led-3 {
101 function = LED_FUNCTIO 101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_ 102 color = <LED_COLOR_ID_GREEN>;
103 label = "led02_grn"; 103 label = "led02_grn";
104 gpios = <&gpio1 14 GPI 104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
105 default-state = "off"; 105 default-state = "off";
106 }; 106 };
107 107
108 led-4 { 108 led-4 {
109 function = LED_FUNCTIO 109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_ 110 color = <LED_COLOR_ID_RED>;
111 label = "led03_red"; 111 label = "led03_red";
112 gpios = <&gpio1 9 GPIO 112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
113 default-state = "off"; 113 default-state = "off";
114 }; 114 };
115 115
116 led-5 { 116 led-5 {
117 function = LED_FUNCTIO 117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_ 118 color = <LED_COLOR_ID_GREEN>;
119 label = "led03_grn"; 119 label = "led03_grn";
120 gpios = <&gpio5 3 GPIO 120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
121 default-state = "off"; 121 default-state = "off";
122 }; 122 };
123 123
124 led-6 { 124 led-6 {
125 function = LED_FUNCTIO 125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_ 126 color = <LED_COLOR_ID_RED>;
127 label = "led04_red"; 127 label = "led04_red";
128 gpios = <&gpio4 29 GPI 128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
129 default-state = "off"; 129 default-state = "off";
130 }; 130 };
131 131
132 led-7 { 132 led-7 {
133 function = LED_FUNCTIO 133 function = LED_FUNCTION_STATUS;
134 color = <LED_COLOR_ID_ 134 color = <LED_COLOR_ID_GREEN>;
135 label = "led04_grn"; 135 label = "led04_grn";
136 gpios = <&gpio4 28 GPI 136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
137 default-state = "off"; 137 default-state = "off";
138 }; 138 };
139 139
140 led-8 { 140 led-8 {
141 function = LED_FUNCTIO 141 function = LED_FUNCTION_STATUS;
142 color = <LED_COLOR_ID_ 142 color = <LED_COLOR_ID_RED>;
143 label = "led05_red"; 143 label = "led05_red";
144 gpios = <&gpio1 13 GPI 144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
145 default-state = "off"; 145 default-state = "off";
146 }; 146 };
147 147
148 led-9 { 148 led-9 {
149 function = LED_FUNCTIO 149 function = LED_FUNCTION_STATUS;
150 color = <LED_COLOR_ID_ 150 color = <LED_COLOR_ID_GREEN>;
151 label = "led05_grn"; 151 label = "led05_grn";
152 gpios = <&gpio4 31 GPI 152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
153 default-state = "off"; 153 default-state = "off";
154 }; 154 };
155 155
156 led-a { 156 led-a {
157 function = LED_FUNCTIO 157 function = LED_FUNCTION_STATUS;
158 color = <LED_COLOR_ID_ 158 color = <LED_COLOR_ID_RED>;
159 label = "led06_red"; 159 label = "led06_red";
160 gpios = <&gpio5 4 GPIO 160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161 default-state = "off"; 161 default-state = "off";
162 }; 162 };
163 163
164 led-b { 164 led-b {
165 function = LED_FUNCTIO 165 function = LED_FUNCTION_STATUS;
166 color = <LED_COLOR_ID_ 166 color = <LED_COLOR_ID_GREEN>;
167 label = "led06_grn"; 167 label = "led06_grn";
168 gpios = <&gpio1 8 GPIO 168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
169 default-state = "off"; 169 default-state = "off";
170 }; 170 };
171 }; 171 };
172 172
173 pcie0_refclk: pcie0-refclk { 173 pcie0_refclk: pcie0-refclk {
174 compatible = "fixed-clock"; 174 compatible = "fixed-clock";
175 #clock-cells = <0>; 175 #clock-cells = <0>;
176 clock-frequency = <100000000>; 176 clock-frequency = <100000000>;
177 }; 177 };
178 178
179 reg_3p3v: regulator-3p3v { 179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed" 180 compatible = "regulator-fixed";
181 regulator-name = "3P3V"; 181 regulator-name = "3P3V";
182 regulator-min-microvolt = <330 182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <330 183 regulator-max-microvolt = <3300000>;
184 regulator-always-on; 184 regulator-always-on;
185 }; 185 };
186 }; 186 };
187 187
188 &A53_0 { 188 &A53_0 {
189 cpu-supply = <&buck2>; 189 cpu-supply = <&buck2>;
190 }; 190 };
191 191
192 &A53_1 { 192 &A53_1 {
193 cpu-supply = <&buck2>; 193 cpu-supply = <&buck2>;
194 }; 194 };
195 195
196 &A53_2 { 196 &A53_2 {
197 cpu-supply = <&buck2>; 197 cpu-supply = <&buck2>;
198 }; 198 };
199 199
200 &A53_3 { 200 &A53_3 {
201 cpu-supply = <&buck2>; 201 cpu-supply = <&buck2>;
202 }; 202 };
203 203
204 &ddrc { 204 &ddrc {
205 operating-points-v2 = <&ddrc_opp_table 205 operating-points-v2 = <&ddrc_opp_table>;
206 206
207 ddrc_opp_table: opp-table { 207 ddrc_opp_table: opp-table {
208 compatible = "operating-points 208 compatible = "operating-points-v2";
209 209
210 opp-25000000 { !! 210 opp-25M {
211 opp-hz = /bits/ 64 <25 211 opp-hz = /bits/ 64 <25000000>;
212 }; 212 };
213 213
214 opp-100000000 { !! 214 opp-100M {
215 opp-hz = /bits/ 64 <10 215 opp-hz = /bits/ 64 <100000000>;
216 }; 216 };
217 217
218 opp-750000000 { !! 218 opp-750M {
219 opp-hz = /bits/ 64 <75 219 opp-hz = /bits/ 64 <750000000>;
220 }; 220 };
221 }; 221 };
222 }; 222 };
223 223
224 &fec1 { 224 &fec1 {
225 pinctrl-names = "default"; 225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_fec1>; 226 pinctrl-0 = <&pinctrl_fec1>;
227 phy-mode = "rgmii-id"; 227 phy-mode = "rgmii-id";
228 phy-handle = <ðphy0>; 228 phy-handle = <ðphy0>;
229 local-mac-address = [00 00 00 00 00 00 229 local-mac-address = [00 00 00 00 00 00];
230 status = "okay"; 230 status = "okay";
231 231
232 mdio { 232 mdio {
233 #address-cells = <1>; 233 #address-cells = <1>;
234 #size-cells = <0>; 234 #size-cells = <0>;
235 235
236 ethphy0: ethernet-phy@0 { 236 ethphy0: ethernet-phy@0 {
237 compatible = "ethernet 237 compatible = "ethernet-phy-ieee802.3-c22";
238 reg = <0>; 238 reg = <0>;
239 rx-internal-delay-ps = 239 rx-internal-delay-ps = <2000>;
240 tx-internal-delay-ps = 240 tx-internal-delay-ps = <2500>;
241 }; 241 };
242 }; 242 };
243 }; 243 };
244 244
245 &gpio1 { 245 &gpio1 {
246 gpio-line-names = "", "", "", "", "", 246 gpio-line-names = "", "", "", "", "", "", "", "",
247 "", "", "rs422_en#", "rs485_en 247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
248 "", "", "", "", "", "", "", "" 248 "", "", "", "", "", "", "", "",
249 "", "", "", "", "", "", "", "" 249 "", "", "", "", "", "", "", "";
250 }; 250 };
251 251
252 &gpio2 { 252 &gpio2 {
253 gpio-line-names = "dig2_in", "dig2_out !! 253 gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
254 "dig1_out#", "dig1_in", "", "" 254 "dig1_out#", "dig1_in", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "" 255 "", "", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "" 256 "", "", "", "", "", "", "", "";
257 }; 257 };
258 258
259 &gpio5 { 259 &gpio5 {
260 gpio-line-names = "", "", "", "", "", 260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
261 "sim2_det#", "sim2_sel", "", " 261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
262 "", "", "", "", "", "", "", "" 262 "", "", "", "", "", "", "", "",
263 "", "", "", "", "", "", "", "" 263 "", "", "", "", "", "", "", "";
264 }; 264 };
265 265
266 &i2c1 { 266 &i2c1 {
267 clock-frequency = <100000>; 267 clock-frequency = <100000>;
268 pinctrl-names = "default", "gpio"; !! 268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>; 269 pinctrl-0 = <&pinctrl_i2c1>;
270 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
273 status = "okay"; 270 status = "okay";
274 271
275 gsc: gsc@20 { 272 gsc: gsc@20 {
276 compatible = "gw,gsc"; 273 compatible = "gw,gsc";
277 reg = <0x20>; 274 reg = <0x20>;
278 pinctrl-0 = <&pinctrl_gsc>; 275 pinctrl-0 = <&pinctrl_gsc>;
279 interrupt-parent = <&gpio4>; 276 interrupt-parent = <&gpio4>;
280 interrupts = <26 IRQ_TYPE_EDGE 277 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
281 interrupt-controller; 278 interrupt-controller;
282 #interrupt-cells = <1>; 279 #interrupt-cells = <1>;
283 #address-cells = <1>; <<
284 #size-cells = <0>; <<
285 280
286 adc { 281 adc {
287 compatible = "gw,gsc-a 282 compatible = "gw,gsc-adc";
288 #address-cells = <1>; 283 #address-cells = <1>;
289 #size-cells = <0>; 284 #size-cells = <0>;
290 285
291 channel@6 { 286 channel@6 {
292 gw,mode = <0>; 287 gw,mode = <0>;
293 reg = <0x06>; 288 reg = <0x06>;
294 label = "temp" 289 label = "temp";
295 }; 290 };
296 291
297 channel@8 { 292 channel@8 {
298 gw,mode = <3>; !! 293 gw,mode = <1>;
299 reg = <0x08>; 294 reg = <0x08>;
300 label = "vdd_b 295 label = "vdd_bat";
301 }; 296 };
302 297
303 channel@82 { 298 channel@82 {
304 gw,mode = <2>; 299 gw,mode = <2>;
305 reg = <0x82>; 300 reg = <0x82>;
306 label = "vin"; 301 label = "vin";
307 gw,voltage-div 302 gw,voltage-divider-ohms = <22100 1000>;
308 gw,voltage-off 303 gw,voltage-offset-microvolt = <700000>;
309 }; 304 };
310 305
311 channel@84 { 306 channel@84 {
312 gw,mode = <2>; 307 gw,mode = <2>;
313 reg = <0x84>; 308 reg = <0x84>;
314 label = "vdd_5 309 label = "vdd_5p0";
315 gw,voltage-div 310 gw,voltage-divider-ohms = <10000 10000>;
316 }; 311 };
317 312
318 channel@86 { 313 channel@86 {
319 gw,mode = <2>; 314 gw,mode = <2>;
320 reg = <0x86>; 315 reg = <0x86>;
321 label = "vdd_3 316 label = "vdd_3p3";
322 gw,voltage-div 317 gw,voltage-divider-ohms = <10000 10000>;
323 }; 318 };
324 319
325 channel@88 { 320 channel@88 {
326 gw,mode = <2>; 321 gw,mode = <2>;
327 reg = <0x88>; 322 reg = <0x88>;
328 label = "vdd_0 323 label = "vdd_0p9";
329 }; 324 };
330 325
331 channel@8c { 326 channel@8c {
332 gw,mode = <2>; 327 gw,mode = <2>;
333 reg = <0x8c>; 328 reg = <0x8c>;
334 label = "vdd_s 329 label = "vdd_soc";
335 }; 330 };
336 331
337 channel@8e { 332 channel@8e {
338 gw,mode = <2>; 333 gw,mode = <2>;
339 reg = <0x8e>; 334 reg = <0x8e>;
340 label = "vdd_a 335 label = "vdd_arm";
341 }; 336 };
342 337
343 channel@90 { 338 channel@90 {
344 gw,mode = <2>; 339 gw,mode = <2>;
345 reg = <0x90>; 340 reg = <0x90>;
346 label = "vdd_1 341 label = "vdd_1p8";
347 }; 342 };
348 343
349 channel@92 { 344 channel@92 {
350 gw,mode = <2>; 345 gw,mode = <2>;
351 reg = <0x92>; 346 reg = <0x92>;
352 label = "vdd_d 347 label = "vdd_dram";
353 }; 348 };
354 349
355 channel@a2 { 350 channel@a2 {
356 gw,mode = <2>; 351 gw,mode = <2>;
357 reg = <0xa2>; 352 reg = <0xa2>;
358 label = "vdd_g 353 label = "vdd_gsc";
359 gw,voltage-div 354 gw,voltage-divider-ohms = <10000 10000>;
360 }; 355 };
361 }; 356 };
362 }; 357 };
363 358
364 gpio: gpio@23 { 359 gpio: gpio@23 {
365 compatible = "nxp,pca9555"; 360 compatible = "nxp,pca9555";
366 reg = <0x23>; 361 reg = <0x23>;
367 gpio-controller; 362 gpio-controller;
368 #gpio-cells = <2>; 363 #gpio-cells = <2>;
369 interrupt-parent = <&gsc>; 364 interrupt-parent = <&gsc>;
370 interrupts = <4>; 365 interrupts = <4>;
371 }; 366 };
372 367
373 eeprom@50 { 368 eeprom@50 {
374 compatible = "atmel,24c02"; 369 compatible = "atmel,24c02";
375 reg = <0x50>; 370 reg = <0x50>;
376 pagesize = <16>; 371 pagesize = <16>;
377 }; 372 };
378 373
379 eeprom@51 { 374 eeprom@51 {
380 compatible = "atmel,24c02"; 375 compatible = "atmel,24c02";
381 reg = <0x51>; 376 reg = <0x51>;
382 pagesize = <16>; 377 pagesize = <16>;
383 }; 378 };
384 379
385 eeprom@52 { 380 eeprom@52 {
386 compatible = "atmel,24c02"; 381 compatible = "atmel,24c02";
387 reg = <0x52>; 382 reg = <0x52>;
388 pagesize = <16>; 383 pagesize = <16>;
389 }; 384 };
390 385
391 eeprom@53 { 386 eeprom@53 {
392 compatible = "atmel,24c02"; 387 compatible = "atmel,24c02";
393 reg = <0x53>; 388 reg = <0x53>;
394 pagesize = <16>; 389 pagesize = <16>;
395 }; 390 };
396 391
397 rtc@68 { 392 rtc@68 {
398 compatible = "dallas,ds1672"; 393 compatible = "dallas,ds1672";
399 reg = <0x68>; 394 reg = <0x68>;
400 }; 395 };
401 }; 396 };
402 397
403 &i2c2 { 398 &i2c2 {
404 clock-frequency = <400000>; 399 clock-frequency = <400000>;
405 pinctrl-names = "default", "gpio"; !! 400 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_i2c2>; 401 pinctrl-0 = <&pinctrl_i2c2>;
407 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
408 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
409 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
410 status = "okay"; 402 status = "okay";
411 403
412 pmic@4b { 404 pmic@4b {
413 compatible = "rohm,bd71847"; 405 compatible = "rohm,bd71847";
414 reg = <0x4b>; 406 reg = <0x4b>;
415 pinctrl-names = "default"; 407 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pmic>; 408 pinctrl-0 = <&pinctrl_pmic>;
417 interrupt-parent = <&gpio3>; 409 interrupt-parent = <&gpio3>;
418 interrupts = <8 IRQ_TYPE_LEVEL 410 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
419 rohm,reset-snvs-powered; 411 rohm,reset-snvs-powered;
420 #clock-cells = <0>; 412 #clock-cells = <0>;
421 clocks = <&osc_32k>; !! 413 clocks = <&osc_32k 0>;
422 clock-output-names = "clk-32k- 414 clock-output-names = "clk-32k-out";
423 415
424 regulators { 416 regulators {
425 /* vdd_soc: 0.805-0.90 417 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
426 BUCK1 { 418 BUCK1 {
427 regulator-name 419 regulator-name = "buck1";
428 regulator-min- 420 regulator-min-microvolt = <700000>;
429 regulator-max- 421 regulator-max-microvolt = <1300000>;
430 regulator-boot 422 regulator-boot-on;
431 regulator-alwa 423 regulator-always-on;
432 regulator-ramp 424 regulator-ramp-delay = <1250>;
433 }; 425 };
434 426
435 /* vdd_arm: 0.805-1.0V 427 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
436 buck2: BUCK2 { 428 buck2: BUCK2 {
437 regulator-name 429 regulator-name = "buck2";
438 regulator-min- 430 regulator-min-microvolt = <700000>;
439 regulator-max- 431 regulator-max-microvolt = <1300000>;
440 regulator-boot 432 regulator-boot-on;
441 regulator-alwa 433 regulator-always-on;
442 regulator-ramp 434 regulator-ramp-delay = <1250>;
443 rohm,dvs-run-v 435 rohm,dvs-run-voltage = <1000000>;
444 rohm,dvs-idle- 436 rohm,dvs-idle-voltage = <900000>;
445 }; 437 };
446 438
447 /* vdd_0p9: 0.805-1.0V 439 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
448 BUCK3 { 440 BUCK3 {
449 regulator-name 441 regulator-name = "buck3";
450 regulator-min- 442 regulator-min-microvolt = <700000>;
451 regulator-max- 443 regulator-max-microvolt = <1350000>;
452 regulator-boot 444 regulator-boot-on;
453 regulator-alwa 445 regulator-always-on;
454 }; 446 };
455 447
456 /* vdd_3p3 */ 448 /* vdd_3p3 */
457 BUCK4 { 449 BUCK4 {
458 regulator-name 450 regulator-name = "buck4";
459 regulator-min- 451 regulator-min-microvolt = <3000000>;
460 regulator-max- 452 regulator-max-microvolt = <3300000>;
461 regulator-boot 453 regulator-boot-on;
462 regulator-alwa 454 regulator-always-on;
463 }; 455 };
464 456
465 /* vdd_1p8 */ 457 /* vdd_1p8 */
466 BUCK5 { 458 BUCK5 {
467 regulator-name 459 regulator-name = "buck5";
468 regulator-min- 460 regulator-min-microvolt = <1605000>;
469 regulator-max- 461 regulator-max-microvolt = <1995000>;
470 regulator-boot 462 regulator-boot-on;
471 regulator-alwa 463 regulator-always-on;
472 }; 464 };
473 465
474 /* vdd_dram */ 466 /* vdd_dram */
475 BUCK6 { 467 BUCK6 {
476 regulator-name 468 regulator-name = "buck6";
477 regulator-min- 469 regulator-min-microvolt = <800000>;
478 regulator-max- 470 regulator-max-microvolt = <1400000>;
479 regulator-boot 471 regulator-boot-on;
480 regulator-alwa 472 regulator-always-on;
481 }; 473 };
482 474
483 /* nvcc_snvs_1p8 */ 475 /* nvcc_snvs_1p8 */
484 LDO1 { 476 LDO1 {
485 regulator-name 477 regulator-name = "ldo1";
486 regulator-min- 478 regulator-min-microvolt = <1600000>;
487 regulator-max- 479 regulator-max-microvolt = <1900000>;
488 regulator-boot 480 regulator-boot-on;
489 regulator-alwa 481 regulator-always-on;
490 }; 482 };
491 483
492 /* vdd_snvs_0p8 */ 484 /* vdd_snvs_0p8 */
493 LDO2 { 485 LDO2 {
494 regulator-name 486 regulator-name = "ldo2";
495 regulator-min- 487 regulator-min-microvolt = <800000>;
496 regulator-max- 488 regulator-max-microvolt = <900000>;
497 regulator-boot 489 regulator-boot-on;
498 regulator-alwa 490 regulator-always-on;
499 }; 491 };
500 492
501 /* vdda_1p8 */ 493 /* vdda_1p8 */
502 LDO3 { 494 LDO3 {
503 regulator-name 495 regulator-name = "ldo3";
504 regulator-min- 496 regulator-min-microvolt = <1800000>;
505 regulator-max- 497 regulator-max-microvolt = <3300000>;
506 regulator-boot 498 regulator-boot-on;
507 regulator-alwa 499 regulator-always-on;
508 }; 500 };
509 501
510 LDO4 { 502 LDO4 {
511 regulator-name 503 regulator-name = "ldo4";
512 regulator-min- 504 regulator-min-microvolt = <900000>;
513 regulator-max- 505 regulator-max-microvolt = <1800000>;
514 regulator-boot 506 regulator-boot-on;
515 regulator-alwa 507 regulator-always-on;
516 }; 508 };
517 509
518 LDO6 { 510 LDO6 {
519 regulator-name 511 regulator-name = "ldo6";
520 regulator-min- 512 regulator-min-microvolt = <900000>;
521 regulator-max- 513 regulator-max-microvolt = <1800000>;
522 regulator-boot 514 regulator-boot-on;
523 regulator-alwa 515 regulator-always-on;
524 }; 516 };
525 }; 517 };
526 }; 518 };
527 }; 519 };
528 520
529 &i2c3 { 521 &i2c3 {
530 clock-frequency = <400000>; 522 clock-frequency = <400000>;
531 pinctrl-names = "default", "gpio"; !! 523 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_i2c3>; 524 pinctrl-0 = <&pinctrl_i2c3>;
533 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
534 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
535 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
536 status = "okay"; 525 status = "okay";
537 526
538 accelerometer@19 { 527 accelerometer@19 {
539 pinctrl-names = "default"; 528 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_accel>; 529 pinctrl-0 = <&pinctrl_accel>;
541 compatible = "st,lis2de12"; 530 compatible = "st,lis2de12";
542 reg = <0x19>; 531 reg = <0x19>;
543 st,drdy-int-pin = <1>; 532 st,drdy-int-pin = <1>;
544 interrupt-parent = <&gpio1>; 533 interrupt-parent = <&gpio1>;
545 interrupts = <15 IRQ_TYPE_LEVE 534 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
>> 535 interrupt-names = "INT1";
546 }; 536 };
547 }; 537 };
548 538
549 &pcie_phy { 539 &pcie_phy {
550 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 540 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
551 fsl,clkreq-unsupported; 541 fsl,clkreq-unsupported;
552 clocks = <&pcie0_refclk>; 542 clocks = <&pcie0_refclk>;
553 clock-names = "ref"; 543 clock-names = "ref";
554 status = "okay"; 544 status = "okay";
555 }; 545 };
556 546
557 &pcie0 { 547 &pcie0 {
558 pinctrl-names = "default"; 548 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_pcie0>; 549 pinctrl-0 = <&pinctrl_pcie0>;
560 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LO 550 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
561 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, !! 551 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
562 <&clk IMX8MM_CLK_PCIE1_AUX>; !! 552 <&pcie0_refclk>;
>> 553 clock-names = "pcie", "pcie_aux", "pcie_bus";
563 assigned-clocks = <&clk IMX8MM_CLK_PCI 554 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
564 <&clk IMX8MM_CLK_PCI 555 <&clk IMX8MM_CLK_PCIE1_CTRL>;
565 assigned-clock-rates = <10000000>, <25 556 assigned-clock-rates = <10000000>, <250000000>;
566 assigned-clock-parents = <&clk IMX8MM_ 557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
567 <&clk IMX8MM_ 558 <&clk IMX8MM_SYS_PLL2_250M>;
568 status = "okay"; 559 status = "okay";
569 }; 560 };
570 561
571 &disp_blk_ctrl { <<
572 status = "disabled"; <<
573 }; <<
574 <<
575 &pgc_mipi { 562 &pgc_mipi {
576 status = "disabled"; 563 status = "disabled";
577 }; 564 };
578 565
579 /* off-board RS232/RS485/RS422 */ 566 /* off-board RS232/RS485/RS422 */
580 &uart1 { 567 &uart1 {
581 pinctrl-names = "default"; 568 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart1>; 569 pinctrl-0 = <&pinctrl_uart1>;
583 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW> 570 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
584 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW> 571 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
585 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW> 572 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
586 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW> 573 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
587 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW 574 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
>> 575 uart-has-rtscts;
588 status = "okay"; 576 status = "okay";
589 }; 577 };
590 578
591 /* console */ 579 /* console */
592 &uart2 { 580 &uart2 {
593 pinctrl-names = "default"; 581 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_uart2>; 582 pinctrl-0 = <&pinctrl_uart2>;
595 status = "okay"; 583 status = "okay";
596 }; 584 };
597 585
598 &usbotg1 { 586 &usbotg1 {
599 dr_mode = "host"; 587 dr_mode = "host";
600 disable-over-current; 588 disable-over-current;
601 status = "okay"; 589 status = "okay";
602 }; 590 };
603 591
604 /* microSD */ 592 /* microSD */
605 &usdhc2 { 593 &usdhc2 {
606 pinctrl-names = "default", "state_100m 594 pinctrl-names = "default", "state_100mhz", "state_200mhz";
607 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 595 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
608 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 596 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 597 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 598 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
611 bus-width = <4>; 599 bus-width = <4>;
612 vmmc-supply = <®_3p3v>; 600 vmmc-supply = <®_3p3v>;
613 status = "okay"; 601 status = "okay";
614 }; 602 };
615 603
616 /* eMMC */ 604 /* eMMC */
617 &usdhc3 { 605 &usdhc3 {
618 pinctrl-names = "default", "state_100m 606 pinctrl-names = "default", "state_100mhz", "state_200mhz";
619 pinctrl-0 = <&pinctrl_usdhc3>; 607 pinctrl-0 = <&pinctrl_usdhc3>;
620 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 608 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
621 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 609 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
622 bus-width = <8>; 610 bus-width = <8>;
623 non-removable; 611 non-removable;
624 status = "okay"; 612 status = "okay";
625 }; 613 };
626 614
627 &wdog1 { 615 &wdog1 {
628 pinctrl-names = "default"; 616 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_wdog>; 617 pinctrl-0 = <&pinctrl_wdog>;
630 fsl,ext-reset-output; 618 fsl,ext-reset-output;
631 status = "okay"; 619 status = "okay";
632 }; 620 };
633 621
634 &iomuxc { 622 &iomuxc {
635 pinctrl-names = "default"; 623 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_hog>; 624 pinctrl-0 = <&pinctrl_hog>;
637 625
638 pinctrl_hog: hoggrp { 626 pinctrl_hog: hoggrp {
639 fsl,pins = < 627 fsl,pins = <
640 MX8MM_IOMUXC_GPIO1_IO1 628 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
641 MX8MM_IOMUXC_GPIO1_IO1 629 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
642 MX8MM_IOMUXC_GPIO1_IO1 630 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
643 MX8MM_IOMUXC_SD1_DATA7 631 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
644 MX8MM_IOMUXC_SD1_DATA6 632 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
645 MX8MM_IOMUXC_SD1_DATA4 <<
646 MX8MM_IOMUXC_SD1_DATA0 <<
647 MX8MM_IOMUXC_SD1_CLK_G 633 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
648 MX8MM_IOMUXC_SD1_CMD_G 634 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
649 MX8MM_IOMUXC_ECSPI1_MO 635 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
650 MX8MM_IOMUXC_ECSPI1_MI 636 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
651 MX8MM_IOMUXC_ECSPI1_SS 637 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
652 MX8MM_IOMUXC_ECSPI2_MI 638 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
653 >; 639 >;
654 }; 640 };
655 641
656 pinctrl_accel: accelgrp { 642 pinctrl_accel: accelgrp {
657 fsl,pins = < 643 fsl,pins = <
658 MX8MM_IOMUXC_GPIO1_IO1 644 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
659 >; 645 >;
660 }; 646 };
661 647
662 pinctrl_fec1: fec1grp { 648 pinctrl_fec1: fec1grp {
663 fsl,pins = < 649 fsl,pins = <
664 MX8MM_IOMUXC_ENET_MDC_ 650 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
665 MX8MM_IOMUXC_ENET_MDIO 651 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
666 MX8MM_IOMUXC_ENET_TD3_ 652 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
667 MX8MM_IOMUXC_ENET_TD2_ 653 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
668 MX8MM_IOMUXC_ENET_TD1_ 654 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
669 MX8MM_IOMUXC_ENET_TD0_ 655 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
670 MX8MM_IOMUXC_ENET_RD3_ 656 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
671 MX8MM_IOMUXC_ENET_RD2_ 657 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
672 MX8MM_IOMUXC_ENET_RD1_ 658 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
673 MX8MM_IOMUXC_ENET_RD0_ 659 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
674 MX8MM_IOMUXC_ENET_TXC_ 660 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
675 MX8MM_IOMUXC_ENET_RXC_ 661 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
676 MX8MM_IOMUXC_ENET_RX_C 662 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
677 MX8MM_IOMUXC_ENET_TX_C 663 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
678 MX8MM_IOMUXC_SAI2_TXFS 664 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
679 MX8MM_IOMUXC_SAI2_TXC_ 665 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
680 >; 666 >;
681 }; 667 };
682 668
683 pinctrl_gsc: gscgrp { 669 pinctrl_gsc: gscgrp {
684 fsl,pins = < 670 fsl,pins = <
685 MX8MM_IOMUXC_SAI2_TXD0 671 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
686 >; 672 >;
687 }; 673 };
688 674
689 pinctrl_i2c1: i2c1grp { 675 pinctrl_i2c1: i2c1grp {
690 fsl,pins = < 676 fsl,pins = <
691 MX8MM_IOMUXC_I2C1_SCL_ 677 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
692 MX8MM_IOMUXC_I2C1_SDA_ 678 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
693 >; 679 >;
694 }; 680 };
695 681
696 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
697 fsl,pins = < <<
698 MX8MM_IOMUXC_I2C1_SCL_ <<
699 MX8MM_IOMUXC_I2C1_SDA_ <<
700 >; <<
701 }; <<
702 <<
703 pinctrl_i2c2: i2c2grp { 682 pinctrl_i2c2: i2c2grp {
704 fsl,pins = < 683 fsl,pins = <
705 MX8MM_IOMUXC_I2C2_SCL_ 684 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
706 MX8MM_IOMUXC_I2C2_SDA_ 685 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
707 >; 686 >;
708 }; 687 };
709 688
710 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
711 fsl,pins = < <<
712 MX8MM_IOMUXC_I2C2_SCL_ <<
713 MX8MM_IOMUXC_I2C2_SDA_ <<
714 >; <<
715 }; <<
716 <<
717 pinctrl_i2c3: i2c3grp { 689 pinctrl_i2c3: i2c3grp {
718 fsl,pins = < 690 fsl,pins = <
719 MX8MM_IOMUXC_I2C3_SCL_ 691 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
720 MX8MM_IOMUXC_I2C3_SDA_ 692 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
721 >; <<
722 }; <<
723 <<
724 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
725 fsl,pins = < <<
726 MX8MM_IOMUXC_I2C3_SCL_ <<
727 MX8MM_IOMUXC_I2C3_SDA_ <<
728 >; 693 >;
729 }; 694 };
730 695
731 pinctrl_gpio_leds: gpioledgrp { 696 pinctrl_gpio_leds: gpioledgrp {
732 fsl,pins = < 697 fsl,pins = <
733 MX8MM_IOMUXC_SPDIF_EXT 698 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
734 MX8MM_IOMUXC_SAI3_RXD_ 699 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
735 MX8MM_IOMUXC_SAI3_MCLK 700 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
736 MX8MM_IOMUXC_GPIO1_IO1 701 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
737 MX8MM_IOMUXC_GPIO1_IO0 702 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
738 MX8MM_IOMUXC_SPDIF_TX_ 703 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
739 MX8MM_IOMUXC_SAI3_RXC_ 704 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
740 MX8MM_IOMUXC_SAI3_RXFS 705 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
741 MX8MM_IOMUXC_GPIO1_IO1 706 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
742 MX8MM_IOMUXC_SAI3_TXFS 707 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
743 MX8MM_IOMUXC_SPDIF_RX_ 708 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
744 MX8MM_IOMUXC_GPIO1_IO0 709 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
745 >; 710 >;
746 }; 711 };
747 712
748 pinctrl_pcie0: pciegrp { 713 pinctrl_pcie0: pciegrp {
749 fsl,pins = < 714 fsl,pins = <
750 MX8MM_IOMUXC_ECSPI2_MO 715 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
751 >; 716 >;
752 }; 717 };
753 718
754 pinctrl_pmic: pmicgrp { 719 pinctrl_pmic: pmicgrp {
755 fsl,pins = < 720 fsl,pins = <
756 MX8MM_IOMUXC_NAND_DATA 721 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
757 >; 722 >;
758 }; 723 };
759 724
760 pinctrl_uart1: uart1grp { 725 pinctrl_uart1: uart1grp {
761 fsl,pins = < 726 fsl,pins = <
762 MX8MM_IOMUXC_UART1_RXD 727 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
763 MX8MM_IOMUXC_UART1_TXD 728 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
764 MX8MM_IOMUXC_GPIO1_IO0 729 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
765 MX8MM_IOMUXC_GPIO1_IO0 730 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
766 MX8MM_IOMUXC_GPIO1_IO0 731 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
767 MX8MM_IOMUXC_GPIO1_IO0 732 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
768 MX8MM_IOMUXC_SAI5_RXD3 733 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
769 >; 734 >;
770 }; 735 };
771 736
772 pinctrl_uart2: uart2grp { 737 pinctrl_uart2: uart2grp {
773 fsl,pins = < 738 fsl,pins = <
774 MX8MM_IOMUXC_UART2_RXD 739 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
775 MX8MM_IOMUXC_UART2_TXD 740 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
776 >; 741 >;
777 }; 742 };
778 743
779 pinctrl_usdhc2: usdhc2grp { 744 pinctrl_usdhc2: usdhc2grp {
780 fsl,pins = < 745 fsl,pins = <
781 MX8MM_IOMUXC_SD2_CLK_U 746 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
782 MX8MM_IOMUXC_SD2_CMD_U 747 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
783 MX8MM_IOMUXC_SD2_DATA0 748 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
784 MX8MM_IOMUXC_SD2_DATA1 749 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
785 MX8MM_IOMUXC_SD2_DATA2 750 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
786 MX8MM_IOMUXC_SD2_DATA3 751 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
787 >; 752 >;
788 }; 753 };
789 754
790 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 755 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
791 fsl,pins = < 756 fsl,pins = <
792 MX8MM_IOMUXC_SD2_CLK_U 757 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
793 MX8MM_IOMUXC_SD2_CMD_U 758 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
794 MX8MM_IOMUXC_SD2_DATA0 759 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
795 MX8MM_IOMUXC_SD2_DATA1 760 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
796 MX8MM_IOMUXC_SD2_DATA2 761 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
797 MX8MM_IOMUXC_SD2_DATA3 762 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
798 >; 763 >;
799 }; 764 };
800 765
801 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 766 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
802 fsl,pins = < 767 fsl,pins = <
803 MX8MM_IOMUXC_SD2_CLK_U 768 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
804 MX8MM_IOMUXC_SD2_CMD_U 769 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
805 MX8MM_IOMUXC_SD2_DATA0 770 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
806 MX8MM_IOMUXC_SD2_DATA1 771 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
807 MX8MM_IOMUXC_SD2_DATA2 772 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
808 MX8MM_IOMUXC_SD2_DATA3 773 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
809 >; 774 >;
810 }; 775 };
811 776
812 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 777 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
813 fsl,pins = < 778 fsl,pins = <
814 MX8MM_IOMUXC_SD2_CD_B_ 779 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
815 MX8MM_IOMUXC_GPIO1_IO0 780 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
816 >; 781 >;
817 }; 782 };
818 783
819 pinctrl_usdhc3: usdhc3grp { 784 pinctrl_usdhc3: usdhc3grp {
820 fsl,pins = < 785 fsl,pins = <
821 MX8MM_IOMUXC_NAND_WE_B 786 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
822 MX8MM_IOMUXC_NAND_WP_B 787 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
823 MX8MM_IOMUXC_NAND_DATA 788 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
824 MX8MM_IOMUXC_NAND_DATA 789 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
825 MX8MM_IOMUXC_NAND_DATA 790 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
826 MX8MM_IOMUXC_NAND_DATA 791 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
827 MX8MM_IOMUXC_NAND_RE_B 792 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
828 MX8MM_IOMUXC_NAND_CE2_ 793 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
829 MX8MM_IOMUXC_NAND_CE3_ 794 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
830 MX8MM_IOMUXC_NAND_CLE_ 795 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
831 MX8MM_IOMUXC_NAND_CE1_ 796 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
832 >; 797 >;
833 }; 798 };
834 799
835 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 800 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
836 fsl,pins = < 801 fsl,pins = <
837 MX8MM_IOMUXC_NAND_WE_B 802 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
838 MX8MM_IOMUXC_NAND_WP_B 803 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
839 MX8MM_IOMUXC_NAND_DATA 804 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
840 MX8MM_IOMUXC_NAND_DATA 805 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
841 MX8MM_IOMUXC_NAND_DATA 806 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
842 MX8MM_IOMUXC_NAND_DATA 807 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
843 MX8MM_IOMUXC_NAND_RE_B 808 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
844 MX8MM_IOMUXC_NAND_CE2_ 809 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
845 MX8MM_IOMUXC_NAND_CE3_ 810 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
846 MX8MM_IOMUXC_NAND_CLE_ 811 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
847 MX8MM_IOMUXC_NAND_CE1_ 812 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
848 >; 813 >;
849 }; 814 };
850 815
851 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 816 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
852 fsl,pins = < 817 fsl,pins = <
853 MX8MM_IOMUXC_NAND_WE_B 818 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
854 MX8MM_IOMUXC_NAND_WP_B 819 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
855 MX8MM_IOMUXC_NAND_DATA 820 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
856 MX8MM_IOMUXC_NAND_DATA 821 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
857 MX8MM_IOMUXC_NAND_DATA 822 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
858 MX8MM_IOMUXC_NAND_DATA 823 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
859 MX8MM_IOMUXC_NAND_RE_B 824 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
860 MX8MM_IOMUXC_NAND_CE2_ 825 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
861 MX8MM_IOMUXC_NAND_CE3_ 826 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
862 MX8MM_IOMUXC_NAND_CLE_ 827 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
863 MX8MM_IOMUXC_NAND_CE1_ 828 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
864 >; 829 >;
865 }; 830 };
866 831
867 pinctrl_wdog: wdoggrp { 832 pinctrl_wdog: wdoggrp {
868 fsl,pins = < 833 fsl,pins = <
869 MX8MM_IOMUXC_GPIO1_IO0 834 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
870 >; 835 >;
871 }; 836 };
872 }; 837 };
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