1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2022 Gateworks Corporation 3 * Copyright 2022 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 12
13 #include "imx8mm.dtsi" 13 #include "imx8mm.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7904 i.MX8 16 model = "Gateworks Venice GW7904 i.MX8MM board";
17 compatible = "gateworks,imx8mm-gw7904" 17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart2; 20 stdout-path = &uart2;
21 }; 21 };
22 22
23 memory@40000000 { 23 memory@40000000 {
24 device_type = "memory"; 24 device_type = "memory";
25 reg = <0x0 0x40000000 0 0x8000 25 reg = <0x0 0x40000000 0 0x80000000>;
26 }; 26 };
27 27
28 gpio-keys { 28 gpio-keys {
29 compatible = "gpio-keys"; 29 compatible = "gpio-keys";
30 30
31 key-0 { 31 key-0 {
32 label = "user_pb"; 32 label = "user_pb";
33 gpios = <&gpio 2 GPIO_ 33 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
34 linux,code = <BTN_0>; 34 linux,code = <BTN_0>;
35 }; 35 };
36 36
37 key-1 { 37 key-1 {
38 label = "user_pb1x"; 38 label = "user_pb1x";
39 linux,code = <BTN_1>; 39 linux,code = <BTN_1>;
40 interrupt-parent = <&g 40 interrupt-parent = <&gsc>;
41 interrupts = <0>; 41 interrupts = <0>;
42 }; 42 };
43 43
44 key-2 { 44 key-2 {
45 label = "key_erased"; 45 label = "key_erased";
46 linux,code = <BTN_2>; 46 linux,code = <BTN_2>;
47 interrupt-parent = <&g 47 interrupt-parent = <&gsc>;
48 interrupts = <1>; 48 interrupts = <1>;
49 }; 49 };
50 50
51 key-3 { 51 key-3 {
52 label = "eeprom_wp"; 52 label = "eeprom_wp";
53 linux,code = <BTN_3>; 53 linux,code = <BTN_3>;
54 interrupt-parent = <&g 54 interrupt-parent = <&gsc>;
55 interrupts = <2>; 55 interrupts = <2>;
56 }; 56 };
57 57
58 key-4 { 58 key-4 {
59 label = "switch_hold"; 59 label = "switch_hold";
60 linux,code = <BTN_5>; 60 linux,code = <BTN_5>;
61 interrupt-parent = <&g 61 interrupt-parent = <&gsc>;
62 interrupts = <7>; 62 interrupts = <7>;
63 }; 63 };
64 }; 64 };
65 65
66 led-controller { 66 led-controller {
67 compatible = "gpio-leds"; 67 compatible = "gpio-leds";
68 pinctrl-names = "default"; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_led 69 pinctrl-0 = <&pinctrl_gpio_leds>;
70 70
71 led-0 { 71 led-0 {
72 function = LED_FUNCTIO 72 function = LED_FUNCTION_STATUS;
73 color = <LED_COLOR_ID_ 73 color = <LED_COLOR_ID_GREEN>;
74 label = "led01_grn"; 74 label = "led01_grn";
75 gpios = <&gpioled 0 GP 75 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
76 default-state = "off"; 76 default-state = "off";
77 }; 77 };
78 78
79 led-1 { 79 led-1 {
80 function = LED_FUNCTIO 80 function = LED_FUNCTION_STATUS;
81 color = <LED_COLOR_ID_ 81 color = <LED_COLOR_ID_YELLOW>;
82 label = "led01_yel"; 82 label = "led01_yel";
83 gpios = <&gpioled 1 GP 83 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
84 default-state = "off"; 84 default-state = "off";
85 }; 85 };
86 86
87 led-2 { 87 led-2 {
88 function = LED_FUNCTIO 88 function = LED_FUNCTION_STATUS;
89 color = <LED_COLOR_ID_ 89 color = <LED_COLOR_ID_GREEN>;
90 label = "led02_grn"; 90 label = "led02_grn";
91 gpios = <&gpioled 2 GP 91 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
92 default-state = "off"; 92 default-state = "off";
93 }; 93 };
94 94
95 led-3 { 95 led-3 {
96 function = LED_FUNCTIO 96 function = LED_FUNCTION_STATUS;
97 color = <LED_COLOR_ID_ 97 color = <LED_COLOR_ID_YELLOW>;
98 label = "led02_yel"; 98 label = "led02_yel";
99 gpios = <&gpioled 3 GP 99 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
100 default-state = "off"; 100 default-state = "off";
101 }; 101 };
102 102
103 led-4 { 103 led-4 {
104 function = LED_FUNCTIO 104 function = LED_FUNCTION_STATUS;
105 color = <LED_COLOR_ID_ 105 color = <LED_COLOR_ID_GREEN>;
106 label = "led03_grn"; 106 label = "led03_grn";
107 gpios = <&gpioled 4 GP 107 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
108 default-state = "off"; 108 default-state = "off";
109 }; 109 };
110 110
111 led-5 { 111 led-5 {
112 function = LED_FUNCTIO 112 function = LED_FUNCTION_STATUS;
113 color = <LED_COLOR_ID_ 113 color = <LED_COLOR_ID_YELLOW>;
114 label = "led03_yel"; 114 label = "led03_yel";
115 gpios = <&gpioled 5 GP 115 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
116 default-state = "off"; 116 default-state = "off";
117 }; 117 };
118 118
119 led-6 { 119 led-6 {
120 function = LED_FUNCTIO 120 function = LED_FUNCTION_STATUS;
121 color = <LED_COLOR_ID_ 121 color = <LED_COLOR_ID_GREEN>;
122 label = "led04_grn"; 122 label = "led04_grn";
123 gpios = <&gpioled 6 GP 123 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
124 default-state = "off"; 124 default-state = "off";
125 }; 125 };
126 126
127 led-7 { 127 led-7 {
128 function = LED_FUNCTIO 128 function = LED_FUNCTION_STATUS;
129 color = <LED_COLOR_ID_ 129 color = <LED_COLOR_ID_YELLOW>;
130 label = "led04_yel"; 130 label = "led04_yel";
131 gpios = <&gpioled 7 GP 131 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
132 default-state = "off"; 132 default-state = "off";
133 }; 133 };
134 134
135 led-8 { 135 led-8 {
136 function = LED_FUNCTIO 136 function = LED_FUNCTION_STATUS;
137 color = <LED_COLOR_ID_ 137 color = <LED_COLOR_ID_GREEN>;
138 label = "led05_grn"; 138 label = "led05_grn";
139 gpios = <&gpioled 8 GP 139 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
140 default-state = "off"; 140 default-state = "off";
141 }; 141 };
142 142
143 led-9 { 143 led-9 {
144 function = LED_FUNCTIO 144 function = LED_FUNCTION_STATUS;
145 color = <LED_COLOR_ID_ 145 color = <LED_COLOR_ID_YELLOW>;
146 label = "led05_yel"; 146 label = "led05_yel";
147 gpios = <&gpioled 9 GP 147 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
148 default-state = "off"; 148 default-state = "off";
149 }; 149 };
150 150
151 led-10 { 151 led-10 {
152 function = LED_FUNCTIO 152 function = LED_FUNCTION_STATUS;
153 color = <LED_COLOR_ID_ 153 color = <LED_COLOR_ID_GREEN>;
154 label = "led06_grn"; 154 label = "led06_grn";
155 gpios = <&gpio1 8 GPIO 155 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
156 default-state = "off"; 156 default-state = "off";
157 }; 157 };
158 158
159 led-11 { 159 led-11 {
160 function = LED_FUNCTIO 160 function = LED_FUNCTION_STATUS;
161 color = <LED_COLOR_ID_ 161 color = <LED_COLOR_ID_RED>;
162 label = "led06_red"; 162 label = "led06_red";
163 gpios = <&gpio1 9 GPIO 163 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
164 default-state = "off"; 164 default-state = "off";
165 }; 165 };
166 166
167 led-12 { 167 led-12 {
168 function = LED_FUNCTIO 168 function = LED_FUNCTION_STATUS;
169 color = <LED_COLOR_ID_ 169 color = <LED_COLOR_ID_GREEN>;
170 label = "led07_grn"; 170 label = "led07_grn";
171 gpios = <&gpio1 10 GPI 171 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
172 default-state = "off"; 172 default-state = "off";
173 }; 173 };
174 174
175 led-13 { 175 led-13 {
176 function = LED_FUNCTIO 176 function = LED_FUNCTION_STATUS;
177 color = <LED_COLOR_ID_ 177 color = <LED_COLOR_ID_RED>;
178 label = "led07_red"; 178 label = "led07_red";
179 gpios = <&gpio1 11 GPI 179 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
180 default-state = "off"; 180 default-state = "off";
181 }; 181 };
182 182
183 led-14 { 183 led-14 {
184 function = LED_FUNCTIO 184 function = LED_FUNCTION_STATUS;
185 color = <LED_COLOR_ID_ 185 color = <LED_COLOR_ID_GREEN>;
186 label = "led08_grn"; 186 label = "led08_grn";
187 gpios = <&gpioled 10 G 187 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
188 default-state = "off"; 188 default-state = "off";
189 }; 189 };
190 190
191 led-15 { 191 led-15 {
192 function = LED_FUNCTIO 192 function = LED_FUNCTION_STATUS;
193 color = <LED_COLOR_ID_ 193 color = <LED_COLOR_ID_YELLOW>;
194 label = "led08_yel"; 194 label = "led08_yel";
195 gpios = <&gpioled 11 G 195 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
196 default-state = "off"; 196 default-state = "off";
197 }; 197 };
198 198
199 led-16 { 199 led-16 {
200 function = LED_FUNCTIO 200 function = LED_FUNCTION_STATUS;
201 color = <LED_COLOR_ID_ 201 color = <LED_COLOR_ID_GREEN>;
202 label = "led09_grn"; 202 label = "led09_grn";
203 gpios = <&gpioled 12 G 203 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
204 default-state = "off"; 204 default-state = "off";
205 }; 205 };
206 206
207 led-17 { 207 led-17 {
208 function = LED_FUNCTIO 208 function = LED_FUNCTION_STATUS;
209 color = <LED_COLOR_ID_ 209 color = <LED_COLOR_ID_YELLOW>;
210 label = "led09_yel"; 210 label = "led09_yel";
211 gpios = <&gpioled 13 G 211 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
212 default-state = "off"; 212 default-state = "off";
213 }; 213 };
214 214
215 led-18 { 215 led-18 {
216 function = LED_FUNCTIO 216 function = LED_FUNCTION_STATUS;
217 color = <LED_COLOR_ID_ 217 color = <LED_COLOR_ID_GREEN>;
218 label = "led10_grn"; 218 label = "led10_grn";
219 gpios = <&gpioled 14 G 219 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
220 default-state = "off"; 220 default-state = "off";
221 }; 221 };
222 222
223 led-19 { 223 led-19 {
224 function = LED_FUNCTIO 224 function = LED_FUNCTION_STATUS;
225 color = <LED_COLOR_ID_ 225 color = <LED_COLOR_ID_YELLOW>;
226 label = "led10_yel"; 226 label = "led10_yel";
227 gpios = <&gpioled 15 G 227 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
228 default-state = "off"; 228 default-state = "off";
229 }; 229 };
230 }; 230 };
231 231
232 pcie0_refclk: pcie0-refclk { 232 pcie0_refclk: pcie0-refclk {
233 compatible = "fixed-clock"; 233 compatible = "fixed-clock";
234 #clock-cells = <0>; 234 #clock-cells = <0>;
235 clock-frequency = <100000000>; 235 clock-frequency = <100000000>;
236 }; 236 };
237 237
238 reg_3p3v: regulator-3p3v { 238 reg_3p3v: regulator-3p3v {
239 compatible = "regulator-fixed" 239 compatible = "regulator-fixed";
240 regulator-name = "3P3V"; 240 regulator-name = "3P3V";
241 regulator-min-microvolt = <330 241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <330 242 regulator-max-microvolt = <3300000>;
243 regulator-always-on; 243 regulator-always-on;
244 }; 244 };
245 }; 245 };
246 246
247 &A53_0 { 247 &A53_0 {
248 cpu-supply = <&buck2>; 248 cpu-supply = <&buck2>;
249 }; 249 };
250 250
251 &A53_1 { 251 &A53_1 {
252 cpu-supply = <&buck2>; 252 cpu-supply = <&buck2>;
253 }; 253 };
254 254
255 &A53_2 { 255 &A53_2 {
256 cpu-supply = <&buck2>; 256 cpu-supply = <&buck2>;
257 }; 257 };
258 258
259 &A53_3 { 259 &A53_3 {
260 cpu-supply = <&buck2>; 260 cpu-supply = <&buck2>;
261 }; 261 };
262 262
263 &ddrc { 263 &ddrc {
264 operating-points-v2 = <&ddrc_opp_table 264 operating-points-v2 = <&ddrc_opp_table>;
265 265
266 ddrc_opp_table: opp-table { 266 ddrc_opp_table: opp-table {
267 compatible = "operating-points 267 compatible = "operating-points-v2";
268 268
269 opp-25000000 { !! 269 opp-25M {
270 opp-hz = /bits/ 64 <25 270 opp-hz = /bits/ 64 <25000000>;
271 }; 271 };
272 272
273 opp-100000000 { !! 273 opp-100M {
274 opp-hz = /bits/ 64 <10 274 opp-hz = /bits/ 64 <100000000>;
275 }; 275 };
276 276
277 opp-750000000 { !! 277 opp-750M {
278 opp-hz = /bits/ 64 <75 278 opp-hz = /bits/ 64 <750000000>;
279 }; 279 };
280 }; 280 };
281 }; 281 };
282 282
283 &fec1 { 283 &fec1 {
284 pinctrl-names = "default"; 284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec1>; 285 pinctrl-0 = <&pinctrl_fec1>;
286 phy-mode = "rgmii-id"; 286 phy-mode = "rgmii-id";
287 phy-handle = <ðphy0>; 287 phy-handle = <ðphy0>;
288 local-mac-address = [00 00 00 00 00 00 288 local-mac-address = [00 00 00 00 00 00];
289 status = "okay"; 289 status = "okay";
290 290
291 mdio { 291 mdio {
292 #address-cells = <1>; 292 #address-cells = <1>;
293 #size-cells = <0>; 293 #size-cells = <0>;
294 294
295 ethphy0: ethernet-phy@0 { 295 ethphy0: ethernet-phy@0 {
296 compatible = "ethernet 296 compatible = "ethernet-phy-ieee802.3-c22";
297 reg = <0>; 297 reg = <0>;
298 }; 298 };
299 }; 299 };
300 }; 300 };
301 301
302 &gpio1 { 302 &gpio1 {
303 gpio-line-names = "", "", "", "", "", 303 gpio-line-names = "", "", "", "", "", "", "", "",
304 "", "", "", "", "rs232_en#", " 304 "", "", "", "", "rs232_en#", "", "", "",
305 "", "", "", "", "", "", "", "" 305 "", "", "", "", "", "", "", "",
306 "", "", "", "", "", "", "", "" 306 "", "", "", "", "", "", "", "";
307 }; 307 };
308 308
309 &gpio5 { 309 &gpio5 {
310 gpio-line-names = "", "", "", "", "", 310 gpio-line-names = "", "", "", "", "", "", "", "",
311 "", "", "", "", "pci_wdis#", " 311 "", "", "", "", "pci_wdis#", "", "", "",
312 "", "", "", "", "", "", "", "" 312 "", "", "", "", "", "", "", "",
313 "", "", "", "", "", "", "", "" 313 "", "", "", "", "", "", "", "";
314 }; 314 };
315 315
316 &i2c1 { 316 &i2c1 {
317 clock-frequency = <100000>; 317 clock-frequency = <100000>;
318 pinctrl-names = "default", "gpio"; !! 318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_i2c1>; 319 pinctrl-0 = <&pinctrl_i2c1>;
320 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
321 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
322 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
323 status = "okay"; 320 status = "okay";
324 321
325 gsc: gsc@20 { 322 gsc: gsc@20 {
326 compatible = "gw,gsc"; 323 compatible = "gw,gsc";
327 reg = <0x20>; 324 reg = <0x20>;
328 pinctrl-0 = <&pinctrl_gsc>; 325 pinctrl-0 = <&pinctrl_gsc>;
329 interrupt-parent = <&gpio4>; 326 interrupt-parent = <&gpio4>;
330 interrupts = <26 IRQ_TYPE_EDGE 327 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
331 interrupt-controller; 328 interrupt-controller;
332 #interrupt-cells = <1>; 329 #interrupt-cells = <1>;
333 #address-cells = <1>; <<
334 #size-cells = <0>; <<
335 330
336 adc { 331 adc {
337 compatible = "gw,gsc-a 332 compatible = "gw,gsc-adc";
338 #address-cells = <1>; 333 #address-cells = <1>;
339 #size-cells = <0>; 334 #size-cells = <0>;
340 335
341 channel@6 { 336 channel@6 {
342 gw,mode = <0>; 337 gw,mode = <0>;
343 reg = <0x06>; 338 reg = <0x06>;
344 label = "temp" 339 label = "temp";
345 }; 340 };
346 341
347 channel@82 { 342 channel@82 {
348 gw,mode = <2>; 343 gw,mode = <2>;
349 reg = <0x82>; 344 reg = <0x82>;
350 label = "vin"; 345 label = "vin";
351 gw,voltage-div 346 gw,voltage-divider-ohms = <22100 1000>;
352 gw,voltage-off 347 gw,voltage-offset-microvolt = <700000>;
353 }; 348 };
354 349
355 channel@84 { 350 channel@84 {
356 gw,mode = <2>; 351 gw,mode = <2>;
357 reg = <0x84>; 352 reg = <0x84>;
358 label = "vdd_5 353 label = "vdd_5p0";
359 gw,voltage-div 354 gw,voltage-divider-ohms = <10000 10000>;
360 }; 355 };
361 356
362 channel@86 { 357 channel@86 {
363 gw,mode = <2>; 358 gw,mode = <2>;
364 reg = <0x86>; 359 reg = <0x86>;
365 label = "vdd_3 360 label = "vdd_3p3";
366 gw,voltage-div 361 gw,voltage-divider-ohms = <10000 10000>;
367 }; 362 };
368 363
369 channel@88 { 364 channel@88 {
370 gw,mode = <2>; 365 gw,mode = <2>;
371 reg = <0x88>; 366 reg = <0x88>;
372 label = "vdd_0 367 label = "vdd_0p9";
373 }; 368 };
374 369
375 channel@8c { 370 channel@8c {
376 gw,mode = <2>; 371 gw,mode = <2>;
377 reg = <0x8c>; 372 reg = <0x8c>;
378 label = "vdd_s 373 label = "vdd_soc";
379 }; 374 };
380 375
381 channel@8e { 376 channel@8e {
382 gw,mode = <2>; 377 gw,mode = <2>;
383 reg = <0x8e>; 378 reg = <0x8e>;
384 label = "vdd_a 379 label = "vdd_arm";
385 }; 380 };
386 381
387 channel@90 { 382 channel@90 {
388 gw,mode = <2>; 383 gw,mode = <2>;
389 reg = <0x90>; 384 reg = <0x90>;
390 label = "vdd_1 385 label = "vdd_1p8";
391 }; 386 };
392 387
393 channel@92 { 388 channel@92 {
394 gw,mode = <2>; 389 gw,mode = <2>;
395 reg = <0x92>; 390 reg = <0x92>;
396 label = "vdd_d 391 label = "vdd_dram";
397 }; 392 };
398 393
399 channel@a2 { 394 channel@a2 {
400 gw,mode = <2>; 395 gw,mode = <2>;
401 reg = <0xa2>; 396 reg = <0xa2>;
402 label = "vdd_g 397 label = "vdd_gsc";
403 gw,voltage-div 398 gw,voltage-divider-ohms = <10000 10000>;
404 }; 399 };
405 }; 400 };
406 }; 401 };
407 402
408 gpio: gpio@23 { 403 gpio: gpio@23 {
409 compatible = "nxp,pca9555"; 404 compatible = "nxp,pca9555";
410 reg = <0x23>; 405 reg = <0x23>;
411 gpio-controller; 406 gpio-controller;
412 #gpio-cells = <2>; 407 #gpio-cells = <2>;
413 interrupt-parent = <&gsc>; 408 interrupt-parent = <&gsc>;
414 interrupts = <4>; 409 interrupts = <4>;
415 }; 410 };
416 411
417 eeprom@50 { 412 eeprom@50 {
418 compatible = "atmel,24c02"; 413 compatible = "atmel,24c02";
419 reg = <0x50>; 414 reg = <0x50>;
420 pagesize = <16>; 415 pagesize = <16>;
421 }; 416 };
422 417
423 eeprom@51 { 418 eeprom@51 {
424 compatible = "atmel,24c02"; 419 compatible = "atmel,24c02";
425 reg = <0x51>; 420 reg = <0x51>;
426 pagesize = <16>; 421 pagesize = <16>;
427 }; 422 };
428 423
429 eeprom@52 { 424 eeprom@52 {
430 compatible = "atmel,24c02"; 425 compatible = "atmel,24c02";
431 reg = <0x52>; 426 reg = <0x52>;
432 pagesize = <16>; 427 pagesize = <16>;
433 }; 428 };
434 429
435 eeprom@53 { 430 eeprom@53 {
436 compatible = "atmel,24c02"; 431 compatible = "atmel,24c02";
437 reg = <0x53>; 432 reg = <0x53>;
438 pagesize = <16>; 433 pagesize = <16>;
439 }; 434 };
440 435
441 rtc@68 { 436 rtc@68 {
442 compatible = "dallas,ds1672"; 437 compatible = "dallas,ds1672";
443 reg = <0x68>; 438 reg = <0x68>;
444 }; 439 };
445 }; 440 };
446 441
447 &i2c2 { 442 &i2c2 {
448 clock-frequency = <400000>; 443 clock-frequency = <400000>;
449 pinctrl-names = "default", "gpio"; !! 444 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_i2c2>; 445 pinctrl-0 = <&pinctrl_i2c2>;
451 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
452 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
453 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
454 status = "okay"; 446 status = "okay";
455 447
456 pmic@4b { 448 pmic@4b {
457 compatible = "rohm,bd71847"; 449 compatible = "rohm,bd71847";
458 reg = <0x4b>; 450 reg = <0x4b>;
459 pinctrl-names = "default"; 451 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_pmic>; 452 pinctrl-0 = <&pinctrl_pmic>;
461 interrupt-parent = <&gpio3>; 453 interrupt-parent = <&gpio3>;
462 interrupts = <8 IRQ_TYPE_LEVEL 454 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
463 rohm,reset-snvs-powered; 455 rohm,reset-snvs-powered;
464 #clock-cells = <0>; 456 #clock-cells = <0>;
465 clocks = <&osc_32k>; !! 457 clocks = <&osc_32k 0>;
466 clock-output-names = "clk-32k- 458 clock-output-names = "clk-32k-out";
467 459
468 regulators { 460 regulators {
469 /* vdd_soc: 0.805-0.90 461 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
470 BUCK1 { 462 BUCK1 {
471 regulator-name 463 regulator-name = "buck1";
472 regulator-min- 464 regulator-min-microvolt = <700000>;
473 regulator-max- 465 regulator-max-microvolt = <1300000>;
474 regulator-boot 466 regulator-boot-on;
475 regulator-alwa 467 regulator-always-on;
476 regulator-ramp 468 regulator-ramp-delay = <1250>;
477 }; 469 };
478 470
479 /* vdd_arm: 0.805-1.0V 471 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
480 buck2: BUCK2 { 472 buck2: BUCK2 {
481 regulator-name 473 regulator-name = "buck2";
482 regulator-min- 474 regulator-min-microvolt = <700000>;
483 regulator-max- 475 regulator-max-microvolt = <1300000>;
484 regulator-boot 476 regulator-boot-on;
485 regulator-alwa 477 regulator-always-on;
486 regulator-ramp 478 regulator-ramp-delay = <1250>;
487 rohm,dvs-run-v 479 rohm,dvs-run-voltage = <1000000>;
488 rohm,dvs-idle- 480 rohm,dvs-idle-voltage = <900000>;
489 }; 481 };
490 482
491 /* vdd_0p9: 0.805-1.0V 483 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
492 BUCK3 { 484 BUCK3 {
493 regulator-name 485 regulator-name = "buck3";
494 regulator-min- 486 regulator-min-microvolt = <700000>;
495 regulator-max- 487 regulator-max-microvolt = <1350000>;
496 regulator-boot 488 regulator-boot-on;
497 regulator-alwa 489 regulator-always-on;
498 }; 490 };
499 491
500 /* vdd_3p3 */ 492 /* vdd_3p3 */
501 BUCK4 { 493 BUCK4 {
502 regulator-name 494 regulator-name = "buck4";
503 regulator-min- 495 regulator-min-microvolt = <3000000>;
504 regulator-max- 496 regulator-max-microvolt = <3300000>;
505 regulator-boot 497 regulator-boot-on;
506 regulator-alwa 498 regulator-always-on;
507 }; 499 };
508 500
509 /* vdd_1p8 */ 501 /* vdd_1p8 */
510 BUCK5 { 502 BUCK5 {
511 regulator-name 503 regulator-name = "buck5";
512 regulator-min- 504 regulator-min-microvolt = <1605000>;
513 regulator-max- 505 regulator-max-microvolt = <1995000>;
514 regulator-boot 506 regulator-boot-on;
515 regulator-alwa 507 regulator-always-on;
516 }; 508 };
517 509
518 /* vdd_dram */ 510 /* vdd_dram */
519 BUCK6 { 511 BUCK6 {
520 regulator-name 512 regulator-name = "buck6";
521 regulator-min- 513 regulator-min-microvolt = <800000>;
522 regulator-max- 514 regulator-max-microvolt = <1400000>;
523 regulator-boot 515 regulator-boot-on;
524 regulator-alwa 516 regulator-always-on;
525 }; 517 };
526 518
527 /* nvcc_snvs_1p8 */ 519 /* nvcc_snvs_1p8 */
528 LDO1 { 520 LDO1 {
529 regulator-name 521 regulator-name = "ldo1";
530 regulator-min- 522 regulator-min-microvolt = <1600000>;
531 regulator-max- 523 regulator-max-microvolt = <1900000>;
532 regulator-boot 524 regulator-boot-on;
533 regulator-alwa 525 regulator-always-on;
534 }; 526 };
535 527
536 /* vdd_snvs_0p8 */ 528 /* vdd_snvs_0p8 */
537 LDO2 { 529 LDO2 {
538 regulator-name 530 regulator-name = "ldo2";
539 regulator-min- 531 regulator-min-microvolt = <800000>;
540 regulator-max- 532 regulator-max-microvolt = <900000>;
541 regulator-boot 533 regulator-boot-on;
542 regulator-alwa 534 regulator-always-on;
543 }; 535 };
544 536
545 /* vdda_1p8 */ 537 /* vdda_1p8 */
546 LDO3 { 538 LDO3 {
547 regulator-name 539 regulator-name = "ldo3";
548 regulator-min- 540 regulator-min-microvolt = <1800000>;
549 regulator-max- 541 regulator-max-microvolt = <3300000>;
550 regulator-boot 542 regulator-boot-on;
551 regulator-alwa 543 regulator-always-on;
552 }; 544 };
553 545
554 LDO4 { 546 LDO4 {
555 regulator-name 547 regulator-name = "ldo4";
556 regulator-min- 548 regulator-min-microvolt = <900000>;
557 regulator-max- 549 regulator-max-microvolt = <1800000>;
558 regulator-boot 550 regulator-boot-on;
559 regulator-alwa 551 regulator-always-on;
560 }; 552 };
561 553
562 LDO6 { 554 LDO6 {
563 regulator-name 555 regulator-name = "ldo6";
564 regulator-min- 556 regulator-min-microvolt = <900000>;
565 regulator-max- 557 regulator-max-microvolt = <1800000>;
566 regulator-boot 558 regulator-boot-on;
567 regulator-alwa 559 regulator-always-on;
568 }; 560 };
569 }; 561 };
570 }; 562 };
571 }; 563 };
572 564
573 &i2c3 { 565 &i2c3 {
574 clock-frequency = <400000>; 566 clock-frequency = <400000>;
575 pinctrl-names = "default", "gpio"; !! 567 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_i2c3>; 568 pinctrl-0 = <&pinctrl_i2c3>;
577 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
578 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
579 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
580 status = "okay"; 569 status = "okay";
581 570
582 accelerometer@19 { 571 accelerometer@19 {
583 pinctrl-names = "default"; 572 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_accel>; 573 pinctrl-0 = <&pinctrl_accel>;
585 compatible = "st,lis2de12"; 574 compatible = "st,lis2de12";
586 reg = <0x19>; 575 reg = <0x19>;
587 st,drdy-int-pin = <1>; 576 st,drdy-int-pin = <1>;
588 interrupt-parent = <&gpio1>; 577 interrupt-parent = <&gpio1>;
589 interrupts = <15 IRQ_TYPE_LEVE 578 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
>> 579 interrupt-names = "INT1";
590 }; 580 };
591 }; 581 };
592 582
593 &i2c4 { 583 &i2c4 {
594 clock-frequency = <400000>; 584 clock-frequency = <400000>;
595 pinctrl-names = "default", "gpio"; !! 585 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_i2c4>; 586 pinctrl-0 = <&pinctrl_i2c4>;
597 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
598 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
599 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
600 status = "okay"; 587 status = "okay";
601 588
602 gpioled: gpio@27 { 589 gpioled: gpio@27 {
603 compatible = "nxp,pca9555"; 590 compatible = "nxp,pca9555";
604 reg = <0x27>; 591 reg = <0x27>;
605 gpio-controller; 592 gpio-controller;
606 #gpio-cells = <2>; 593 #gpio-cells = <2>;
607 }; 594 };
608 }; 595 };
609 596
610 &pcie_phy { 597 &pcie_phy {
611 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 598 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
612 fsl,clkreq-unsupported; 599 fsl,clkreq-unsupported;
613 clocks = <&pcie0_refclk>; 600 clocks = <&pcie0_refclk>;
614 clock-names = "ref"; 601 clock-names = "ref";
615 status = "okay"; 602 status = "okay";
616 }; 603 };
617 604
618 &pcie0 { 605 &pcie0 {
619 pinctrl-names = "default"; 606 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_pcie0>; 607 pinctrl-0 = <&pinctrl_pcie0>;
621 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LO 608 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
622 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, !! 609 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
623 <&clk IMX8MM_CLK_PCIE1_AUX>; !! 610 <&pcie0_refclk>;
>> 611 clock-names = "pcie", "pcie_aux", "pcie_bus";
624 assigned-clocks = <&clk IMX8MM_CLK_PCI 612 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
625 <&clk IMX8MM_CLK_PCI 613 <&clk IMX8MM_CLK_PCIE1_CTRL>;
626 assigned-clock-rates = <10000000>, <25 614 assigned-clock-rates = <10000000>, <250000000>;
627 assigned-clock-parents = <&clk IMX8MM_ 615 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
628 <&clk IMX8MM_ 616 <&clk IMX8MM_SYS_PLL2_250M>;
629 status = "okay"; 617 status = "okay";
630 }; 618 };
631 619
632 &disp_blk_ctrl { 620 &disp_blk_ctrl {
633 status = "disabled"; 621 status = "disabled";
634 }; 622 };
635 623
636 &pgc_mipi { 624 &pgc_mipi {
637 status = "disabled"; 625 status = "disabled";
638 }; 626 };
639 627
640 /* off-board RS232 */ 628 /* off-board RS232 */
641 &uart1 { 629 &uart1 {
642 pinctrl-names = "default"; 630 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_uart1>; 631 pinctrl-0 = <&pinctrl_uart1>;
644 cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW <<
645 rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW <<
646 status = "okay"; 632 status = "okay";
647 }; 633 };
648 634
649 /* console */ 635 /* console */
650 &uart2 { 636 &uart2 {
651 pinctrl-names = "default"; 637 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_uart2>; 638 pinctrl-0 = <&pinctrl_uart2>;
653 status = "okay"; 639 status = "okay";
654 }; 640 };
655 641
>> 642 /* off-board RS232 */
>> 643 &uart3 {
>> 644 pinctrl-names = "default";
>> 645 pinctrl-0 = <&pinctrl_uart3>;
>> 646 status = "okay";
>> 647 };
>> 648
656 &usbotg1 { 649 &usbotg1 {
657 dr_mode = "host"; 650 dr_mode = "host";
658 disable-over-current; 651 disable-over-current;
659 status = "okay"; 652 status = "okay";
660 }; 653 };
661 654
662 /* microSD */ 655 /* microSD */
663 &usdhc2 { 656 &usdhc2 {
664 pinctrl-names = "default", "state_100m 657 pinctrl-names = "default", "state_100mhz", "state_200mhz";
665 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 658 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
666 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 659 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
667 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 660 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
668 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 661 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
669 bus-width = <4>; 662 bus-width = <4>;
670 vmmc-supply = <®_3p3v>; 663 vmmc-supply = <®_3p3v>;
671 status = "okay"; 664 status = "okay";
672 }; 665 };
673 666
674 /* eMMC */ 667 /* eMMC */
675 &usdhc3 { 668 &usdhc3 {
676 pinctrl-names = "default", "state_100m 669 pinctrl-names = "default", "state_100mhz", "state_200mhz";
677 pinctrl-0 = <&pinctrl_usdhc3>; 670 pinctrl-0 = <&pinctrl_usdhc3>;
678 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 671 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
679 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 672 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
680 bus-width = <8>; 673 bus-width = <8>;
681 non-removable; 674 non-removable;
682 status = "okay"; 675 status = "okay";
683 }; 676 };
684 677
685 &wdog1 { 678 &wdog1 {
686 pinctrl-names = "default"; 679 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_wdog>; 680 pinctrl-0 = <&pinctrl_wdog>;
688 fsl,ext-reset-output; 681 fsl,ext-reset-output;
689 status = "okay"; 682 status = "okay";
690 }; 683 };
691 684
692 &iomuxc { 685 &iomuxc {
693 pinctrl-names = "default"; 686 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_hog>; 687 pinctrl-0 = <&pinctrl_hog>;
695 688
696 pinctrl_hog: hoggrp { 689 pinctrl_hog: hoggrp {
697 fsl,pins = < 690 fsl,pins = <
698 MX8MM_IOMUXC_GPIO1_IO1 691 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
699 MX8MM_IOMUXC_ECSPI2_MI 692 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
700 >; 693 >;
701 }; 694 };
702 695
703 pinctrl_accel: accelgrp { 696 pinctrl_accel: accelgrp {
704 fsl,pins = < 697 fsl,pins = <
705 MX8MM_IOMUXC_GPIO1_IO1 698 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
706 >; 699 >;
707 }; 700 };
708 701
709 pinctrl_fec1: fec1grp { 702 pinctrl_fec1: fec1grp {
710 fsl,pins = < 703 fsl,pins = <
711 MX8MM_IOMUXC_ENET_MDC_ 704 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
712 MX8MM_IOMUXC_ENET_MDIO 705 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
713 MX8MM_IOMUXC_ENET_TD3_ 706 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
714 MX8MM_IOMUXC_ENET_TD2_ 707 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
715 MX8MM_IOMUXC_ENET_TD1_ 708 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
716 MX8MM_IOMUXC_ENET_TD0_ 709 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
717 MX8MM_IOMUXC_ENET_RD3_ 710 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
718 MX8MM_IOMUXC_ENET_RD2_ 711 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
719 MX8MM_IOMUXC_ENET_RD1_ 712 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
720 MX8MM_IOMUXC_ENET_RD0_ 713 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
721 MX8MM_IOMUXC_ENET_TXC_ 714 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
722 MX8MM_IOMUXC_ENET_RXC_ 715 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
723 MX8MM_IOMUXC_ENET_RX_C 716 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
724 MX8MM_IOMUXC_ENET_TX_C 717 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
725 MX8MM_IOMUXC_SAI2_TXFS 718 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
726 MX8MM_IOMUXC_SAI2_TXC_ 719 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
727 >; 720 >;
728 }; 721 };
729 722
730 pinctrl_gpio_leds: gpioledsgrp { 723 pinctrl_gpio_leds: gpioledsgrp {
731 fsl,pins = < 724 fsl,pins = <
732 MX8MM_IOMUXC_GPIO1_IO0 725 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
733 MX8MM_IOMUXC_GPIO1_IO0 726 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
734 MX8MM_IOMUXC_GPIO1_IO1 727 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
735 MX8MM_IOMUXC_GPIO1_IO1 728 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
736 >; 729 >;
737 }; 730 };
738 731
739 pinctrl_gsc: gscgrp { 732 pinctrl_gsc: gscgrp {
740 fsl,pins = < 733 fsl,pins = <
741 MX8MM_IOMUXC_SAI2_TXD0 734 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
742 >; 735 >;
743 }; 736 };
744 737
745 pinctrl_i2c1: i2c1grp { 738 pinctrl_i2c1: i2c1grp {
746 fsl,pins = < 739 fsl,pins = <
747 MX8MM_IOMUXC_I2C1_SCL_ 740 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
748 MX8MM_IOMUXC_I2C1_SDA_ 741 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
749 >; 742 >;
750 }; 743 };
751 744
752 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
753 fsl,pins = < <<
754 MX8MM_IOMUXC_I2C1_SCL_ <<
755 MX8MM_IOMUXC_I2C1_SDA_ <<
756 >; <<
757 }; <<
758 <<
759 pinctrl_i2c2: i2c2grp { 745 pinctrl_i2c2: i2c2grp {
760 fsl,pins = < 746 fsl,pins = <
761 MX8MM_IOMUXC_I2C2_SCL_ 747 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
762 MX8MM_IOMUXC_I2C2_SDA_ 748 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
763 >; 749 >;
764 }; 750 };
765 751
766 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
767 fsl,pins = < <<
768 MX8MM_IOMUXC_I2C2_SCL_ <<
769 MX8MM_IOMUXC_I2C2_SDA_ <<
770 >; <<
771 }; <<
772 <<
773 pinctrl_i2c3: i2c3grp { 752 pinctrl_i2c3: i2c3grp {
774 fsl,pins = < 753 fsl,pins = <
775 MX8MM_IOMUXC_I2C3_SCL_ 754 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
776 MX8MM_IOMUXC_I2C3_SDA_ 755 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
777 >; 756 >;
778 }; 757 };
779 758
780 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
781 fsl,pins = < <<
782 MX8MM_IOMUXC_I2C3_SCL_ <<
783 MX8MM_IOMUXC_I2C3_SDA_ <<
784 >; <<
785 }; <<
786 <<
787 pinctrl_i2c4: i2c4grp { 759 pinctrl_i2c4: i2c4grp {
788 fsl,pins = < 760 fsl,pins = <
789 MX8MM_IOMUXC_I2C4_SCL_ 761 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
790 MX8MM_IOMUXC_I2C4_SDA_ 762 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
791 >; 763 >;
792 }; 764 };
793 765
794 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
795 fsl,pins = < <<
796 MX8MM_IOMUXC_I2C4_SCL_ <<
797 MX8MM_IOMUXC_I2C4_SDA_ <<
798 >; <<
799 }; <<
800 <<
801 pinctrl_pcie0: pciegrp { 766 pinctrl_pcie0: pciegrp {
802 fsl,pins = < 767 fsl,pins = <
803 MX8MM_IOMUXC_ECSPI2_MO 768 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
804 >; 769 >;
805 }; 770 };
806 771
807 pinctrl_pmic: pmicgrp { 772 pinctrl_pmic: pmicgrp {
808 fsl,pins = < 773 fsl,pins = <
809 MX8MM_IOMUXC_NAND_DATA 774 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
810 >; 775 >;
811 }; 776 };
812 777
813 pinctrl_uart1: uart1grp { 778 pinctrl_uart1: uart1grp {
814 fsl,pins = < 779 fsl,pins = <
815 MX8MM_IOMUXC_UART1_RXD 780 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
816 MX8MM_IOMUXC_UART1_TXD 781 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
817 MX8MM_IOMUXC_UART3_RXD <<
818 MX8MM_IOMUXC_UART3_TXD <<
819 >; 782 >;
820 }; 783 };
821 784
822 pinctrl_uart2: uart2grp { 785 pinctrl_uart2: uart2grp {
823 fsl,pins = < 786 fsl,pins = <
824 MX8MM_IOMUXC_UART2_RXD 787 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
825 MX8MM_IOMUXC_UART2_TXD 788 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>> 789 >;
>> 790 };
>> 791
>> 792 pinctrl_uart3: uart3grp {
>> 793 fsl,pins = <
>> 794 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
>> 795 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
826 >; 796 >;
827 }; 797 };
828 798
829 pinctrl_usdhc2: usdhc2grp { 799 pinctrl_usdhc2: usdhc2grp {
830 fsl,pins = < 800 fsl,pins = <
831 MX8MM_IOMUXC_SD2_CLK_U 801 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
832 MX8MM_IOMUXC_SD2_CMD_U 802 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
833 MX8MM_IOMUXC_SD2_DATA0 803 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
834 MX8MM_IOMUXC_SD2_DATA1 804 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
835 MX8MM_IOMUXC_SD2_DATA2 805 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
836 MX8MM_IOMUXC_SD2_DATA3 806 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
837 >; 807 >;
838 }; 808 };
839 809
840 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 810 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
841 fsl,pins = < 811 fsl,pins = <
842 MX8MM_IOMUXC_SD2_CLK_U 812 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
843 MX8MM_IOMUXC_SD2_CMD_U 813 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
844 MX8MM_IOMUXC_SD2_DATA0 814 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
845 MX8MM_IOMUXC_SD2_DATA1 815 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
846 MX8MM_IOMUXC_SD2_DATA2 816 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
847 MX8MM_IOMUXC_SD2_DATA3 817 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
848 >; 818 >;
849 }; 819 };
850 820
851 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 821 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
852 fsl,pins = < 822 fsl,pins = <
853 MX8MM_IOMUXC_SD2_CLK_U 823 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
854 MX8MM_IOMUXC_SD2_CMD_U 824 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
855 MX8MM_IOMUXC_SD2_DATA0 825 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
856 MX8MM_IOMUXC_SD2_DATA1 826 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
857 MX8MM_IOMUXC_SD2_DATA2 827 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
858 MX8MM_IOMUXC_SD2_DATA3 828 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
859 >; 829 >;
860 }; 830 };
861 831
862 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 832 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
863 fsl,pins = < 833 fsl,pins = <
864 MX8MM_IOMUXC_SD2_CD_B_ 834 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
865 MX8MM_IOMUXC_GPIO1_IO0 835 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
866 >; 836 >;
867 }; 837 };
868 838
869 pinctrl_usdhc3: usdhc3grp { 839 pinctrl_usdhc3: usdhc3grp {
870 fsl,pins = < 840 fsl,pins = <
871 MX8MM_IOMUXC_NAND_WE_B 841 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
872 MX8MM_IOMUXC_NAND_WP_B 842 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
873 MX8MM_IOMUXC_NAND_DATA 843 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
874 MX8MM_IOMUXC_NAND_DATA 844 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
875 MX8MM_IOMUXC_NAND_DATA 845 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
876 MX8MM_IOMUXC_NAND_DATA 846 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
877 MX8MM_IOMUXC_NAND_RE_B 847 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
878 MX8MM_IOMUXC_NAND_CE2_ 848 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
879 MX8MM_IOMUXC_NAND_CE3_ 849 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
880 MX8MM_IOMUXC_NAND_CLE_ 850 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
881 MX8MM_IOMUXC_NAND_CE1_ 851 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
882 >; 852 >;
883 }; 853 };
884 854
885 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 855 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
886 fsl,pins = < 856 fsl,pins = <
887 MX8MM_IOMUXC_NAND_WE_B 857 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
888 MX8MM_IOMUXC_NAND_WP_B 858 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
889 MX8MM_IOMUXC_NAND_DATA 859 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
890 MX8MM_IOMUXC_NAND_DATA 860 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
891 MX8MM_IOMUXC_NAND_DATA 861 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
892 MX8MM_IOMUXC_NAND_DATA 862 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
893 MX8MM_IOMUXC_NAND_RE_B 863 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
894 MX8MM_IOMUXC_NAND_CE2_ 864 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
895 MX8MM_IOMUXC_NAND_CE3_ 865 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
896 MX8MM_IOMUXC_NAND_CLE_ 866 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
897 MX8MM_IOMUXC_NAND_CE1_ 867 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
898 >; 868 >;
899 }; 869 };
900 870
901 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 871 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
902 fsl,pins = < 872 fsl,pins = <
903 MX8MM_IOMUXC_NAND_WE_B 873 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
904 MX8MM_IOMUXC_NAND_WP_B 874 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
905 MX8MM_IOMUXC_NAND_DATA 875 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
906 MX8MM_IOMUXC_NAND_DATA 876 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
907 MX8MM_IOMUXC_NAND_DATA 877 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
908 MX8MM_IOMUXC_NAND_DATA 878 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
909 MX8MM_IOMUXC_NAND_RE_B 879 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
910 MX8MM_IOMUXC_NAND_CE2_ 880 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
911 MX8MM_IOMUXC_NAND_CE3_ 881 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
912 MX8MM_IOMUXC_NAND_CLE_ 882 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
913 MX8MM_IOMUXC_NAND_CE1_ 883 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
914 >; 884 >;
915 }; 885 };
916 886
917 pinctrl_wdog: wdoggrp { 887 pinctrl_wdog: wdoggrp {
918 fsl,pins = < 888 fsl,pins = <
919 MX8MM_IOMUXC_GPIO1_IO0 889 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
920 >; 890 >;
921 }; 891 };
922 }; 892 };
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