1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy-imx8-pcie.h> !! 6 #include "dt-bindings/phy/phy-imx8-pcie.h"
7 #include <dt-bindings/pwm/pwm.h> !! 7 #include "dt-bindings/pwm/pwm.h"
8 #include "imx8mm.dtsi" 8 #include "imx8mm.dtsi"
9 #include "imx8mm-overdrive.dtsi" <<
10 9
11 / { 10 / {
12 chosen { 11 chosen {
13 stdout-path = &uart1; 12 stdout-path = &uart1;
14 }; 13 };
15 14
16 aliases { 15 aliases {
17 rtc0 = &rtc_i2c; 16 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc; 17 rtc1 = &snvs_rtc;
19 }; 18 };
20 19
21 backlight: backlight { 20 backlight: backlight {
22 compatible = "pwm-backlight"; 21 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 8 22 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4> 23 default-brightness-level = <4>;
25 /* Verdin I2S_2_D_OUT (DSI_1_B 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
26 enable-gpios = <&gpio3 24 GPIO 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default"; 26 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_i2s_2_d_ 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
29 power-supply = <®_3p3v>; 28 power-supply = <®_3p3v>;
30 /* Verdin PWM_3_DSI/PWM_3_DSI_ 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
31 pwms = <&pwm1 0 6666667 PWM_PO 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 /* Fixed clock dedicated to SPI CAN co 34 /* Fixed clock dedicated to SPI CAN controller */
36 clk40m: oscillator { 35 clk40m: oscillator {
37 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
38 #clock-cells = <0>; 37 #clock-cells = <0>;
39 clock-frequency = <40000000>; 38 clock-frequency = <40000000>;
40 }; 39 };
41 40
42 gpio-keys { 41 gpio-keys {
43 compatible = "gpio-keys"; 42 compatible = "gpio-keys";
44 pinctrl-names = "default"; 43 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_key 44 pinctrl-0 = <&pinctrl_gpio_keys>;
46 45
47 key-wakeup { !! 46 wakeup {
48 debounce-interval = <1 47 debounce-interval = <10>;
49 /* Verdin CTRL_WAKE1_M 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
50 gpios = <&gpio4 28 GPI 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 label = "Wake-Up"; 50 label = "Wake-Up";
52 linux,code = <KEY_WAKE 51 linux,code = <KEY_WAKEUP>;
53 wakeup-source; 52 wakeup-source;
54 }; 53 };
55 }; 54 };
56 55
57 hdmi_connector: hdmi-connector { <<
58 compatible = "hdmi-connector"; <<
59 ddc-i2c-bus = <&i2c2>; <<
60 /* Verdin PWM_3_DSI (SODIMM 19 <<
61 hpd-gpios = <&gpio1 1 GPIO_ACT <<
62 label = "hdmi"; <<
63 pinctrl-names = "default"; <<
64 pinctrl-0 = <&pinctrl_pwm_3_ds <<
65 type = "a"; <<
66 status = "disabled"; <<
67 }; <<
68 <<
69 panel_lvds: panel-lvds { <<
70 compatible = "panel-lvds"; <<
71 backlight = <&backlight>; <<
72 data-mapping = "vesa-24"; <<
73 status = "disabled"; <<
74 }; <<
75 <<
76 /* Carrier Board Supplies */ 56 /* Carrier Board Supplies */
77 reg_1p8v: regulator-1p8v { 57 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed" 58 compatible = "regulator-fixed";
79 regulator-max-microvolt = <180 59 regulator-max-microvolt = <1800000>;
80 regulator-min-microvolt = <180 60 regulator-min-microvolt = <1800000>;
81 regulator-name = "+V1.8_SW"; 61 regulator-name = "+V1.8_SW";
82 }; 62 };
83 63
84 reg_3p3v: regulator-3p3v { 64 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed" 65 compatible = "regulator-fixed";
86 regulator-max-microvolt = <330 66 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <330 67 regulator-min-microvolt = <3300000>;
88 regulator-name = "+V3.3_SW"; 68 regulator-name = "+V3.3_SW";
89 }; 69 };
90 70
91 reg_5p0v: regulator-5p0v { 71 reg_5p0v: regulator-5p0v {
92 compatible = "regulator-fixed" 72 compatible = "regulator-fixed";
93 regulator-max-microvolt = <500 73 regulator-max-microvolt = <5000000>;
94 regulator-min-microvolt = <500 74 regulator-min-microvolt = <5000000>;
95 regulator-name = "+V5_SW"; 75 regulator-name = "+V5_SW";
96 }; 76 };
97 77
98 /* Non PMIC On-module Supplies */ 78 /* Non PMIC On-module Supplies */
99 reg_ethphy: regulator-ethphy { 79 reg_ethphy: regulator-ethphy {
100 compatible = "regulator-fixed" 80 compatible = "regulator-fixed";
101 enable-active-high; 81 enable-active-high;
102 gpio = <&gpio2 20 GPIO_ACTIVE_ 82 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
103 off-on-delay-us = <500000>; !! 83 off-on-delay = <500000>;
104 pinctrl-names = "default"; 84 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_eth> 85 pinctrl-0 = <&pinctrl_reg_eth>;
106 regulator-always-on; <<
107 regulator-boot-on; 86 regulator-boot-on;
108 regulator-max-microvolt = <330 87 regulator-max-microvolt = <3300000>;
109 regulator-min-microvolt = <330 88 regulator-min-microvolt = <3300000>;
110 regulator-name = "On-module +V 89 regulator-name = "On-module +V3.3_ETH";
111 startup-delay-us = <200000>; 90 startup-delay-us = <200000>;
112 }; 91 };
113 92
114 /* <<
115 * By default we enable CTRL_SLEEP_MOC <<
116 * peripherals on the carrier board po <<
117 * If more granularity or power saving <<
118 * in the carrier board device tree fi <<
119 */ <<
120 reg_force_sleep_moci: regulator-force- <<
121 compatible = "regulator-fixed" <<
122 enable-active-high; <<
123 /* Verdin CTRL_SLEEP_MOCI# (SO <<
124 gpio = <&gpio5 1 GPIO_ACTIVE_H <<
125 regulator-always-on; <<
126 regulator-boot-on; <<
127 regulator-name = "CTRL_SLEEP_M <<
128 }; <<
129 <<
130 reg_usb_otg1_vbus: regulator-usb-otg1 93 reg_usb_otg1_vbus: regulator-usb-otg1 {
131 compatible = "regulator-fixed" 94 compatible = "regulator-fixed";
132 enable-active-high; 95 enable-active-high;
133 /* Verdin USB_1_EN (SODIMM 155 96 /* Verdin USB_1_EN (SODIMM 155) */
134 gpio = <&gpio1 12 GPIO_ACTIVE_ 97 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
135 pinctrl-names = "default"; 98 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_usb1 99 pinctrl-0 = <&pinctrl_reg_usb1_en>;
137 regulator-max-microvolt = <500 100 regulator-max-microvolt = <5000000>;
138 regulator-min-microvolt = <500 101 regulator-min-microvolt = <5000000>;
139 regulator-name = "USB_1_EN"; 102 regulator-name = "USB_1_EN";
140 }; 103 };
141 104
142 reg_usb_otg2_vbus: regulator-usb-otg2 105 reg_usb_otg2_vbus: regulator-usb-otg2 {
143 compatible = "regulator-fixed" 106 compatible = "regulator-fixed";
144 enable-active-high; 107 enable-active-high;
145 /* Verdin USB_2_EN (SODIMM 185 108 /* Verdin USB_2_EN (SODIMM 185) */
146 gpio = <&gpio1 14 GPIO_ACTIVE_ 109 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
147 pinctrl-names = "default"; 110 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb2 111 pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 regulator-max-microvolt = <500 112 regulator-max-microvolt = <5000000>;
150 regulator-min-microvolt = <500 113 regulator-min-microvolt = <5000000>;
151 regulator-name = "USB_2_EN"; 114 regulator-name = "USB_2_EN";
152 }; 115 };
153 116
154 reg_usdhc2_vmmc: regulator-usdhc2 { 117 reg_usdhc2_vmmc: regulator-usdhc2 {
155 compatible = "regulator-fixed" 118 compatible = "regulator-fixed";
156 enable-active-high; 119 enable-active-high;
157 /* Verdin SD_1_PWR_EN (SODIMM 120 /* Verdin SD_1_PWR_EN (SODIMM 76) */
158 gpio = <&gpio3 5 GPIO_ACTIVE_H 121 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
159 off-on-delay-us = <100000>; !! 122 off-on-delay = <100000>;
160 pinctrl-names = "default"; 123 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc2_p 124 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
162 regulator-max-microvolt = <330 125 regulator-max-microvolt = <3300000>;
163 regulator-min-microvolt = <330 126 regulator-min-microvolt = <3300000>;
164 regulator-name = "+V3.3_SD"; 127 regulator-name = "+V3.3_SD";
165 startup-delay-us = <2000>; 128 startup-delay-us = <2000>;
166 }; 129 };
167 130
168 reserved-memory { 131 reserved-memory {
169 #address-cells = <2>; 132 #address-cells = <2>;
170 #size-cells = <2>; 133 #size-cells = <2>;
171 ranges; 134 ranges;
172 135
173 /* Use the kernel configuratio 136 /* Use the kernel configuration settings instead */
174 /delete-node/ linux,cma; 137 /delete-node/ linux,cma;
175 }; 138 };
176 }; 139 };
177 140
178 &A53_0 { 141 &A53_0 {
179 cpu-supply = <®_vdd_arm>; 142 cpu-supply = <®_vdd_arm>;
180 }; 143 };
181 144
182 &A53_1 { 145 &A53_1 {
183 cpu-supply = <®_vdd_arm>; 146 cpu-supply = <®_vdd_arm>;
184 }; 147 };
185 148
186 &A53_2 { 149 &A53_2 {
187 cpu-supply = <®_vdd_arm>; 150 cpu-supply = <®_vdd_arm>;
188 }; 151 };
189 152
190 &A53_3 { 153 &A53_3 {
191 cpu-supply = <®_vdd_arm>; 154 cpu-supply = <®_vdd_arm>;
192 }; 155 };
193 156
194 &cpu_alert0 { <<
195 temperature = <95000>; <<
196 }; <<
197 <<
198 &cpu_crit0 { <<
199 temperature = <105000>; <<
200 }; <<
201 <<
202 &ddrc { 157 &ddrc {
203 operating-points-v2 = <&ddrc_opp_table 158 operating-points-v2 = <&ddrc_opp_table>;
204 159
205 ddrc_opp_table: opp-table { 160 ddrc_opp_table: opp-table {
206 compatible = "operating-points 161 compatible = "operating-points-v2";
207 162
208 opp-25000000 { !! 163 opp-25M {
209 opp-hz = /bits/ 64 <25 164 opp-hz = /bits/ 64 <25000000>;
210 }; 165 };
211 166
212 opp-100000000 { !! 167 opp-100M {
213 opp-hz = /bits/ 64 <10 168 opp-hz = /bits/ 64 <100000000>;
214 }; 169 };
215 170
216 opp-750000000 { !! 171 opp-750M {
217 opp-hz = /bits/ 64 <75 172 opp-hz = /bits/ 64 <750000000>;
218 }; 173 };
219 }; 174 };
220 }; 175 };
221 176
222 /* Verdin SPI_1 */ 177 /* Verdin SPI_1 */
223 &ecspi2 { 178 &ecspi2 {
224 #address-cells = <1>; 179 #address-cells = <1>;
225 #size-cells = <0>; 180 #size-cells = <0>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 181 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 pinctrl-names = "default"; 182 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ecspi2>; 183 pinctrl-0 = <&pinctrl_ecspi2>;
229 }; 184 };
230 185
231 /* On-module SPI */ !! 186 /* Verdin CAN_1 (On-module) */
232 &ecspi3 { 187 &ecspi3 {
233 #address-cells = <1>; 188 #address-cells = <1>;
234 #size-cells = <0>; 189 #size-cells = <0>;
235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW> !! 190 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
236 pinctrl-names = "default"; 191 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi3>, <&pinct !! 192 pinctrl-0 = <&pinctrl_ecspi3>;
238 status = "okay"; 193 status = "okay";
239 194
240 /* Verdin CAN_1 */ <<
241 can1: can@0 { 195 can1: can@0 {
242 compatible = "microchip,mcp251 196 compatible = "microchip,mcp251xfd";
243 clocks = <&clk40m>; 197 clocks = <&clk40m>;
244 interrupts-extended = <&gpio1 198 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
245 pinctrl-names = "default"; 199 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_can1_int 200 pinctrl-0 = <&pinctrl_can1_int>;
247 reg = <0>; 201 reg = <0>;
248 spi-max-frequency = <8500000>; 202 spi-max-frequency = <8500000>;
249 }; 203 };
250 <<
251 verdin_som_tpm: tpm@1 { <<
252 compatible = "atmel,attpm20p", <<
253 reg = <0x1>; <<
254 spi-max-frequency = <36000000> <<
255 }; <<
256 }; 204 };
257 205
258 /* Verdin ETH_1 (On-module PHY) */ 206 /* Verdin ETH_1 (On-module PHY) */
259 &fec1 { 207 &fec1 {
260 fsl,magic-packet; 208 fsl,magic-packet;
261 phy-handle = <ðphy0>; 209 phy-handle = <ðphy0>;
262 phy-mode = "rgmii-id"; 210 phy-mode = "rgmii-id";
263 phy-supply = <®_ethphy>; 211 phy-supply = <®_ethphy>;
264 pinctrl-names = "default", "sleep"; 212 pinctrl-names = "default", "sleep";
265 pinctrl-0 = <&pinctrl_fec1>; 213 pinctrl-0 = <&pinctrl_fec1>;
266 pinctrl-1 = <&pinctrl_fec1_sleep>; 214 pinctrl-1 = <&pinctrl_fec1_sleep>;
267 215
268 mdio { 216 mdio {
269 #address-cells = <1>; 217 #address-cells = <1>;
270 #size-cells = <0>; 218 #size-cells = <0>;
271 219
272 ethphy0: ethernet-phy@7 { 220 ethphy0: ethernet-phy@7 {
273 compatible = "ethernet 221 compatible = "ethernet-phy-ieee802.3-c22";
274 interrupt-parent = <&g 222 interrupt-parent = <&gpio1>;
275 interrupts = <10 IRQ_T 223 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
276 micrel,led-mode = <0>; 224 micrel,led-mode = <0>;
277 reg = <7>; 225 reg = <7>;
278 }; 226 };
279 }; 227 };
280 }; 228 };
281 229
282 /* Verdin QSPI_1 */ 230 /* Verdin QSPI_1 */
283 &flexspi { 231 &flexspi {
284 pinctrl-names = "default"; 232 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexspi0>; 233 pinctrl-0 = <&pinctrl_flexspi0>;
286 }; 234 };
287 235
288 &gpio1 { 236 &gpio1 {
289 gpio-line-names = "SODIMM_216", 237 gpio-line-names = "SODIMM_216",
290 "SODIMM_19", 238 "SODIMM_19",
291 "", 239 "",
292 "", 240 "",
293 "", 241 "",
294 "", 242 "",
295 "", 243 "",
296 "", 244 "",
297 "SODIMM_220", 245 "SODIMM_220",
298 "SODIMM_222", 246 "SODIMM_222",
299 "", 247 "",
300 "SODIMM_218", 248 "SODIMM_218",
301 "SODIMM_155", 249 "SODIMM_155",
302 "SODIMM_157", 250 "SODIMM_157",
303 "SODIMM_185", 251 "SODIMM_185",
304 "SODIMM_187"; 252 "SODIMM_187";
305 }; 253 };
306 254
307 &gpio2 { 255 &gpio2 {
308 gpio-line-names = "", 256 gpio-line-names = "",
309 "", 257 "",
310 "", 258 "",
311 "", 259 "",
312 "", 260 "",
313 "", 261 "",
314 "", 262 "",
315 "", 263 "",
316 "", 264 "",
317 "", 265 "",
318 "", 266 "",
319 "", 267 "",
320 "SODIMM_84", 268 "SODIMM_84",
321 "SODIMM_78", 269 "SODIMM_78",
322 "SODIMM_74", 270 "SODIMM_74",
323 "SODIMM_80", 271 "SODIMM_80",
324 "SODIMM_82", 272 "SODIMM_82",
325 "SODIMM_70", 273 "SODIMM_70",
326 "SODIMM_72"; 274 "SODIMM_72";
327 }; 275 };
328 276
329 &gpio5 { 277 &gpio5 {
330 gpio-line-names = "SODIMM_131", 278 gpio-line-names = "SODIMM_131",
331 "", 279 "",
332 "SODIMM_91", 280 "SODIMM_91",
333 "SODIMM_16", 281 "SODIMM_16",
334 "SODIMM_15", 282 "SODIMM_15",
335 "SODIMM_208", 283 "SODIMM_208",
336 "SODIMM_137", 284 "SODIMM_137",
337 "SODIMM_139", 285 "SODIMM_139",
338 "SODIMM_141", 286 "SODIMM_141",
339 "SODIMM_143", 287 "SODIMM_143",
340 "SODIMM_196", 288 "SODIMM_196",
341 "SODIMM_200", 289 "SODIMM_200",
342 "SODIMM_198", 290 "SODIMM_198",
343 "SODIMM_202", 291 "SODIMM_202",
344 "", 292 "",
345 "", 293 "",
346 "SODIMM_55", 294 "SODIMM_55",
347 "SODIMM_53", 295 "SODIMM_53",
348 "SODIMM_95", 296 "SODIMM_95",
349 "SODIMM_93", 297 "SODIMM_93",
350 "SODIMM_14", 298 "SODIMM_14",
351 "SODIMM_12", 299 "SODIMM_12",
352 "", 300 "",
353 "", 301 "",
354 "", 302 "",
355 "", 303 "",
356 "SODIMM_210", 304 "SODIMM_210",
357 "SODIMM_212", 305 "SODIMM_212",
358 "SODIMM_151", 306 "SODIMM_151",
359 "SODIMM_153"; 307 "SODIMM_153";
>> 308
>> 309 ctrl-sleep-moci-hog {
>> 310 gpio-hog;
>> 311 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
>> 312 gpios = <1 GPIO_ACTIVE_HIGH>;
>> 313 line-name = "CTRL_SLEEP_MOCI#";
>> 314 output-high;
>> 315 pinctrl-names = "default";
>> 316 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
>> 317 };
360 }; 318 };
361 319
362 /* On-module I2C */ 320 /* On-module I2C */
363 &i2c1 { 321 &i2c1 {
364 clock-frequency = <400000>; 322 clock-frequency = <400000>;
365 pinctrl-names = "default", "gpio"; 323 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c1>; 324 pinctrl-0 = <&pinctrl_i2c1>;
367 pinctrl-1 = <&pinctrl_i2c1_gpio>; 325 pinctrl-1 = <&pinctrl_i2c1_gpio>;
368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 326 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 327 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
370 status = "okay"; 328 status = "okay";
371 329
372 pca9450: pmic@25 { 330 pca9450: pmic@25 {
373 compatible = "nxp,pca9450a"; 331 compatible = "nxp,pca9450a";
374 interrupt-parent = <&gpio1>; 332 interrupt-parent = <&gpio1>;
375 /* PMIC PCA9450 PMIC_nINT GPIO 333 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
376 interrupts = <3 IRQ_TYPE_LEVEL 334 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
377 pinctrl-names = "default"; 335 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pmic>; 336 pinctrl-0 = <&pinctrl_pmic>;
379 reg = <0x25>; 337 reg = <0x25>;
>> 338 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
380 339
381 /* 340 /*
382 * The bootloader is expected 341 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
383 * behind this PMIC. 342 * behind this PMIC.
384 */ 343 */
385 344
386 regulators { 345 regulators {
387 reg_vdd_soc: BUCK1 { 346 reg_vdd_soc: BUCK1 {
388 nxp,dvs-run-vo 347 nxp,dvs-run-voltage = <850000>;
389 nxp,dvs-standb 348 nxp,dvs-standby-voltage = <800000>;
390 regulator-alwa 349 regulator-always-on;
391 regulator-boot 350 regulator-boot-on;
392 regulator-max- 351 regulator-max-microvolt = <850000>;
393 regulator-min- 352 regulator-min-microvolt = <800000>;
394 regulator-name 353 regulator-name = "On-module +VDD_SOC (BUCK1)";
395 regulator-ramp 354 regulator-ramp-delay = <3125>;
396 }; 355 };
397 356
398 reg_vdd_arm: BUCK2 { 357 reg_vdd_arm: BUCK2 {
399 nxp,dvs-run-vo 358 nxp,dvs-run-voltage = <950000>;
400 nxp,dvs-standb 359 nxp,dvs-standby-voltage = <850000>;
401 regulator-alwa 360 regulator-always-on;
402 regulator-boot 361 regulator-boot-on;
403 regulator-max- 362 regulator-max-microvolt = <1050000>;
404 regulator-min- 363 regulator-min-microvolt = <805000>;
405 regulator-name 364 regulator-name = "On-module +VDD_ARM (BUCK2)";
406 regulator-ramp 365 regulator-ramp-delay = <3125>;
407 }; 366 };
408 367
409 reg_vdd_dram: BUCK3 { 368 reg_vdd_dram: BUCK3 {
410 regulator-alwa 369 regulator-always-on;
411 regulator-boot 370 regulator-boot-on;
412 regulator-max- 371 regulator-max-microvolt = <1000000>;
413 regulator-min- 372 regulator-min-microvolt = <805000>;
414 regulator-name 373 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
415 }; 374 };
416 375
417 reg_vdd_3v3: BUCK4 { 376 reg_vdd_3v3: BUCK4 {
418 regulator-alwa 377 regulator-always-on;
419 regulator-boot 378 regulator-boot-on;
420 regulator-max- 379 regulator-max-microvolt = <3300000>;
421 regulator-min- 380 regulator-min-microvolt = <3300000>;
422 regulator-name 381 regulator-name = "On-module +V3.3 (BUCK4)";
423 }; 382 };
424 383
425 reg_vdd_1v8: BUCK5 { 384 reg_vdd_1v8: BUCK5 {
426 regulator-alwa 385 regulator-always-on;
427 regulator-boot 386 regulator-boot-on;
428 regulator-max- 387 regulator-max-microvolt = <1800000>;
429 regulator-min- 388 regulator-min-microvolt = <1800000>;
430 regulator-name 389 regulator-name = "PWR_1V8_MOCI (BUCK5)";
431 }; 390 };
432 391
433 reg_nvcc_dram: BUCK6 { 392 reg_nvcc_dram: BUCK6 {
434 regulator-alwa 393 regulator-always-on;
435 regulator-boot 394 regulator-boot-on;
436 regulator-max- 395 regulator-max-microvolt = <1100000>;
437 regulator-min- 396 regulator-min-microvolt = <1100000>;
438 regulator-name 397 regulator-name = "On-module +VDD_DDR (BUCK6)";
439 }; 398 };
440 399
441 reg_nvcc_snvs: LDO1 { 400 reg_nvcc_snvs: LDO1 {
442 regulator-alwa 401 regulator-always-on;
443 regulator-boot 402 regulator-boot-on;
444 regulator-max- 403 regulator-max-microvolt = <1800000>;
445 regulator-min- 404 regulator-min-microvolt = <1800000>;
446 regulator-name 405 regulator-name = "On-module +V1.8_SNVS (LDO1)";
447 }; 406 };
448 407
449 reg_vdd_snvs: LDO2 { 408 reg_vdd_snvs: LDO2 {
450 regulator-alwa 409 regulator-always-on;
451 regulator-boot 410 regulator-boot-on;
452 regulator-max- 411 regulator-max-microvolt = <800000>;
453 regulator-min- 412 regulator-min-microvolt = <800000>;
454 regulator-name 413 regulator-name = "On-module +V0.8_SNVS (LDO2)";
455 }; 414 };
456 415
457 reg_vdda: LDO3 { 416 reg_vdda: LDO3 {
458 regulator-alwa 417 regulator-always-on;
459 regulator-boot 418 regulator-boot-on;
460 regulator-max- 419 regulator-max-microvolt = <1800000>;
461 regulator-min- 420 regulator-min-microvolt = <1800000>;
462 regulator-name 421 regulator-name = "On-module +V1.8A (LDO3)";
463 }; 422 };
464 423
465 reg_vdd_phy: LDO4 { 424 reg_vdd_phy: LDO4 {
466 regulator-alwa 425 regulator-always-on;
467 regulator-boot 426 regulator-boot-on;
468 regulator-max- 427 regulator-max-microvolt = <900000>;
469 regulator-min- 428 regulator-min-microvolt = <900000>;
470 regulator-name 429 regulator-name = "On-module +V0.9_MIPI (LDO4)";
471 }; 430 };
472 431
473 reg_nvcc_sd: LDO5 { 432 reg_nvcc_sd: LDO5 {
474 regulator-max- 433 regulator-max-microvolt = <3300000>;
475 regulator-min- 434 regulator-min-microvolt = <1800000>;
476 regulator-name 435 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
477 }; 436 };
478 }; 437 };
479 }; 438 };
480 439
481 rtc_i2c: rtc@32 { 440 rtc_i2c: rtc@32 {
482 compatible = "epson,rx8130"; 441 compatible = "epson,rx8130";
483 reg = <0x32>; 442 reg = <0x32>;
484 }; 443 };
485 444
486 adc@49 { 445 adc@49 {
487 compatible = "ti,ads1015"; 446 compatible = "ti,ads1015";
488 reg = <0x49>; 447 reg = <0x49>;
489 #address-cells = <1>; 448 #address-cells = <1>;
490 #size-cells = <0>; 449 #size-cells = <0>;
491 450
492 /* Verdin I2C_1 (ADC_4 - ADC_3 451 /* Verdin I2C_1 (ADC_4 - ADC_3) */
493 channel@0 { 452 channel@0 {
494 reg = <0>; 453 reg = <0>;
495 ti,datarate = <4>; 454 ti,datarate = <4>;
496 ti,gain = <2>; 455 ti,gain = <2>;
497 }; 456 };
498 457
499 /* Verdin I2C_1 (ADC_4 - ADC_1 458 /* Verdin I2C_1 (ADC_4 - ADC_1) */
500 channel@1 { 459 channel@1 {
501 reg = <1>; 460 reg = <1>;
502 ti,datarate = <4>; 461 ti,datarate = <4>;
503 ti,gain = <2>; 462 ti,gain = <2>;
504 }; 463 };
505 464
506 /* Verdin I2C_1 (ADC_3 - ADC_1 465 /* Verdin I2C_1 (ADC_3 - ADC_1) */
507 channel@2 { 466 channel@2 {
508 reg = <2>; 467 reg = <2>;
509 ti,datarate = <4>; 468 ti,datarate = <4>;
510 ti,gain = <2>; 469 ti,gain = <2>;
511 }; 470 };
512 471
513 /* Verdin I2C_1 (ADC_2 - ADC_1 472 /* Verdin I2C_1 (ADC_2 - ADC_1) */
514 channel@3 { 473 channel@3 {
515 reg = <3>; 474 reg = <3>;
516 ti,datarate = <4>; 475 ti,datarate = <4>;
517 ti,gain = <2>; 476 ti,gain = <2>;
518 }; 477 };
519 478
520 /* Verdin I2C_1 ADC_4 */ 479 /* Verdin I2C_1 ADC_4 */
521 channel@4 { 480 channel@4 {
522 reg = <4>; 481 reg = <4>;
523 ti,datarate = <4>; 482 ti,datarate = <4>;
524 ti,gain = <2>; 483 ti,gain = <2>;
525 }; 484 };
526 485
527 /* Verdin I2C_1 ADC_3 */ 486 /* Verdin I2C_1 ADC_3 */
528 channel@5 { 487 channel@5 {
529 reg = <5>; 488 reg = <5>;
530 ti,datarate = <4>; 489 ti,datarate = <4>;
531 ti,gain = <2>; 490 ti,gain = <2>;
532 }; 491 };
533 492
534 /* Verdin I2C_1 ADC_2 */ 493 /* Verdin I2C_1 ADC_2 */
535 channel@6 { 494 channel@6 {
536 reg = <6>; 495 reg = <6>;
537 ti,datarate = <4>; 496 ti,datarate = <4>;
538 ti,gain = <2>; 497 ti,gain = <2>;
539 }; 498 };
540 499
541 /* Verdin I2C_1 ADC_1 */ 500 /* Verdin I2C_1 ADC_1 */
542 channel@7 { 501 channel@7 {
543 reg = <7>; 502 reg = <7>;
544 ti,datarate = <4>; 503 ti,datarate = <4>;
545 ti,gain = <2>; 504 ti,gain = <2>;
546 }; 505 };
547 }; 506 };
548 507
549 eeprom@50 { 508 eeprom@50 {
550 compatible = "st,24c02"; 509 compatible = "st,24c02";
551 pagesize = <16>; 510 pagesize = <16>;
552 reg = <0x50>; 511 reg = <0x50>;
553 }; 512 };
554 }; 513 };
555 514
556 /* Verdin I2C_2_DSI */ 515 /* Verdin I2C_2_DSI */
557 &i2c2 { 516 &i2c2 {
558 clock-frequency = <400000>; !! 517 clock-frequency = <10000>;
559 pinctrl-names = "default", "gpio"; 518 pinctrl-names = "default", "gpio";
560 pinctrl-0 = <&pinctrl_i2c2>; 519 pinctrl-0 = <&pinctrl_i2c2>;
561 pinctrl-1 = <&pinctrl_i2c2_gpio>; 520 pinctrl-1 = <&pinctrl_i2c2_gpio>;
562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 521 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 522 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
564 status = "disabled"; 523 status = "disabled";
565 }; 524 };
566 525
567 /* Verdin I2C_3_HDMI N/A */ 526 /* Verdin I2C_3_HDMI N/A */
568 527
569 /* Verdin I2C_4_CSI */ 528 /* Verdin I2C_4_CSI */
570 &i2c3 { 529 &i2c3 {
571 clock-frequency = <400000>; 530 clock-frequency = <400000>;
572 pinctrl-names = "default", "gpio"; 531 pinctrl-names = "default", "gpio";
573 pinctrl-0 = <&pinctrl_i2c3>; 532 pinctrl-0 = <&pinctrl_i2c3>;
574 pinctrl-1 = <&pinctrl_i2c3_gpio>; 533 pinctrl-1 = <&pinctrl_i2c3_gpio>;
575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 534 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 535 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577 }; 536 };
578 537
579 /* Verdin I2C_1 */ 538 /* Verdin I2C_1 */
580 &i2c4 { 539 &i2c4 {
581 clock-frequency = <400000>; 540 clock-frequency = <400000>;
582 pinctrl-names = "default", "gpio"; 541 pinctrl-names = "default", "gpio";
583 pinctrl-0 = <&pinctrl_i2c4>; 542 pinctrl-0 = <&pinctrl_i2c4>;
584 pinctrl-1 = <&pinctrl_i2c4_gpio>; 543 pinctrl-1 = <&pinctrl_i2c4_gpio>;
585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 544 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 545 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
587 546
588 gpio_expander_21: gpio-expander@21 { 547 gpio_expander_21: gpio-expander@21 {
589 compatible = "nxp,pcal6416"; 548 compatible = "nxp,pcal6416";
590 #gpio-cells = <2>; 549 #gpio-cells = <2>;
591 gpio-controller; 550 gpio-controller;
592 reg = <0x21>; 551 reg = <0x21>;
593 vcc-supply = <®_3p3v>; 552 vcc-supply = <®_3p3v>;
594 status = "disabled"; 553 status = "disabled";
595 }; 554 };
596 555
597 lvds_ti_sn65dsi84: bridge@2c { !! 556 lvds_ti_sn65dsi83: bridge@2c {
598 compatible = "ti,sn65dsi84"; !! 557 compatible = "ti,sn65dsi83";
599 /* Verdin GPIO_9_DSI (SN65DSI8 558 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
600 /* Verdin GPIO_10_DSI (SODIMM 559 /* Verdin GPIO_10_DSI (SODIMM 21) */
601 enable-gpios = <&gpio3 3 GPIO_ 560 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
602 pinctrl-names = "default"; 561 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_gpio_10_ 562 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
604 reg = <0x2c>; 563 reg = <0x2c>;
605 status = "disabled"; 564 status = "disabled";
606 }; 565 };
607 566
608 /* Current measurement into module VCC 567 /* Current measurement into module VCC */
609 hwmon: hwmon@40 { 568 hwmon: hwmon@40 {
610 compatible = "ti,ina219"; 569 compatible = "ti,ina219";
611 reg = <0x40>; 570 reg = <0x40>;
612 shunt-resistor = <10000>; 571 shunt-resistor = <10000>;
613 status = "disabled"; 572 status = "disabled";
614 }; 573 };
615 574
616 hdmi_lontium_lt8912: hdmi@48 { 575 hdmi_lontium_lt8912: hdmi@48 {
617 compatible = "lontium,lt8912b" 576 compatible = "lontium,lt8912b";
618 pinctrl-names = "default"; 577 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_gpio_10_ !! 578 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
620 reg = <0x48>; 579 reg = <0x48>;
621 /* Verdin GPIO_9_DSI (LT8912 I 580 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
622 /* Verdin GPIO_10_DSI (SODIMM 581 /* Verdin GPIO_10_DSI (SODIMM 21) */
623 reset-gpios = <&gpio3 3 GPIO_A 582 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
624 status = "disabled"; 583 status = "disabled";
625 }; 584 };
626 585
627 atmel_mxt_ts: touch@4a { 586 atmel_mxt_ts: touch@4a {
628 compatible = "atmel,maxtouch"; 587 compatible = "atmel,maxtouch";
629 /* 588 /*
630 * Verdin GPIO_9_DSI 589 * Verdin GPIO_9_DSI
631 * (TOUCH_INT#, SODIMM 17, als !! 590 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
632 */ 591 */
633 interrupt-parent = <&gpio3>; 592 interrupt-parent = <&gpio3>;
634 interrupts = <15 IRQ_TYPE_EDGE 593 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
635 pinctrl-names = "default"; 594 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_gpio_9_d 595 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
637 reg = <0x4a>; 596 reg = <0x4a>;
638 /* Verdin I2S_2_BCLK (TOUCH_RE 597 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
639 reset-gpios = <&gpio3 23 GPIO_ 598 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
640 status = "disabled"; 599 status = "disabled";
641 }; 600 };
642 601
643 /* Temperature sensor on carrier board 602 /* Temperature sensor on carrier board */
644 hwmon_temp: sensor@4f { 603 hwmon_temp: sensor@4f {
645 compatible = "ti,tmp75c"; 604 compatible = "ti,tmp75c";
646 reg = <0x4f>; 605 reg = <0x4f>;
647 status = "disabled"; 606 status = "disabled";
648 }; 607 };
649 608
650 /* EEPROM on display adapter (MIPI DSI 609 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
651 eeprom_display_adapter: eeprom@50 { 610 eeprom_display_adapter: eeprom@50 {
652 compatible = "st,24c02"; 611 compatible = "st,24c02";
653 pagesize = <16>; 612 pagesize = <16>;
654 reg = <0x50>; 613 reg = <0x50>;
655 status = "disabled"; 614 status = "disabled";
656 }; 615 };
657 616
658 /* EEPROM on carrier board */ 617 /* EEPROM on carrier board */
659 eeprom_carrier_board: eeprom@57 { 618 eeprom_carrier_board: eeprom@57 {
660 compatible = "st,24c02"; 619 compatible = "st,24c02";
661 pagesize = <16>; 620 pagesize = <16>;
662 reg = <0x57>; 621 reg = <0x57>;
663 status = "disabled"; 622 status = "disabled";
664 }; 623 };
665 }; 624 };
666 625
667 /* Verdin PCIE_1 */ 626 /* Verdin PCIE_1 */
668 &pcie0 { 627 &pcie0 {
669 assigned-clocks = <&clk IMX8MM_CLK_PCI 628 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
670 <&clk IMX8MM_CLK_PCI 629 <&clk IMX8MM_CLK_PCIE1_CTRL>;
671 assigned-clock-parents = <&clk IMX8MM_ 630 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
672 <&clk IMX8MM_ 631 <&clk IMX8MM_SYS_PLL2_250M>;
673 assigned-clock-rates = <10000000>, <25 632 assigned-clock-rates = <10000000>, <250000000>;
>> 633 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
>> 634 <&clk IMX8MM_CLK_PCIE1_PHY>;
>> 635 clock-names = "pcie", "pcie_aux", "pcie_bus";
674 pinctrl-names = "default"; 636 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pcie0>; 637 pinctrl-0 = <&pinctrl_pcie0>;
676 /* PCIE_1_RESET# (SODIMM 244) */ 638 /* PCIE_1_RESET# (SODIMM 244) */
677 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LO 639 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
678 }; 640 };
679 641
680 &pcie_phy { 642 &pcie_phy {
681 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 643 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
682 clock-names = "ref"; <<
683 fsl,clkreq-unsupported; 644 fsl,clkreq-unsupported;
684 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 645 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
685 fsl,tx-deemph-gen1 = <0x2d>; 646 fsl,tx-deemph-gen1 = <0x2d>;
686 fsl,tx-deemph-gen2 = <0xf>; 647 fsl,tx-deemph-gen2 = <0xf>;
687 }; 648 };
688 649
689 /* Verdin PWM_3_DSI */ 650 /* Verdin PWM_3_DSI */
690 &pwm1 { 651 &pwm1 {
691 pinctrl-names = "default"; 652 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_1>; 653 pinctrl-0 = <&pinctrl_pwm_1>;
693 #pwm-cells = <3>; 654 #pwm-cells = <3>;
694 }; 655 };
695 656
696 /* Verdin PWM_1 */ 657 /* Verdin PWM_1 */
697 &pwm2 { 658 &pwm2 {
698 pinctrl-names = "default"; 659 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_pwm_2>; 660 pinctrl-0 = <&pinctrl_pwm_2>;
700 #pwm-cells = <3>; 661 #pwm-cells = <3>;
701 }; 662 };
702 663
703 /* Verdin PWM_2 */ 664 /* Verdin PWM_2 */
704 &pwm3 { 665 &pwm3 {
705 pinctrl-names = "default"; 666 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_pwm_3>; 667 pinctrl-0 = <&pinctrl_pwm_3>;
707 #pwm-cells = <3>; 668 #pwm-cells = <3>;
708 }; 669 };
709 670
710 /* Verdin I2S_1 */ 671 /* Verdin I2S_1 */
711 &sai2 { 672 &sai2 {
712 #sound-dai-cells = <0>; 673 #sound-dai-cells = <0>;
713 assigned-clock-parents = <&clk IMX8MM_ 674 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
714 assigned-clock-rates = <24576000>; 675 assigned-clock-rates = <24576000>;
715 assigned-clocks = <&clk IMX8MM_CLK_SAI 676 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
716 pinctrl-names = "default"; 677 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_sai2>; 678 pinctrl-0 = <&pinctrl_sai2>;
718 }; 679 };
719 680
720 &snvs_pwrkey { 681 &snvs_pwrkey {
721 status = "okay"; 682 status = "okay";
722 }; 683 };
723 684
724 /* Verdin UART_3, used as the Linux console */ 685 /* Verdin UART_3, used as the Linux console */
725 &uart1 { 686 &uart1 {
726 pinctrl-names = "default"; 687 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_uart1>; 688 pinctrl-0 = <&pinctrl_uart1>;
728 }; 689 };
729 690
730 /* Verdin UART_1 */ 691 /* Verdin UART_1 */
731 &uart2 { 692 &uart2 {
732 pinctrl-names = "default"; 693 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_uart2>; 694 pinctrl-0 = <&pinctrl_uart2>;
734 uart-has-rtscts; 695 uart-has-rtscts;
735 }; 696 };
736 697
737 /* Verdin UART_2 */ 698 /* Verdin UART_2 */
738 &uart3 { 699 &uart3 {
739 pinctrl-names = "default"; 700 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_uart3>; 701 pinctrl-0 = <&pinctrl_uart3>;
741 uart-has-rtscts; 702 uart-has-rtscts;
742 }; 703 };
743 704
744 /* 705 /*
745 * Verdin UART_4 706 * Verdin UART_4
746 * Resource allocated to M4 by default, must n 707 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
747 */ 708 */
748 &uart4 { 709 &uart4 {
749 pinctrl-names = "default"; 710 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_uart4>; 711 pinctrl-0 = <&pinctrl_uart4>;
751 }; 712 };
752 713
753 /* Verdin USB_1 */ 714 /* Verdin USB_1 */
754 &usbotg1 { 715 &usbotg1 {
755 adp-disable; 716 adp-disable;
756 dr_mode = "otg"; 717 dr_mode = "otg";
757 hnp-disable; 718 hnp-disable;
>> 719 over-current-active-low;
758 samsung,picophy-dc-vol-level-adjust = 720 samsung,picophy-dc-vol-level-adjust = <7>;
759 samsung,picophy-pre-emp-curr-control = 721 samsung,picophy-pre-emp-curr-control = <3>;
760 srp-disable; 722 srp-disable;
761 vbus-supply = <®_usb_otg1_vbus>; 723 vbus-supply = <®_usb_otg1_vbus>;
762 }; 724 };
763 725
764 /* Verdin USB_2 */ 726 /* Verdin USB_2 */
765 &usbotg2 { 727 &usbotg2 {
766 dr_mode = "host"; 728 dr_mode = "host";
>> 729 over-current-active-low;
767 samsung,picophy-dc-vol-level-adjust = 730 samsung,picophy-dc-vol-level-adjust = <7>;
768 samsung,picophy-pre-emp-curr-control = 731 samsung,picophy-pre-emp-curr-control = <3>;
769 vbus-supply = <®_usb_otg2_vbus>; 732 vbus-supply = <®_usb_otg2_vbus>;
770 }; 733 };
771 734
772 &usbphynop1 { 735 &usbphynop1 {
773 vcc-supply = <®_vdd_3v3>; 736 vcc-supply = <®_vdd_3v3>;
774 }; 737 };
775 738
776 &usbphynop2 { 739 &usbphynop2 {
777 power-domains = <&pgc_otg2>; 740 power-domains = <&pgc_otg2>;
778 vcc-supply = <®_vdd_3v3>; 741 vcc-supply = <®_vdd_3v3>;
779 }; 742 };
780 743
781 /* On-module eMMC */ 744 /* On-module eMMC */
782 &usdhc1 { 745 &usdhc1 {
783 bus-width = <8>; 746 bus-width = <8>;
784 keep-power-in-suspend; 747 keep-power-in-suspend;
785 non-removable; 748 non-removable;
786 pinctrl-names = "default", "state_100m 749 pinctrl-names = "default", "state_100mhz", "state_200mhz";
787 pinctrl-0 = <&pinctrl_usdhc1>; 750 pinctrl-0 = <&pinctrl_usdhc1>;
788 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 751 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
789 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 752 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
790 status = "okay"; 753 status = "okay";
791 }; 754 };
792 755
793 /* Verdin SD_1 */ 756 /* Verdin SD_1 */
794 &usdhc2 { 757 &usdhc2 {
795 bus-width = <4>; 758 bus-width = <4>;
796 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 759 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
797 disable-wp; 760 disable-wp;
798 pinctrl-names = "default", "state_100m 761 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
799 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 762 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
800 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 763 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
801 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 764 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
802 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 765 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
803 vmmc-supply = <®_usdhc2_vmmc>; 766 vmmc-supply = <®_usdhc2_vmmc>;
804 }; 767 };
805 768
806 &wdog1 { 769 &wdog1 {
807 fsl,ext-reset-output; 770 fsl,ext-reset-output;
808 pinctrl-names = "default"; 771 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_wdog>; 772 pinctrl-0 = <&pinctrl_wdog>;
810 status = "okay"; 773 status = "okay";
811 }; 774 };
812 775
813 &iomuxc { 776 &iomuxc {
814 pinctrl-names = "default"; 777 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_gpio1>, <&pinctr 778 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
816 <&pinctrl_gpio3>, <&pinctr 779 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
817 <&pinctrl_gpio7>, <&pinctr 780 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
818 <&pinctrl_gpio_hog1>, <&pi !! 781 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
>> 782 <&pinctrl_pmic_tpm_ena>;
819 783
820 pinctrl_can1_int: can1intgrp { 784 pinctrl_can1_int: can1intgrp {
821 fsl,pins = 785 fsl,pins =
822 <MX8MM_IOMUXC_GPIO1_IO 786 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
823 }; 787 };
824 788
825 pinctrl_can2_int: can2intgrp { 789 pinctrl_can2_int: can2intgrp {
826 fsl,pins = 790 fsl,pins =
827 <MX8MM_IOMUXC_GPIO1_IO 791 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
828 }; 792 };
829 793
830 pinctrl_ctrl_sleep_moci: ctrlsleepmoci 794 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
831 fsl,pins = 795 fsl,pins =
832 <MX8MM_IOMUXC_SAI3_TXD 796 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
833 }; 797 };
834 798
835 pinctrl_ecspi2: ecspi2grp { 799 pinctrl_ecspi2: ecspi2grp {
836 fsl,pins = 800 fsl,pins =
837 <MX8MM_IOMUXC_ECSPI2_M 801 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
838 <MX8MM_IOMUXC_ECSPI2_M 802 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
839 <MX8MM_IOMUXC_ECSPI2_S 803 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
840 <MX8MM_IOMUXC_ECSPI2_S 804 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
841 }; 805 };
842 806
843 pinctrl_ecspi3: ecspi3grp { 807 pinctrl_ecspi3: ecspi3grp {
844 fsl,pins = 808 fsl,pins =
845 <MX8MM_IOMUXC_GPIO1_IO 809 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
846 <MX8MM_IOMUXC_UART1_RX 810 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
847 <MX8MM_IOMUXC_UART1_TX 811 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
848 <MX8MM_IOMUXC_UART2_RX 812 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
849 <MX8MM_IOMUXC_UART2_TX 813 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
850 }; 814 };
851 815
852 pinctrl_fec1: fec1grp { 816 pinctrl_fec1: fec1grp {
853 fsl,pins = 817 fsl,pins =
854 <MX8MM_IOMUXC_ENET_MDC 818 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
855 <MX8MM_IOMUXC_ENET_MDI 819 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
856 <MX8MM_IOMUXC_ENET_RD0 820 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
857 <MX8MM_IOMUXC_ENET_RD1 821 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
858 <MX8MM_IOMUXC_ENET_RD2 822 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
859 <MX8MM_IOMUXC_ENET_RD3 823 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
860 <MX8MM_IOMUXC_ENET_RXC 824 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
861 <MX8MM_IOMUXC_ENET_RX_ 825 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
862 <MX8MM_IOMUXC_ENET_TD0 826 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
863 <MX8MM_IOMUXC_ENET_TD1 827 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
864 <MX8MM_IOMUXC_ENET_TD2 828 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
865 <MX8MM_IOMUXC_ENET_TD3 829 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
866 <MX8MM_IOMUXC_ENET_TXC 830 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
867 <MX8MM_IOMUXC_ENET_TX_ 831 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
868 <MX8MM_IOMUXC_GPIO1_IO 832 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
869 }; 833 };
870 834
871 pinctrl_fec1_sleep: fec1-sleepgrp { 835 pinctrl_fec1_sleep: fec1-sleepgrp {
872 fsl,pins = 836 fsl,pins =
873 <MX8MM_IOMUXC_ENET_MDC 837 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
874 <MX8MM_IOMUXC_ENET_MDI 838 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
875 <MX8MM_IOMUXC_ENET_RD0 839 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
876 <MX8MM_IOMUXC_ENET_RD1 840 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
877 <MX8MM_IOMUXC_ENET_RD2 841 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
878 <MX8MM_IOMUXC_ENET_RD3 842 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
879 <MX8MM_IOMUXC_ENET_RXC 843 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
880 <MX8MM_IOMUXC_ENET_RX_ 844 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
881 <MX8MM_IOMUXC_ENET_TD0 845 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
882 <MX8MM_IOMUXC_ENET_TD1 846 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
883 <MX8MM_IOMUXC_ENET_TD2 847 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
884 <MX8MM_IOMUXC_ENET_TD3 848 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
885 <MX8MM_IOMUXC_ENET_TXC 849 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
886 <MX8MM_IOMUXC_ENET_TX_ 850 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
887 <MX8MM_IOMUXC_GPIO1_IO 851 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
888 }; 852 };
889 853
890 pinctrl_flexspi0: flexspi0grp { 854 pinctrl_flexspi0: flexspi0grp {
891 fsl,pins = 855 fsl,pins =
892 <MX8MM_IOMUXC_NAND_ALE 856 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
893 <MX8MM_IOMUXC_NAND_CE0 857 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
894 <MX8MM_IOMUXC_NAND_CE1 858 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
895 <MX8MM_IOMUXC_NAND_DAT 859 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
896 <MX8MM_IOMUXC_NAND_DAT 860 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
897 <MX8MM_IOMUXC_NAND_DAT 861 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
898 <MX8MM_IOMUXC_NAND_DAT 862 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
899 <MX8MM_IOMUXC_NAND_DQS 863 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
900 }; 864 };
901 865
902 pinctrl_gpio1: gpio1grp { 866 pinctrl_gpio1: gpio1grp {
903 fsl,pins = 867 fsl,pins =
904 <MX8MM_IOMUXC_NAND_CE3 868 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
905 }; 869 };
906 870
907 pinctrl_gpio2: gpio2grp { 871 pinctrl_gpio2: gpio2grp {
908 fsl,pins = 872 fsl,pins =
909 <MX8MM_IOMUXC_SPDIF_EX 873 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
910 }; 874 };
911 875
912 pinctrl_gpio3: gpio3grp { 876 pinctrl_gpio3: gpio3grp {
913 fsl,pins = 877 fsl,pins =
914 <MX8MM_IOMUXC_UART3_RX 878 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
915 }; 879 };
916 880
917 pinctrl_gpio4: gpio4grp { 881 pinctrl_gpio4: gpio4grp {
918 fsl,pins = 882 fsl,pins =
919 <MX8MM_IOMUXC_UART3_TX 883 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
920 }; 884 };
921 885
922 pinctrl_gpio5: gpio5grp { 886 pinctrl_gpio5: gpio5grp {
923 fsl,pins = 887 fsl,pins =
924 <MX8MM_IOMUXC_GPIO1_IO 888 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
925 }; 889 };
926 890
927 pinctrl_gpio6: gpio6grp { 891 pinctrl_gpio6: gpio6grp {
928 fsl,pins = 892 fsl,pins =
929 <MX8MM_IOMUXC_GPIO1_IO 893 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
930 }; 894 };
931 895
932 pinctrl_gpio7: gpio7grp { 896 pinctrl_gpio7: gpio7grp {
933 fsl,pins = 897 fsl,pins =
934 <MX8MM_IOMUXC_GPIO1_IO 898 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
935 }; 899 };
936 900
937 pinctrl_gpio8: gpio8grp { 901 pinctrl_gpio8: gpio8grp {
938 fsl,pins = 902 fsl,pins =
939 <MX8MM_IOMUXC_GPIO1_IO 903 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
940 }; 904 };
941 905
942 /* Verdin GPIO_9_DSI (pulled-up as act 906 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
943 pinctrl_gpio_9_dsi: gpio9dsigrp { 907 pinctrl_gpio_9_dsi: gpio9dsigrp {
944 fsl,pins = 908 fsl,pins =
945 <MX8MM_IOMUXC_NAND_RE_ !! 909 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
946 }; 910 };
947 911
948 /* Verdin GPIO_10_DSI (pulled-up as ac 912 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
949 pinctrl_gpio_10_dsi: gpio10dsigrp { 913 pinctrl_gpio_10_dsi: gpio10dsigrp {
950 fsl,pins = 914 fsl,pins =
951 <MX8MM_IOMUXC_NAND_CE2 915 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
952 }; 916 };
953 917
954 pinctrl_gpio_hog1: gpiohog1grp { 918 pinctrl_gpio_hog1: gpiohog1grp {
955 fsl,pins = 919 fsl,pins =
956 <MX8MM_IOMUXC_SAI1_MCL 920 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
957 <MX8MM_IOMUXC_SAI1_RXC 921 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
958 <MX8MM_IOMUXC_SAI1_RXD 922 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
959 <MX8MM_IOMUXC_SAI1_RXD 923 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
960 <MX8MM_IOMUXC_SAI1_RXD 924 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
961 <MX8MM_IOMUXC_SAI1_RXD 925 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
962 <MX8MM_IOMUXC_SAI1_RXF 926 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
963 <MX8MM_IOMUXC_SAI1_TXC 927 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
964 <MX8MM_IOMUXC_SAI1_TXD 928 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
965 <MX8MM_IOMUXC_SAI1_TXD 929 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
966 <MX8MM_IOMUXC_SAI1_TXD 930 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
967 <MX8MM_IOMUXC_SAI1_TXD 931 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
968 <MX8MM_IOMUXC_SAI1_TXD 932 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
969 <MX8MM_IOMUXC_SAI1_TXD 933 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
970 <MX8MM_IOMUXC_SAI1_TXF 934 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
971 }; 935 };
972 936
973 pinctrl_gpio_hog2: gpiohog2grp { 937 pinctrl_gpio_hog2: gpiohog2grp {
974 fsl,pins = 938 fsl,pins =
975 <MX8MM_IOMUXC_SAI3_MCL 939 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
976 }; 940 };
977 941
978 pinctrl_gpio_hog3: gpiohog3grp { 942 pinctrl_gpio_hog3: gpiohog3grp {
979 fsl,pins = 943 fsl,pins =
980 <MX8MM_IOMUXC_GPIO1_IO 944 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
981 <MX8MM_IOMUXC_GPIO1_IO 945 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
982 }; 946 };
983 947
984 pinctrl_gpio_keys: gpiokeysgrp { 948 pinctrl_gpio_keys: gpiokeysgrp {
985 fsl,pins = 949 fsl,pins =
986 <MX8MM_IOMUXC_SAI3_RXF 950 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
987 }; 951 };
988 952
989 /* On-module I2C */ 953 /* On-module I2C */
990 pinctrl_i2c1: i2c1grp { 954 pinctrl_i2c1: i2c1grp {
991 fsl,pins = 955 fsl,pins =
992 <MX8MM_IOMUXC_I2C1_SCL 956 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
993 <MX8MM_IOMUXC_I2C1_SDA 957 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
994 }; 958 };
995 959
996 pinctrl_i2c1_gpio: i2c1gpiogrp { 960 pinctrl_i2c1_gpio: i2c1gpiogrp {
997 fsl,pins = 961 fsl,pins =
998 <MX8MM_IOMUXC_I2C1_SCL 962 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
999 <MX8MM_IOMUXC_I2C1_SDA 963 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
1000 }; 964 };
1001 965
1002 /* Verdin I2C_4_CSI */ 966 /* Verdin I2C_4_CSI */
1003 pinctrl_i2c2: i2c2grp { 967 pinctrl_i2c2: i2c2grp {
1004 fsl,pins = 968 fsl,pins =
1005 <MX8MM_IOMUXC_I2C2_SC 969 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
1006 <MX8MM_IOMUXC_I2C2_SD 970 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
1007 }; 971 };
1008 972
1009 pinctrl_i2c2_gpio: i2c2gpiogrp { 973 pinctrl_i2c2_gpio: i2c2gpiogrp {
1010 fsl,pins = 974 fsl,pins =
1011 <MX8MM_IOMUXC_I2C2_SC 975 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
1012 <MX8MM_IOMUXC_I2C2_SD 976 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1013 }; 977 };
1014 978
1015 /* Verdin I2C_2_DSI */ 979 /* Verdin I2C_2_DSI */
1016 pinctrl_i2c3: i2c3grp { 980 pinctrl_i2c3: i2c3grp {
1017 fsl,pins = 981 fsl,pins =
1018 <MX8MM_IOMUXC_I2C3_SC 982 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1019 <MX8MM_IOMUXC_I2C3_SD 983 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1020 }; 984 };
1021 985
1022 pinctrl_i2c3_gpio: i2c3gpiogrp { 986 pinctrl_i2c3_gpio: i2c3gpiogrp {
1023 fsl,pins = 987 fsl,pins =
1024 <MX8MM_IOMUXC_I2C3_SC 988 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1025 <MX8MM_IOMUXC_I2C3_SD 989 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1026 }; 990 };
1027 991
1028 /* Verdin I2C_1 */ 992 /* Verdin I2C_1 */
1029 pinctrl_i2c4: i2c4grp { 993 pinctrl_i2c4: i2c4grp {
1030 fsl,pins = 994 fsl,pins =
1031 <MX8MM_IOMUXC_I2C4_SC 995 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1032 <MX8MM_IOMUXC_I2C4_SD 996 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1033 }; 997 };
1034 998
1035 pinctrl_i2c4_gpio: i2c4gpiogrp { 999 pinctrl_i2c4_gpio: i2c4gpiogrp {
1036 fsl,pins = 1000 fsl,pins =
1037 <MX8MM_IOMUXC_I2C4_SC 1001 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1038 <MX8MM_IOMUXC_I2C4_SD 1002 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1039 }; 1003 };
1040 1004
1041 /* Verdin I2S_2_BCLK (TOUCH_RESET#) * 1005 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1042 pinctrl_i2s_2_bclk_touch_reset: i2s2b 1006 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1043 fsl,pins = 1007 fsl,pins =
1044 <MX8MM_IOMUXC_SAI5_RX 1008 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1045 }; 1009 };
1046 1010
1047 /* Verdin I2S_2_D_OUT shared with SAI 1011 /* Verdin I2S_2_D_OUT shared with SAI5 */
1048 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s 1012 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1049 fsl,pins = 1013 fsl,pins =
1050 <MX8MM_IOMUXC_SAI5_RX 1014 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1051 }; 1015 };
1052 1016
1053 pinctrl_pcie0: pcie0grp { 1017 pinctrl_pcie0: pcie0grp {
1054 fsl,pins = 1018 fsl,pins =
1055 <MX8MM_IOMUXC_SAI5_RX 1019 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1056 /* PMIC_EN_PCIe_CLK, 1020 /* PMIC_EN_PCIe_CLK, unused */
1057 <MX8MM_IOMUXC_SD2_RES 1021 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1058 }; 1022 };
1059 1023
1060 pinctrl_pmic: pmicirqgrp { 1024 pinctrl_pmic: pmicirqgrp {
1061 fsl,pins = 1025 fsl,pins =
1062 <MX8MM_IOMUXC_GPIO1_I 1026 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1063 }; 1027 };
1064 1028
1065 /* Verdin PWM_3_DSI shared with GPIO1 1029 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1066 pinctrl_pwm_1: pwm1grp { 1030 pinctrl_pwm_1: pwm1grp {
1067 fsl,pins = 1031 fsl,pins =
1068 <MX8MM_IOMUXC_GPIO1_I 1032 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1069 }; 1033 };
1070 1034
1071 pinctrl_pwm_2: pwm2grp { 1035 pinctrl_pwm_2: pwm2grp {
1072 fsl,pins = 1036 fsl,pins =
1073 <MX8MM_IOMUXC_SPDIF_R 1037 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1074 }; 1038 };
1075 1039
1076 pinctrl_pwm_3: pwm3grp { 1040 pinctrl_pwm_3: pwm3grp {
1077 fsl,pins = 1041 fsl,pins =
1078 <MX8MM_IOMUXC_SPDIF_T 1042 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1079 }; 1043 };
1080 1044
1081 /* Verdin PWM_3_DSI (pulled-down as a 1045 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1082 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihp 1046 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1083 fsl,pins = 1047 fsl,pins =
1084 <MX8MM_IOMUXC_GPIO1_I 1048 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1085 }; 1049 };
1086 1050
1087 pinctrl_reg_eth: regethgrp { 1051 pinctrl_reg_eth: regethgrp {
1088 fsl,pins = 1052 fsl,pins =
1089 <MX8MM_IOMUXC_SD2_WP_ 1053 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1090 }; 1054 };
1091 1055
1092 pinctrl_reg_usb1_en: regusb1engrp { 1056 pinctrl_reg_usb1_en: regusb1engrp {
1093 fsl,pins = 1057 fsl,pins =
1094 <MX8MM_IOMUXC_GPIO1_I 1058 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1095 }; 1059 };
1096 1060
1097 pinctrl_reg_usb2_en: regusb2engrp { 1061 pinctrl_reg_usb2_en: regusb2engrp {
1098 fsl,pins = 1062 fsl,pins =
1099 <MX8MM_IOMUXC_GPIO1_I 1063 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1100 }; 1064 };
1101 1065
1102 pinctrl_sai2: sai2grp { 1066 pinctrl_sai2: sai2grp {
1103 fsl,pins = 1067 fsl,pins =
1104 <MX8MM_IOMUXC_SAI2_MC 1068 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1105 <MX8MM_IOMUXC_SAI2_TX 1069 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1106 <MX8MM_IOMUXC_SAI2_TX 1070 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1107 <MX8MM_IOMUXC_SAI2_RX 1071 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1108 <MX8MM_IOMUXC_SAI2_TX 1072 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1109 }; 1073 };
1110 1074
1111 pinctrl_sai5: sai5grp { 1075 pinctrl_sai5: sai5grp {
1112 fsl,pins = 1076 fsl,pins =
1113 <MX8MM_IOMUXC_SAI5_RX 1077 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1114 <MX8MM_IOMUXC_SAI5_RX 1078 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1115 <MX8MM_IOMUXC_SAI5_RX 1079 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1116 <MX8MM_IOMUXC_SAI5_RX 1080 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1117 }; 1081 };
1118 1082
1119 /* control signal for optional ATTPM2 1083 /* control signal for optional ATTPM20P or SE050 */
1120 pinctrl_tpm_spi_cs: tpmspicsgrp { !! 1084 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1121 fsl,pins = 1085 fsl,pins =
1122 <MX8MM_IOMUXC_SAI1_TX 1086 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1123 }; 1087 };
1124 1088
1125 pinctrl_tsp: tspgrp { 1089 pinctrl_tsp: tspgrp {
1126 fsl,pins = 1090 fsl,pins =
1127 <MX8MM_IOMUXC_SAI1_RX 1091 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1128 <MX8MM_IOMUXC_SAI1_RX 1092 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1129 <MX8MM_IOMUXC_SAI1_RX 1093 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1130 <MX8MM_IOMUXC_SAI1_RX 1094 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1131 <MX8MM_IOMUXC_SAI1_TX 1095 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1132 }; 1096 };
1133 1097
1134 pinctrl_uart1: uart1grp { 1098 pinctrl_uart1: uart1grp {
1135 fsl,pins = 1099 fsl,pins =
1136 <MX8MM_IOMUXC_SAI2_RX 1100 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1137 <MX8MM_IOMUXC_SAI2_RX 1101 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1138 }; 1102 };
1139 1103
1140 pinctrl_uart2: uart2grp { 1104 pinctrl_uart2: uart2grp {
1141 fsl,pins = 1105 fsl,pins =
1142 <MX8MM_IOMUXC_SAI3_RX 1106 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1143 <MX8MM_IOMUXC_SAI3_RX 1107 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1144 <MX8MM_IOMUXC_SAI3_TX 1108 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1145 <MX8MM_IOMUXC_SAI3_TX 1109 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1146 }; 1110 };
1147 1111
1148 pinctrl_uart3: uart3grp { 1112 pinctrl_uart3: uart3grp {
1149 fsl,pins = 1113 fsl,pins =
1150 <MX8MM_IOMUXC_ECSPI1_ 1114 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1151 <MX8MM_IOMUXC_ECSPI1_ 1115 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1152 <MX8MM_IOMUXC_ECSPI1_ 1116 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1153 <MX8MM_IOMUXC_ECSPI1_ 1117 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1154 }; 1118 };
1155 1119
1156 pinctrl_uart4: uart4grp { 1120 pinctrl_uart4: uart4grp {
1157 fsl,pins = 1121 fsl,pins =
1158 <MX8MM_IOMUXC_UART4_R 1122 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1159 <MX8MM_IOMUXC_UART4_T 1123 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1160 }; 1124 };
1161 1125
1162 pinctrl_usdhc1: usdhc1grp { 1126 pinctrl_usdhc1: usdhc1grp {
1163 fsl,pins = 1127 fsl,pins =
1164 <MX8MM_IOMUXC_SD1_CLK 1128 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1165 <MX8MM_IOMUXC_SD1_CMD 1129 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1166 <MX8MM_IOMUXC_SD1_DAT 1130 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1167 <MX8MM_IOMUXC_SD1_DAT 1131 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1168 <MX8MM_IOMUXC_SD1_DAT 1132 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1169 <MX8MM_IOMUXC_SD1_DAT 1133 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1170 <MX8MM_IOMUXC_SD1_DAT 1134 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1171 <MX8MM_IOMUXC_SD1_DAT 1135 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1172 <MX8MM_IOMUXC_SD1_DAT 1136 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1173 <MX8MM_IOMUXC_SD1_DAT 1137 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1174 <MX8MM_IOMUXC_SD1_RES 1138 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1175 <MX8MM_IOMUXC_SD1_STR 1139 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1176 }; 1140 };
1177 1141
1178 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1142 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1179 fsl,pins = 1143 fsl,pins =
1180 <MX8MM_IOMUXC_SD1_CLK 1144 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1181 <MX8MM_IOMUXC_SD1_CMD 1145 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1182 <MX8MM_IOMUXC_SD1_DAT 1146 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1183 <MX8MM_IOMUXC_SD1_DAT 1147 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1184 <MX8MM_IOMUXC_SD1_DAT 1148 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1185 <MX8MM_IOMUXC_SD1_DAT 1149 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1186 <MX8MM_IOMUXC_SD1_DAT 1150 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1187 <MX8MM_IOMUXC_SD1_DAT 1151 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1188 <MX8MM_IOMUXC_SD1_DAT 1152 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1189 <MX8MM_IOMUXC_SD1_DAT 1153 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1190 <MX8MM_IOMUXC_SD1_RES 1154 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1191 <MX8MM_IOMUXC_SD1_STR 1155 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1192 }; 1156 };
1193 1157
1194 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1158 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1195 fsl,pins = 1159 fsl,pins =
1196 <MX8MM_IOMUXC_SD1_CLK 1160 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1197 <MX8MM_IOMUXC_SD1_CMD 1161 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1198 <MX8MM_IOMUXC_SD1_DAT 1162 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1199 <MX8MM_IOMUXC_SD1_DAT 1163 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1200 <MX8MM_IOMUXC_SD1_DAT 1164 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1201 <MX8MM_IOMUXC_SD1_DAT 1165 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1202 <MX8MM_IOMUXC_SD1_DAT 1166 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1203 <MX8MM_IOMUXC_SD1_DAT 1167 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1204 <MX8MM_IOMUXC_SD1_DAT 1168 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1205 <MX8MM_IOMUXC_SD1_DAT 1169 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1206 <MX8MM_IOMUXC_SD1_RES 1170 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1207 <MX8MM_IOMUXC_SD1_STR 1171 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1208 }; 1172 };
1209 1173
1210 pinctrl_usdhc2_cd: usdhc2cdgrp { 1174 pinctrl_usdhc2_cd: usdhc2cdgrp {
1211 fsl,pins = 1175 fsl,pins =
1212 <MX8MM_IOMUXC_SD2_CD_ 1176 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1213 }; 1177 };
1214 1178
1215 pinctrl_usdhc2_cd_sleep: usdhc2cdslpg 1179 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1216 fsl,pins = 1180 fsl,pins =
1217 <MX8MM_IOMUXC_SD2_CD_ 1181 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1218 }; 1182 };
1219 1183
1220 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp 1184 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1221 fsl,pins = 1185 fsl,pins =
1222 <MX8MM_IOMUXC_NAND_CL 1186 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1223 }; 1187 };
1224 1188
1225 /* 1189 /*
1226 * Note: Due to ERR050080 we use disc 1190 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1227 * on-module +V3.3_1.8_SD (LDO5) rail 1191 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1228 */ 1192 */
1229 pinctrl_usdhc2: usdhc2grp { 1193 pinctrl_usdhc2: usdhc2grp {
1230 fsl,pins = 1194 fsl,pins =
1231 <MX8MM_IOMUXC_GPIO1_I 1195 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1232 <MX8MM_IOMUXC_SD2_CLK 1196 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1233 <MX8MM_IOMUXC_SD2_CMD 1197 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1234 <MX8MM_IOMUXC_SD2_DAT 1198 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1235 <MX8MM_IOMUXC_SD2_DAT 1199 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1236 <MX8MM_IOMUXC_SD2_DAT 1200 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1237 <MX8MM_IOMUXC_SD2_DAT 1201 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1238 }; 1202 };
1239 1203
1240 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1204 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1241 fsl,pins = 1205 fsl,pins =
1242 <MX8MM_IOMUXC_GPIO1_I 1206 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1243 <MX8MM_IOMUXC_SD2_CLK 1207 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1244 <MX8MM_IOMUXC_SD2_CMD 1208 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1245 <MX8MM_IOMUXC_SD2_DAT 1209 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1246 <MX8MM_IOMUXC_SD2_DAT 1210 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1247 <MX8MM_IOMUXC_SD2_DAT 1211 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1248 <MX8MM_IOMUXC_SD2_DAT 1212 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1249 }; 1213 };
1250 1214
1251 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1215 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1252 fsl,pins = 1216 fsl,pins =
1253 <MX8MM_IOMUXC_GPIO1_I 1217 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1254 <MX8MM_IOMUXC_SD2_CLK 1218 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1255 <MX8MM_IOMUXC_SD2_CMD 1219 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1256 <MX8MM_IOMUXC_SD2_DAT 1220 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1257 <MX8MM_IOMUXC_SD2_DAT 1221 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1258 <MX8MM_IOMUXC_SD2_DAT 1222 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1259 <MX8MM_IOMUXC_SD2_DAT 1223 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1260 }; 1224 };
1261 1225
1262 /* Avoid backfeeding with removed car 1226 /* Avoid backfeeding with removed card power */
1263 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1227 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1264 fsl,pins = 1228 fsl,pins =
1265 <MX8MM_IOMUXC_GPIO1_I 1229 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1266 <MX8MM_IOMUXC_SD2_CLK 1230 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1267 <MX8MM_IOMUXC_SD2_CMD 1231 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1268 <MX8MM_IOMUXC_SD2_DAT 1232 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1269 <MX8MM_IOMUXC_SD2_DAT 1233 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1270 <MX8MM_IOMUXC_SD2_DAT 1234 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1271 <MX8MM_IOMUXC_SD2_DAT 1235 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1272 }; 1236 };
1273 1237
1274 /* 1238 /*
1275 * On-module Wi-Fi/BT or type specifi 1239 * On-module Wi-Fi/BT or type specific SDHC interface
1276 * (e.g. on X52 extension slot of Ver 1240 * (e.g. on X52 extension slot of Verdin Development Board)
1277 */ 1241 */
1278 pinctrl_usdhc3: usdhc3grp { 1242 pinctrl_usdhc3: usdhc3grp {
1279 fsl,pins = 1243 fsl,pins =
1280 <MX8MM_IOMUXC_NAND_DA 1244 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1281 <MX8MM_IOMUXC_NAND_DA 1245 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1282 <MX8MM_IOMUXC_NAND_DA 1246 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1283 <MX8MM_IOMUXC_NAND_DA 1247 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1284 <MX8MM_IOMUXC_NAND_WE 1248 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1285 <MX8MM_IOMUXC_NAND_WP 1249 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1286 }; 1250 };
1287 1251
1288 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1252 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1289 fsl,pins = 1253 fsl,pins =
1290 <MX8MM_IOMUXC_NAND_DA 1254 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1291 <MX8MM_IOMUXC_NAND_DA 1255 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1292 <MX8MM_IOMUXC_NAND_DA 1256 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1293 <MX8MM_IOMUXC_NAND_DA 1257 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1294 <MX8MM_IOMUXC_NAND_WE 1258 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1295 <MX8MM_IOMUXC_NAND_WP 1259 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1296 }; 1260 };
1297 1261
1298 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1262 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1299 fsl,pins = 1263 fsl,pins =
1300 <MX8MM_IOMUXC_NAND_DA 1264 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1301 <MX8MM_IOMUXC_NAND_DA 1265 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1302 <MX8MM_IOMUXC_NAND_DA 1266 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1303 <MX8MM_IOMUXC_NAND_DA 1267 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1304 <MX8MM_IOMUXC_NAND_WE 1268 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1305 <MX8MM_IOMUXC_NAND_WP 1269 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1306 }; 1270 };
1307 1271
1308 pinctrl_wdog: wdoggrp { 1272 pinctrl_wdog: wdoggrp {
1309 fsl,pins = 1273 fsl,pins =
1310 <MX8MM_IOMUXC_GPIO1_I 1274 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1311 }; 1275 };
1312 1276
1313 pinctrl_wifi_ctrl: wifictrlgrp { 1277 pinctrl_wifi_ctrl: wifictrlgrp {
1314 fsl,pins = 1278 fsl,pins =
1315 <MX8MM_IOMUXC_NAND_RE 1279 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1316 <MX8MM_IOMUXC_SAI1_RX 1280 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1317 <MX8MM_IOMUXC_SAI5_RX 1281 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1318 }; 1282 };
1319 1283
1320 pinctrl_wifi_i2s: bti2sgrp { 1284 pinctrl_wifi_i2s: bti2sgrp {
1321 fsl,pins = 1285 fsl,pins =
1322 <MX8MM_IOMUXC_SAI1_RX 1286 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1323 <MX8MM_IOMUXC_SAI1_RX 1287 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1324 <MX8MM_IOMUXC_SAI1_RX 1288 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1325 <MX8MM_IOMUXC_SAI1_TX 1289 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1326 }; 1290 };
1327 1291
1328 pinctrl_wifi_pwr_en: wifipwrengrp { 1292 pinctrl_wifi_pwr_en: wifipwrengrp {
1329 fsl,pins = 1293 fsl,pins =
1330 <MX8MM_IOMUXC_SAI5_MC 1294 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1331 }; 1295 };
1332 }; 1296 };
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