1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy-imx8-pcie.h> !! 6 #include "dt-bindings/phy/phy-imx8-pcie.h"
7 #include <dt-bindings/pwm/pwm.h> !! 7 #include "dt-bindings/pwm/pwm.h"
8 #include "imx8mm.dtsi" 8 #include "imx8mm.dtsi"
9 #include "imx8mm-overdrive.dtsi" <<
10 9
11 / { 10 / {
12 chosen { 11 chosen {
13 stdout-path = &uart1; 12 stdout-path = &uart1;
14 }; 13 };
15 14
16 aliases { 15 aliases {
17 rtc0 = &rtc_i2c; 16 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc; 17 rtc1 = &snvs_rtc;
19 }; 18 };
20 19
21 backlight: backlight { 20 backlight: backlight {
22 compatible = "pwm-backlight"; 21 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 8 22 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4> 23 default-brightness-level = <4>;
25 /* Verdin I2S_2_D_OUT (DSI_1_B 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
26 enable-gpios = <&gpio3 24 GPIO 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default"; 26 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_i2s_2_d_ 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
29 power-supply = <®_3p3v>; 28 power-supply = <®_3p3v>;
30 /* Verdin PWM_3_DSI/PWM_3_DSI_ 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
31 pwms = <&pwm1 0 6666667 PWM_PO 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 /* Fixed clock dedicated to SPI CAN co 34 /* Fixed clock dedicated to SPI CAN controller */
36 clk40m: oscillator { 35 clk40m: oscillator {
37 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
38 #clock-cells = <0>; 37 #clock-cells = <0>;
39 clock-frequency = <40000000>; 38 clock-frequency = <40000000>;
40 }; 39 };
41 40
42 gpio-keys { 41 gpio-keys {
43 compatible = "gpio-keys"; 42 compatible = "gpio-keys";
44 pinctrl-names = "default"; 43 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_key 44 pinctrl-0 = <&pinctrl_gpio_keys>;
46 45
47 key-wakeup { 46 key-wakeup {
48 debounce-interval = <1 47 debounce-interval = <10>;
49 /* Verdin CTRL_WAKE1_M 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
50 gpios = <&gpio4 28 GPI 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 label = "Wake-Up"; 50 label = "Wake-Up";
52 linux,code = <KEY_WAKE 51 linux,code = <KEY_WAKEUP>;
53 wakeup-source; 52 wakeup-source;
54 }; 53 };
55 }; 54 };
56 55
57 hdmi_connector: hdmi-connector { 56 hdmi_connector: hdmi-connector {
58 compatible = "hdmi-connector"; 57 compatible = "hdmi-connector";
59 ddc-i2c-bus = <&i2c2>; 58 ddc-i2c-bus = <&i2c2>;
60 /* Verdin PWM_3_DSI (SODIMM 19 <<
61 hpd-gpios = <&gpio1 1 GPIO_ACT <<
62 label = "hdmi"; 59 label = "hdmi";
63 pinctrl-names = "default"; <<
64 pinctrl-0 = <&pinctrl_pwm_3_ds <<
65 type = "a"; 60 type = "a";
66 status = "disabled"; 61 status = "disabled";
67 }; 62 };
68 63
69 panel_lvds: panel-lvds { 64 panel_lvds: panel-lvds {
70 compatible = "panel-lvds"; 65 compatible = "panel-lvds";
71 backlight = <&backlight>; 66 backlight = <&backlight>;
72 data-mapping = "vesa-24"; 67 data-mapping = "vesa-24";
73 status = "disabled"; 68 status = "disabled";
74 }; 69 };
75 70
76 /* Carrier Board Supplies */ 71 /* Carrier Board Supplies */
77 reg_1p8v: regulator-1p8v { 72 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed" 73 compatible = "regulator-fixed";
79 regulator-max-microvolt = <180 74 regulator-max-microvolt = <1800000>;
80 regulator-min-microvolt = <180 75 regulator-min-microvolt = <1800000>;
81 regulator-name = "+V1.8_SW"; 76 regulator-name = "+V1.8_SW";
82 }; 77 };
83 78
84 reg_3p3v: regulator-3p3v { 79 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed" 80 compatible = "regulator-fixed";
86 regulator-max-microvolt = <330 81 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <330 82 regulator-min-microvolt = <3300000>;
88 regulator-name = "+V3.3_SW"; 83 regulator-name = "+V3.3_SW";
89 }; 84 };
90 85
91 reg_5p0v: regulator-5p0v { 86 reg_5p0v: regulator-5p0v {
92 compatible = "regulator-fixed" 87 compatible = "regulator-fixed";
93 regulator-max-microvolt = <500 88 regulator-max-microvolt = <5000000>;
94 regulator-min-microvolt = <500 89 regulator-min-microvolt = <5000000>;
95 regulator-name = "+V5_SW"; 90 regulator-name = "+V5_SW";
96 }; 91 };
97 92
98 /* Non PMIC On-module Supplies */ 93 /* Non PMIC On-module Supplies */
99 reg_ethphy: regulator-ethphy { 94 reg_ethphy: regulator-ethphy {
100 compatible = "regulator-fixed" 95 compatible = "regulator-fixed";
101 enable-active-high; 96 enable-active-high;
102 gpio = <&gpio2 20 GPIO_ACTIVE_ 97 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
103 off-on-delay-us = <500000>; 98 off-on-delay-us = <500000>;
104 pinctrl-names = "default"; 99 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_eth> 100 pinctrl-0 = <&pinctrl_reg_eth>;
106 regulator-always-on; 101 regulator-always-on;
107 regulator-boot-on; 102 regulator-boot-on;
108 regulator-max-microvolt = <330 103 regulator-max-microvolt = <3300000>;
109 regulator-min-microvolt = <330 104 regulator-min-microvolt = <3300000>;
110 regulator-name = "On-module +V 105 regulator-name = "On-module +V3.3_ETH";
111 startup-delay-us = <200000>; 106 startup-delay-us = <200000>;
112 }; 107 };
113 108
114 /* <<
115 * By default we enable CTRL_SLEEP_MOC <<
116 * peripherals on the carrier board po <<
117 * If more granularity or power saving <<
118 * in the carrier board device tree fi <<
119 */ <<
120 reg_force_sleep_moci: regulator-force- <<
121 compatible = "regulator-fixed" <<
122 enable-active-high; <<
123 /* Verdin CTRL_SLEEP_MOCI# (SO <<
124 gpio = <&gpio5 1 GPIO_ACTIVE_H <<
125 regulator-always-on; <<
126 regulator-boot-on; <<
127 regulator-name = "CTRL_SLEEP_M <<
128 }; <<
129 <<
130 reg_usb_otg1_vbus: regulator-usb-otg1 109 reg_usb_otg1_vbus: regulator-usb-otg1 {
131 compatible = "regulator-fixed" 110 compatible = "regulator-fixed";
132 enable-active-high; 111 enable-active-high;
133 /* Verdin USB_1_EN (SODIMM 155 112 /* Verdin USB_1_EN (SODIMM 155) */
134 gpio = <&gpio1 12 GPIO_ACTIVE_ 113 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
135 pinctrl-names = "default"; 114 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_usb1 115 pinctrl-0 = <&pinctrl_reg_usb1_en>;
137 regulator-max-microvolt = <500 116 regulator-max-microvolt = <5000000>;
138 regulator-min-microvolt = <500 117 regulator-min-microvolt = <5000000>;
139 regulator-name = "USB_1_EN"; 118 regulator-name = "USB_1_EN";
140 }; 119 };
141 120
142 reg_usb_otg2_vbus: regulator-usb-otg2 121 reg_usb_otg2_vbus: regulator-usb-otg2 {
143 compatible = "regulator-fixed" 122 compatible = "regulator-fixed";
144 enable-active-high; 123 enable-active-high;
145 /* Verdin USB_2_EN (SODIMM 185 124 /* Verdin USB_2_EN (SODIMM 185) */
146 gpio = <&gpio1 14 GPIO_ACTIVE_ 125 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
147 pinctrl-names = "default"; 126 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb2 127 pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 regulator-max-microvolt = <500 128 regulator-max-microvolt = <5000000>;
150 regulator-min-microvolt = <500 129 regulator-min-microvolt = <5000000>;
151 regulator-name = "USB_2_EN"; 130 regulator-name = "USB_2_EN";
152 }; 131 };
153 132
154 reg_usdhc2_vmmc: regulator-usdhc2 { 133 reg_usdhc2_vmmc: regulator-usdhc2 {
155 compatible = "regulator-fixed" 134 compatible = "regulator-fixed";
156 enable-active-high; 135 enable-active-high;
157 /* Verdin SD_1_PWR_EN (SODIMM 136 /* Verdin SD_1_PWR_EN (SODIMM 76) */
158 gpio = <&gpio3 5 GPIO_ACTIVE_H 137 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
159 off-on-delay-us = <100000>; 138 off-on-delay-us = <100000>;
160 pinctrl-names = "default"; 139 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc2_p 140 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
162 regulator-max-microvolt = <330 141 regulator-max-microvolt = <3300000>;
163 regulator-min-microvolt = <330 142 regulator-min-microvolt = <3300000>;
164 regulator-name = "+V3.3_SD"; 143 regulator-name = "+V3.3_SD";
165 startup-delay-us = <2000>; 144 startup-delay-us = <2000>;
166 }; 145 };
167 146
168 reserved-memory { 147 reserved-memory {
169 #address-cells = <2>; 148 #address-cells = <2>;
170 #size-cells = <2>; 149 #size-cells = <2>;
171 ranges; 150 ranges;
172 151
173 /* Use the kernel configuratio 152 /* Use the kernel configuration settings instead */
174 /delete-node/ linux,cma; 153 /delete-node/ linux,cma;
175 }; 154 };
176 }; 155 };
177 156
178 &A53_0 { 157 &A53_0 {
179 cpu-supply = <®_vdd_arm>; 158 cpu-supply = <®_vdd_arm>;
180 }; 159 };
181 160
182 &A53_1 { 161 &A53_1 {
183 cpu-supply = <®_vdd_arm>; 162 cpu-supply = <®_vdd_arm>;
184 }; 163 };
185 164
186 &A53_2 { 165 &A53_2 {
187 cpu-supply = <®_vdd_arm>; 166 cpu-supply = <®_vdd_arm>;
188 }; 167 };
189 168
190 &A53_3 { 169 &A53_3 {
191 cpu-supply = <®_vdd_arm>; 170 cpu-supply = <®_vdd_arm>;
192 }; 171 };
193 172
194 &cpu_alert0 { 173 &cpu_alert0 {
195 temperature = <95000>; 174 temperature = <95000>;
196 }; 175 };
197 176
198 &cpu_crit0 { 177 &cpu_crit0 {
199 temperature = <105000>; 178 temperature = <105000>;
200 }; 179 };
201 180
202 &ddrc { 181 &ddrc {
203 operating-points-v2 = <&ddrc_opp_table 182 operating-points-v2 = <&ddrc_opp_table>;
204 183
205 ddrc_opp_table: opp-table { 184 ddrc_opp_table: opp-table {
206 compatible = "operating-points 185 compatible = "operating-points-v2";
207 186
208 opp-25000000 { !! 187 opp-25M {
209 opp-hz = /bits/ 64 <25 188 opp-hz = /bits/ 64 <25000000>;
210 }; 189 };
211 190
212 opp-100000000 { !! 191 opp-100M {
213 opp-hz = /bits/ 64 <10 192 opp-hz = /bits/ 64 <100000000>;
214 }; 193 };
215 194
216 opp-750000000 { !! 195 opp-750M {
217 opp-hz = /bits/ 64 <75 196 opp-hz = /bits/ 64 <750000000>;
218 }; 197 };
219 }; 198 };
220 }; 199 };
221 200
222 /* Verdin SPI_1 */ 201 /* Verdin SPI_1 */
223 &ecspi2 { 202 &ecspi2 {
224 #address-cells = <1>; 203 #address-cells = <1>;
225 #size-cells = <0>; 204 #size-cells = <0>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 205 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 pinctrl-names = "default"; 206 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ecspi2>; 207 pinctrl-0 = <&pinctrl_ecspi2>;
229 }; 208 };
230 209
231 /* On-module SPI */ !! 210 /* Verdin CAN_1 (On-module) */
232 &ecspi3 { 211 &ecspi3 {
233 #address-cells = <1>; 212 #address-cells = <1>;
234 #size-cells = <0>; 213 #size-cells = <0>;
235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW> !! 214 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
236 pinctrl-names = "default"; 215 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi3>, <&pinct !! 216 pinctrl-0 = <&pinctrl_ecspi3>;
238 status = "okay"; 217 status = "okay";
239 218
240 /* Verdin CAN_1 */ <<
241 can1: can@0 { 219 can1: can@0 {
242 compatible = "microchip,mcp251 220 compatible = "microchip,mcp251xfd";
243 clocks = <&clk40m>; 221 clocks = <&clk40m>;
244 interrupts-extended = <&gpio1 222 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
245 pinctrl-names = "default"; 223 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_can1_int 224 pinctrl-0 = <&pinctrl_can1_int>;
247 reg = <0>; 225 reg = <0>;
248 spi-max-frequency = <8500000>; 226 spi-max-frequency = <8500000>;
249 }; 227 };
250 <<
251 verdin_som_tpm: tpm@1 { <<
252 compatible = "atmel,attpm20p", <<
253 reg = <0x1>; <<
254 spi-max-frequency = <36000000> <<
255 }; <<
256 }; 228 };
257 229
258 /* Verdin ETH_1 (On-module PHY) */ 230 /* Verdin ETH_1 (On-module PHY) */
259 &fec1 { 231 &fec1 {
260 fsl,magic-packet; 232 fsl,magic-packet;
261 phy-handle = <ðphy0>; 233 phy-handle = <ðphy0>;
262 phy-mode = "rgmii-id"; 234 phy-mode = "rgmii-id";
263 phy-supply = <®_ethphy>; 235 phy-supply = <®_ethphy>;
264 pinctrl-names = "default", "sleep"; 236 pinctrl-names = "default", "sleep";
265 pinctrl-0 = <&pinctrl_fec1>; 237 pinctrl-0 = <&pinctrl_fec1>;
266 pinctrl-1 = <&pinctrl_fec1_sleep>; 238 pinctrl-1 = <&pinctrl_fec1_sleep>;
267 239
268 mdio { 240 mdio {
269 #address-cells = <1>; 241 #address-cells = <1>;
270 #size-cells = <0>; 242 #size-cells = <0>;
271 243
272 ethphy0: ethernet-phy@7 { 244 ethphy0: ethernet-phy@7 {
273 compatible = "ethernet 245 compatible = "ethernet-phy-ieee802.3-c22";
274 interrupt-parent = <&g 246 interrupt-parent = <&gpio1>;
275 interrupts = <10 IRQ_T 247 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
276 micrel,led-mode = <0>; 248 micrel,led-mode = <0>;
277 reg = <7>; 249 reg = <7>;
278 }; 250 };
279 }; 251 };
280 }; 252 };
281 253
282 /* Verdin QSPI_1 */ 254 /* Verdin QSPI_1 */
283 &flexspi { 255 &flexspi {
284 pinctrl-names = "default"; 256 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexspi0>; 257 pinctrl-0 = <&pinctrl_flexspi0>;
286 }; 258 };
287 259
288 &gpio1 { 260 &gpio1 {
289 gpio-line-names = "SODIMM_216", 261 gpio-line-names = "SODIMM_216",
290 "SODIMM_19", 262 "SODIMM_19",
291 "", 263 "",
292 "", 264 "",
293 "", 265 "",
294 "", 266 "",
295 "", 267 "",
296 "", 268 "",
297 "SODIMM_220", 269 "SODIMM_220",
298 "SODIMM_222", 270 "SODIMM_222",
299 "", 271 "",
300 "SODIMM_218", 272 "SODIMM_218",
301 "SODIMM_155", 273 "SODIMM_155",
302 "SODIMM_157", 274 "SODIMM_157",
303 "SODIMM_185", 275 "SODIMM_185",
304 "SODIMM_187"; 276 "SODIMM_187";
305 }; 277 };
306 278
307 &gpio2 { 279 &gpio2 {
308 gpio-line-names = "", 280 gpio-line-names = "",
309 "", 281 "",
310 "", 282 "",
311 "", 283 "",
312 "", 284 "",
313 "", 285 "",
314 "", 286 "",
315 "", 287 "",
316 "", 288 "",
317 "", 289 "",
318 "", 290 "",
319 "", 291 "",
320 "SODIMM_84", 292 "SODIMM_84",
321 "SODIMM_78", 293 "SODIMM_78",
322 "SODIMM_74", 294 "SODIMM_74",
323 "SODIMM_80", 295 "SODIMM_80",
324 "SODIMM_82", 296 "SODIMM_82",
325 "SODIMM_70", 297 "SODIMM_70",
326 "SODIMM_72"; 298 "SODIMM_72";
327 }; 299 };
328 300
329 &gpio5 { 301 &gpio5 {
330 gpio-line-names = "SODIMM_131", 302 gpio-line-names = "SODIMM_131",
331 "", 303 "",
332 "SODIMM_91", 304 "SODIMM_91",
333 "SODIMM_16", 305 "SODIMM_16",
334 "SODIMM_15", 306 "SODIMM_15",
335 "SODIMM_208", 307 "SODIMM_208",
336 "SODIMM_137", 308 "SODIMM_137",
337 "SODIMM_139", 309 "SODIMM_139",
338 "SODIMM_141", 310 "SODIMM_141",
339 "SODIMM_143", 311 "SODIMM_143",
340 "SODIMM_196", 312 "SODIMM_196",
341 "SODIMM_200", 313 "SODIMM_200",
342 "SODIMM_198", 314 "SODIMM_198",
343 "SODIMM_202", 315 "SODIMM_202",
344 "", 316 "",
345 "", 317 "",
346 "SODIMM_55", 318 "SODIMM_55",
347 "SODIMM_53", 319 "SODIMM_53",
348 "SODIMM_95", 320 "SODIMM_95",
349 "SODIMM_93", 321 "SODIMM_93",
350 "SODIMM_14", 322 "SODIMM_14",
351 "SODIMM_12", 323 "SODIMM_12",
352 "", 324 "",
353 "", 325 "",
354 "", 326 "",
355 "", 327 "",
356 "SODIMM_210", 328 "SODIMM_210",
357 "SODIMM_212", 329 "SODIMM_212",
358 "SODIMM_151", 330 "SODIMM_151",
359 "SODIMM_153"; 331 "SODIMM_153";
>> 332
>> 333 ctrl-sleep-moci-hog {
>> 334 gpio-hog;
>> 335 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
>> 336 gpios = <1 GPIO_ACTIVE_HIGH>;
>> 337 line-name = "CTRL_SLEEP_MOCI#";
>> 338 output-high;
>> 339 pinctrl-names = "default";
>> 340 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
>> 341 };
360 }; 342 };
361 343
362 /* On-module I2C */ 344 /* On-module I2C */
363 &i2c1 { 345 &i2c1 {
364 clock-frequency = <400000>; 346 clock-frequency = <400000>;
365 pinctrl-names = "default", "gpio"; 347 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c1>; 348 pinctrl-0 = <&pinctrl_i2c1>;
367 pinctrl-1 = <&pinctrl_i2c1_gpio>; 349 pinctrl-1 = <&pinctrl_i2c1_gpio>;
368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 350 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 351 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
370 status = "okay"; 352 status = "okay";
371 353
372 pca9450: pmic@25 { 354 pca9450: pmic@25 {
373 compatible = "nxp,pca9450a"; 355 compatible = "nxp,pca9450a";
374 interrupt-parent = <&gpio1>; 356 interrupt-parent = <&gpio1>;
375 /* PMIC PCA9450 PMIC_nINT GPIO 357 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
376 interrupts = <3 IRQ_TYPE_LEVEL 358 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
377 pinctrl-names = "default"; 359 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pmic>; 360 pinctrl-0 = <&pinctrl_pmic>;
379 reg = <0x25>; 361 reg = <0x25>;
>> 362 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
380 363
381 /* 364 /*
382 * The bootloader is expected 365 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
383 * behind this PMIC. 366 * behind this PMIC.
384 */ 367 */
385 368
386 regulators { 369 regulators {
387 reg_vdd_soc: BUCK1 { 370 reg_vdd_soc: BUCK1 {
388 nxp,dvs-run-vo 371 nxp,dvs-run-voltage = <850000>;
389 nxp,dvs-standb 372 nxp,dvs-standby-voltage = <800000>;
390 regulator-alwa 373 regulator-always-on;
391 regulator-boot 374 regulator-boot-on;
392 regulator-max- 375 regulator-max-microvolt = <850000>;
393 regulator-min- 376 regulator-min-microvolt = <800000>;
394 regulator-name 377 regulator-name = "On-module +VDD_SOC (BUCK1)";
395 regulator-ramp 378 regulator-ramp-delay = <3125>;
396 }; 379 };
397 380
398 reg_vdd_arm: BUCK2 { 381 reg_vdd_arm: BUCK2 {
399 nxp,dvs-run-vo 382 nxp,dvs-run-voltage = <950000>;
400 nxp,dvs-standb 383 nxp,dvs-standby-voltage = <850000>;
401 regulator-alwa 384 regulator-always-on;
402 regulator-boot 385 regulator-boot-on;
403 regulator-max- 386 regulator-max-microvolt = <1050000>;
404 regulator-min- 387 regulator-min-microvolt = <805000>;
405 regulator-name 388 regulator-name = "On-module +VDD_ARM (BUCK2)";
406 regulator-ramp 389 regulator-ramp-delay = <3125>;
407 }; 390 };
408 391
409 reg_vdd_dram: BUCK3 { 392 reg_vdd_dram: BUCK3 {
410 regulator-alwa 393 regulator-always-on;
411 regulator-boot 394 regulator-boot-on;
412 regulator-max- 395 regulator-max-microvolt = <1000000>;
413 regulator-min- 396 regulator-min-microvolt = <805000>;
414 regulator-name 397 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
415 }; 398 };
416 399
417 reg_vdd_3v3: BUCK4 { 400 reg_vdd_3v3: BUCK4 {
418 regulator-alwa 401 regulator-always-on;
419 regulator-boot 402 regulator-boot-on;
420 regulator-max- 403 regulator-max-microvolt = <3300000>;
421 regulator-min- 404 regulator-min-microvolt = <3300000>;
422 regulator-name 405 regulator-name = "On-module +V3.3 (BUCK4)";
423 }; 406 };
424 407
425 reg_vdd_1v8: BUCK5 { 408 reg_vdd_1v8: BUCK5 {
426 regulator-alwa 409 regulator-always-on;
427 regulator-boot 410 regulator-boot-on;
428 regulator-max- 411 regulator-max-microvolt = <1800000>;
429 regulator-min- 412 regulator-min-microvolt = <1800000>;
430 regulator-name 413 regulator-name = "PWR_1V8_MOCI (BUCK5)";
431 }; 414 };
432 415
433 reg_nvcc_dram: BUCK6 { 416 reg_nvcc_dram: BUCK6 {
434 regulator-alwa 417 regulator-always-on;
435 regulator-boot 418 regulator-boot-on;
436 regulator-max- 419 regulator-max-microvolt = <1100000>;
437 regulator-min- 420 regulator-min-microvolt = <1100000>;
438 regulator-name 421 regulator-name = "On-module +VDD_DDR (BUCK6)";
439 }; 422 };
440 423
441 reg_nvcc_snvs: LDO1 { 424 reg_nvcc_snvs: LDO1 {
442 regulator-alwa 425 regulator-always-on;
443 regulator-boot 426 regulator-boot-on;
444 regulator-max- 427 regulator-max-microvolt = <1800000>;
445 regulator-min- 428 regulator-min-microvolt = <1800000>;
446 regulator-name 429 regulator-name = "On-module +V1.8_SNVS (LDO1)";
447 }; 430 };
448 431
449 reg_vdd_snvs: LDO2 { 432 reg_vdd_snvs: LDO2 {
450 regulator-alwa 433 regulator-always-on;
451 regulator-boot 434 regulator-boot-on;
452 regulator-max- 435 regulator-max-microvolt = <800000>;
453 regulator-min- 436 regulator-min-microvolt = <800000>;
454 regulator-name 437 regulator-name = "On-module +V0.8_SNVS (LDO2)";
455 }; 438 };
456 439
457 reg_vdda: LDO3 { 440 reg_vdda: LDO3 {
458 regulator-alwa 441 regulator-always-on;
459 regulator-boot 442 regulator-boot-on;
460 regulator-max- 443 regulator-max-microvolt = <1800000>;
461 regulator-min- 444 regulator-min-microvolt = <1800000>;
462 regulator-name 445 regulator-name = "On-module +V1.8A (LDO3)";
463 }; 446 };
464 447
465 reg_vdd_phy: LDO4 { 448 reg_vdd_phy: LDO4 {
466 regulator-alwa 449 regulator-always-on;
467 regulator-boot 450 regulator-boot-on;
468 regulator-max- 451 regulator-max-microvolt = <900000>;
469 regulator-min- 452 regulator-min-microvolt = <900000>;
470 regulator-name 453 regulator-name = "On-module +V0.9_MIPI (LDO4)";
471 }; 454 };
472 455
473 reg_nvcc_sd: LDO5 { 456 reg_nvcc_sd: LDO5 {
474 regulator-max- 457 regulator-max-microvolt = <3300000>;
475 regulator-min- 458 regulator-min-microvolt = <1800000>;
476 regulator-name 459 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
477 }; 460 };
478 }; 461 };
479 }; 462 };
480 463
481 rtc_i2c: rtc@32 { 464 rtc_i2c: rtc@32 {
482 compatible = "epson,rx8130"; 465 compatible = "epson,rx8130";
483 reg = <0x32>; 466 reg = <0x32>;
484 }; 467 };
485 468
486 adc@49 { 469 adc@49 {
487 compatible = "ti,ads1015"; 470 compatible = "ti,ads1015";
488 reg = <0x49>; 471 reg = <0x49>;
489 #address-cells = <1>; 472 #address-cells = <1>;
490 #size-cells = <0>; 473 #size-cells = <0>;
491 474
492 /* Verdin I2C_1 (ADC_4 - ADC_3 475 /* Verdin I2C_1 (ADC_4 - ADC_3) */
493 channel@0 { 476 channel@0 {
494 reg = <0>; 477 reg = <0>;
495 ti,datarate = <4>; 478 ti,datarate = <4>;
496 ti,gain = <2>; 479 ti,gain = <2>;
497 }; 480 };
498 481
499 /* Verdin I2C_1 (ADC_4 - ADC_1 482 /* Verdin I2C_1 (ADC_4 - ADC_1) */
500 channel@1 { 483 channel@1 {
501 reg = <1>; 484 reg = <1>;
502 ti,datarate = <4>; 485 ti,datarate = <4>;
503 ti,gain = <2>; 486 ti,gain = <2>;
504 }; 487 };
505 488
506 /* Verdin I2C_1 (ADC_3 - ADC_1 489 /* Verdin I2C_1 (ADC_3 - ADC_1) */
507 channel@2 { 490 channel@2 {
508 reg = <2>; 491 reg = <2>;
509 ti,datarate = <4>; 492 ti,datarate = <4>;
510 ti,gain = <2>; 493 ti,gain = <2>;
511 }; 494 };
512 495
513 /* Verdin I2C_1 (ADC_2 - ADC_1 496 /* Verdin I2C_1 (ADC_2 - ADC_1) */
514 channel@3 { 497 channel@3 {
515 reg = <3>; 498 reg = <3>;
516 ti,datarate = <4>; 499 ti,datarate = <4>;
517 ti,gain = <2>; 500 ti,gain = <2>;
518 }; 501 };
519 502
520 /* Verdin I2C_1 ADC_4 */ 503 /* Verdin I2C_1 ADC_4 */
521 channel@4 { 504 channel@4 {
522 reg = <4>; 505 reg = <4>;
523 ti,datarate = <4>; 506 ti,datarate = <4>;
524 ti,gain = <2>; 507 ti,gain = <2>;
525 }; 508 };
526 509
527 /* Verdin I2C_1 ADC_3 */ 510 /* Verdin I2C_1 ADC_3 */
528 channel@5 { 511 channel@5 {
529 reg = <5>; 512 reg = <5>;
530 ti,datarate = <4>; 513 ti,datarate = <4>;
531 ti,gain = <2>; 514 ti,gain = <2>;
532 }; 515 };
533 516
534 /* Verdin I2C_1 ADC_2 */ 517 /* Verdin I2C_1 ADC_2 */
535 channel@6 { 518 channel@6 {
536 reg = <6>; 519 reg = <6>;
537 ti,datarate = <4>; 520 ti,datarate = <4>;
538 ti,gain = <2>; 521 ti,gain = <2>;
539 }; 522 };
540 523
541 /* Verdin I2C_1 ADC_1 */ 524 /* Verdin I2C_1 ADC_1 */
542 channel@7 { 525 channel@7 {
543 reg = <7>; 526 reg = <7>;
544 ti,datarate = <4>; 527 ti,datarate = <4>;
545 ti,gain = <2>; 528 ti,gain = <2>;
546 }; 529 };
547 }; 530 };
548 531
549 eeprom@50 { 532 eeprom@50 {
550 compatible = "st,24c02"; 533 compatible = "st,24c02";
551 pagesize = <16>; 534 pagesize = <16>;
552 reg = <0x50>; 535 reg = <0x50>;
553 }; 536 };
554 }; 537 };
555 538
556 /* Verdin I2C_2_DSI */ 539 /* Verdin I2C_2_DSI */
557 &i2c2 { 540 &i2c2 {
558 clock-frequency = <400000>; !! 541 clock-frequency = <10000>;
559 pinctrl-names = "default", "gpio"; 542 pinctrl-names = "default", "gpio";
560 pinctrl-0 = <&pinctrl_i2c2>; 543 pinctrl-0 = <&pinctrl_i2c2>;
561 pinctrl-1 = <&pinctrl_i2c2_gpio>; 544 pinctrl-1 = <&pinctrl_i2c2_gpio>;
562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 545 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 546 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
564 status = "disabled"; 547 status = "disabled";
565 }; 548 };
566 549
567 /* Verdin I2C_3_HDMI N/A */ 550 /* Verdin I2C_3_HDMI N/A */
568 551
569 /* Verdin I2C_4_CSI */ 552 /* Verdin I2C_4_CSI */
570 &i2c3 { 553 &i2c3 {
571 clock-frequency = <400000>; 554 clock-frequency = <400000>;
572 pinctrl-names = "default", "gpio"; 555 pinctrl-names = "default", "gpio";
573 pinctrl-0 = <&pinctrl_i2c3>; 556 pinctrl-0 = <&pinctrl_i2c3>;
574 pinctrl-1 = <&pinctrl_i2c3_gpio>; 557 pinctrl-1 = <&pinctrl_i2c3_gpio>;
575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 558 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 559 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577 }; 560 };
578 561
579 /* Verdin I2C_1 */ 562 /* Verdin I2C_1 */
580 &i2c4 { 563 &i2c4 {
581 clock-frequency = <400000>; 564 clock-frequency = <400000>;
582 pinctrl-names = "default", "gpio"; 565 pinctrl-names = "default", "gpio";
583 pinctrl-0 = <&pinctrl_i2c4>; 566 pinctrl-0 = <&pinctrl_i2c4>;
584 pinctrl-1 = <&pinctrl_i2c4_gpio>; 567 pinctrl-1 = <&pinctrl_i2c4_gpio>;
585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 568 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 569 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
587 570
588 gpio_expander_21: gpio-expander@21 { 571 gpio_expander_21: gpio-expander@21 {
589 compatible = "nxp,pcal6416"; 572 compatible = "nxp,pcal6416";
590 #gpio-cells = <2>; 573 #gpio-cells = <2>;
591 gpio-controller; 574 gpio-controller;
592 reg = <0x21>; 575 reg = <0x21>;
593 vcc-supply = <®_3p3v>; 576 vcc-supply = <®_3p3v>;
594 status = "disabled"; 577 status = "disabled";
595 }; 578 };
596 579
597 lvds_ti_sn65dsi84: bridge@2c { 580 lvds_ti_sn65dsi84: bridge@2c {
598 compatible = "ti,sn65dsi84"; 581 compatible = "ti,sn65dsi84";
599 /* Verdin GPIO_9_DSI (SN65DSI8 582 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
600 /* Verdin GPIO_10_DSI (SODIMM 583 /* Verdin GPIO_10_DSI (SODIMM 21) */
601 enable-gpios = <&gpio3 3 GPIO_ 584 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
602 pinctrl-names = "default"; 585 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_gpio_10_ 586 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
604 reg = <0x2c>; 587 reg = <0x2c>;
605 status = "disabled"; 588 status = "disabled";
606 }; 589 };
607 590
608 /* Current measurement into module VCC 591 /* Current measurement into module VCC */
609 hwmon: hwmon@40 { 592 hwmon: hwmon@40 {
610 compatible = "ti,ina219"; 593 compatible = "ti,ina219";
611 reg = <0x40>; 594 reg = <0x40>;
612 shunt-resistor = <10000>; 595 shunt-resistor = <10000>;
613 status = "disabled"; 596 status = "disabled";
614 }; 597 };
615 598
616 hdmi_lontium_lt8912: hdmi@48 { 599 hdmi_lontium_lt8912: hdmi@48 {
617 compatible = "lontium,lt8912b" 600 compatible = "lontium,lt8912b";
618 pinctrl-names = "default"; 601 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_gpio_10_ !! 602 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
620 reg = <0x48>; 603 reg = <0x48>;
621 /* Verdin GPIO_9_DSI (LT8912 I 604 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
622 /* Verdin GPIO_10_DSI (SODIMM 605 /* Verdin GPIO_10_DSI (SODIMM 21) */
623 reset-gpios = <&gpio3 3 GPIO_A 606 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
624 status = "disabled"; 607 status = "disabled";
625 }; 608 };
626 609
627 atmel_mxt_ts: touch@4a { 610 atmel_mxt_ts: touch@4a {
628 compatible = "atmel,maxtouch"; 611 compatible = "atmel,maxtouch";
629 /* 612 /*
630 * Verdin GPIO_9_DSI 613 * Verdin GPIO_9_DSI
631 * (TOUCH_INT#, SODIMM 17, als !! 614 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
632 */ 615 */
633 interrupt-parent = <&gpio3>; 616 interrupt-parent = <&gpio3>;
634 interrupts = <15 IRQ_TYPE_EDGE 617 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
635 pinctrl-names = "default"; 618 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_gpio_9_d 619 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
637 reg = <0x4a>; 620 reg = <0x4a>;
638 /* Verdin I2S_2_BCLK (TOUCH_RE 621 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
639 reset-gpios = <&gpio3 23 GPIO_ 622 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
640 status = "disabled"; 623 status = "disabled";
641 }; 624 };
642 625
643 /* Temperature sensor on carrier board 626 /* Temperature sensor on carrier board */
644 hwmon_temp: sensor@4f { 627 hwmon_temp: sensor@4f {
645 compatible = "ti,tmp75c"; 628 compatible = "ti,tmp75c";
646 reg = <0x4f>; 629 reg = <0x4f>;
647 status = "disabled"; 630 status = "disabled";
648 }; 631 };
649 632
650 /* EEPROM on display adapter (MIPI DSI 633 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
651 eeprom_display_adapter: eeprom@50 { 634 eeprom_display_adapter: eeprom@50 {
652 compatible = "st,24c02"; 635 compatible = "st,24c02";
653 pagesize = <16>; 636 pagesize = <16>;
654 reg = <0x50>; 637 reg = <0x50>;
655 status = "disabled"; 638 status = "disabled";
656 }; 639 };
657 640
658 /* EEPROM on carrier board */ 641 /* EEPROM on carrier board */
659 eeprom_carrier_board: eeprom@57 { 642 eeprom_carrier_board: eeprom@57 {
660 compatible = "st,24c02"; 643 compatible = "st,24c02";
661 pagesize = <16>; 644 pagesize = <16>;
662 reg = <0x57>; 645 reg = <0x57>;
663 status = "disabled"; 646 status = "disabled";
664 }; 647 };
665 }; 648 };
666 649
667 /* Verdin PCIE_1 */ 650 /* Verdin PCIE_1 */
668 &pcie0 { 651 &pcie0 {
669 assigned-clocks = <&clk IMX8MM_CLK_PCI 652 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
670 <&clk IMX8MM_CLK_PCI 653 <&clk IMX8MM_CLK_PCIE1_CTRL>;
671 assigned-clock-parents = <&clk IMX8MM_ 654 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
672 <&clk IMX8MM_ 655 <&clk IMX8MM_SYS_PLL2_250M>;
673 assigned-clock-rates = <10000000>, <25 656 assigned-clock-rates = <10000000>, <250000000>;
>> 657 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
>> 658 <&clk IMX8MM_CLK_PCIE1_PHY>;
>> 659 clock-names = "pcie", "pcie_aux", "pcie_bus";
674 pinctrl-names = "default"; 660 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pcie0>; 661 pinctrl-0 = <&pinctrl_pcie0>;
676 /* PCIE_1_RESET# (SODIMM 244) */ 662 /* PCIE_1_RESET# (SODIMM 244) */
677 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LO 663 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
678 }; 664 };
679 665
680 &pcie_phy { 666 &pcie_phy {
681 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 667 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
682 clock-names = "ref"; <<
683 fsl,clkreq-unsupported; 668 fsl,clkreq-unsupported;
684 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 669 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
685 fsl,tx-deemph-gen1 = <0x2d>; 670 fsl,tx-deemph-gen1 = <0x2d>;
686 fsl,tx-deemph-gen2 = <0xf>; 671 fsl,tx-deemph-gen2 = <0xf>;
687 }; 672 };
688 673
689 /* Verdin PWM_3_DSI */ 674 /* Verdin PWM_3_DSI */
690 &pwm1 { 675 &pwm1 {
691 pinctrl-names = "default"; 676 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_1>; 677 pinctrl-0 = <&pinctrl_pwm_1>;
693 #pwm-cells = <3>; 678 #pwm-cells = <3>;
694 }; 679 };
695 680
696 /* Verdin PWM_1 */ 681 /* Verdin PWM_1 */
697 &pwm2 { 682 &pwm2 {
698 pinctrl-names = "default"; 683 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_pwm_2>; 684 pinctrl-0 = <&pinctrl_pwm_2>;
700 #pwm-cells = <3>; 685 #pwm-cells = <3>;
701 }; 686 };
702 687
703 /* Verdin PWM_2 */ 688 /* Verdin PWM_2 */
704 &pwm3 { 689 &pwm3 {
705 pinctrl-names = "default"; 690 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_pwm_3>; 691 pinctrl-0 = <&pinctrl_pwm_3>;
707 #pwm-cells = <3>; 692 #pwm-cells = <3>;
708 }; 693 };
709 694
710 /* Verdin I2S_1 */ 695 /* Verdin I2S_1 */
711 &sai2 { 696 &sai2 {
712 #sound-dai-cells = <0>; 697 #sound-dai-cells = <0>;
713 assigned-clock-parents = <&clk IMX8MM_ 698 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
714 assigned-clock-rates = <24576000>; 699 assigned-clock-rates = <24576000>;
715 assigned-clocks = <&clk IMX8MM_CLK_SAI 700 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
716 pinctrl-names = "default"; 701 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_sai2>; 702 pinctrl-0 = <&pinctrl_sai2>;
718 }; 703 };
719 704
720 &snvs_pwrkey { 705 &snvs_pwrkey {
721 status = "okay"; 706 status = "okay";
722 }; 707 };
723 708
724 /* Verdin UART_3, used as the Linux console */ 709 /* Verdin UART_3, used as the Linux console */
725 &uart1 { 710 &uart1 {
726 pinctrl-names = "default"; 711 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_uart1>; 712 pinctrl-0 = <&pinctrl_uart1>;
728 }; 713 };
729 714
730 /* Verdin UART_1 */ 715 /* Verdin UART_1 */
731 &uart2 { 716 &uart2 {
732 pinctrl-names = "default"; 717 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_uart2>; 718 pinctrl-0 = <&pinctrl_uart2>;
734 uart-has-rtscts; 719 uart-has-rtscts;
735 }; 720 };
736 721
737 /* Verdin UART_2 */ 722 /* Verdin UART_2 */
738 &uart3 { 723 &uart3 {
739 pinctrl-names = "default"; 724 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_uart3>; 725 pinctrl-0 = <&pinctrl_uart3>;
741 uart-has-rtscts; 726 uart-has-rtscts;
742 }; 727 };
743 728
744 /* 729 /*
745 * Verdin UART_4 730 * Verdin UART_4
746 * Resource allocated to M4 by default, must n 731 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
747 */ 732 */
748 &uart4 { 733 &uart4 {
749 pinctrl-names = "default"; 734 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_uart4>; 735 pinctrl-0 = <&pinctrl_uart4>;
751 }; 736 };
752 737
753 /* Verdin USB_1 */ 738 /* Verdin USB_1 */
754 &usbotg1 { 739 &usbotg1 {
755 adp-disable; 740 adp-disable;
756 dr_mode = "otg"; 741 dr_mode = "otg";
757 hnp-disable; 742 hnp-disable;
>> 743 over-current-active-low;
758 samsung,picophy-dc-vol-level-adjust = 744 samsung,picophy-dc-vol-level-adjust = <7>;
759 samsung,picophy-pre-emp-curr-control = 745 samsung,picophy-pre-emp-curr-control = <3>;
760 srp-disable; 746 srp-disable;
761 vbus-supply = <®_usb_otg1_vbus>; 747 vbus-supply = <®_usb_otg1_vbus>;
762 }; 748 };
763 749
764 /* Verdin USB_2 */ 750 /* Verdin USB_2 */
765 &usbotg2 { 751 &usbotg2 {
766 dr_mode = "host"; 752 dr_mode = "host";
>> 753 over-current-active-low;
767 samsung,picophy-dc-vol-level-adjust = 754 samsung,picophy-dc-vol-level-adjust = <7>;
768 samsung,picophy-pre-emp-curr-control = 755 samsung,picophy-pre-emp-curr-control = <3>;
769 vbus-supply = <®_usb_otg2_vbus>; 756 vbus-supply = <®_usb_otg2_vbus>;
770 }; 757 };
771 758
772 &usbphynop1 { 759 &usbphynop1 {
773 vcc-supply = <®_vdd_3v3>; 760 vcc-supply = <®_vdd_3v3>;
774 }; 761 };
775 762
776 &usbphynop2 { 763 &usbphynop2 {
777 power-domains = <&pgc_otg2>; 764 power-domains = <&pgc_otg2>;
778 vcc-supply = <®_vdd_3v3>; 765 vcc-supply = <®_vdd_3v3>;
779 }; 766 };
780 767
781 /* On-module eMMC */ 768 /* On-module eMMC */
782 &usdhc1 { 769 &usdhc1 {
783 bus-width = <8>; 770 bus-width = <8>;
784 keep-power-in-suspend; 771 keep-power-in-suspend;
785 non-removable; 772 non-removable;
786 pinctrl-names = "default", "state_100m 773 pinctrl-names = "default", "state_100mhz", "state_200mhz";
787 pinctrl-0 = <&pinctrl_usdhc1>; 774 pinctrl-0 = <&pinctrl_usdhc1>;
788 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 775 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
789 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 776 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
790 status = "okay"; 777 status = "okay";
791 }; 778 };
792 779
793 /* Verdin SD_1 */ 780 /* Verdin SD_1 */
794 &usdhc2 { 781 &usdhc2 {
795 bus-width = <4>; 782 bus-width = <4>;
796 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 783 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
797 disable-wp; 784 disable-wp;
798 pinctrl-names = "default", "state_100m 785 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
799 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 786 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
800 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 787 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
801 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 788 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
802 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 789 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
803 vmmc-supply = <®_usdhc2_vmmc>; 790 vmmc-supply = <®_usdhc2_vmmc>;
804 }; 791 };
805 792
806 &wdog1 { 793 &wdog1 {
807 fsl,ext-reset-output; 794 fsl,ext-reset-output;
808 pinctrl-names = "default"; 795 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_wdog>; 796 pinctrl-0 = <&pinctrl_wdog>;
810 status = "okay"; 797 status = "okay";
811 }; 798 };
812 799
813 &iomuxc { 800 &iomuxc {
814 pinctrl-names = "default"; 801 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_gpio1>, <&pinctr 802 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
816 <&pinctrl_gpio3>, <&pinctr 803 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
817 <&pinctrl_gpio7>, <&pinctr 804 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
818 <&pinctrl_gpio_hog1>, <&pi !! 805 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
>> 806 <&pinctrl_pmic_tpm_ena>;
819 807
820 pinctrl_can1_int: can1intgrp { 808 pinctrl_can1_int: can1intgrp {
821 fsl,pins = 809 fsl,pins =
822 <MX8MM_IOMUXC_GPIO1_IO 810 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
823 }; 811 };
824 812
825 pinctrl_can2_int: can2intgrp { 813 pinctrl_can2_int: can2intgrp {
826 fsl,pins = 814 fsl,pins =
827 <MX8MM_IOMUXC_GPIO1_IO 815 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
828 }; 816 };
829 817
830 pinctrl_ctrl_sleep_moci: ctrlsleepmoci 818 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
831 fsl,pins = 819 fsl,pins =
832 <MX8MM_IOMUXC_SAI3_TXD 820 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
833 }; 821 };
834 822
835 pinctrl_ecspi2: ecspi2grp { 823 pinctrl_ecspi2: ecspi2grp {
836 fsl,pins = 824 fsl,pins =
837 <MX8MM_IOMUXC_ECSPI2_M 825 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
838 <MX8MM_IOMUXC_ECSPI2_M 826 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
839 <MX8MM_IOMUXC_ECSPI2_S 827 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
840 <MX8MM_IOMUXC_ECSPI2_S 828 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
841 }; 829 };
842 830
843 pinctrl_ecspi3: ecspi3grp { 831 pinctrl_ecspi3: ecspi3grp {
844 fsl,pins = 832 fsl,pins =
845 <MX8MM_IOMUXC_GPIO1_IO 833 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
846 <MX8MM_IOMUXC_UART1_RX 834 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
847 <MX8MM_IOMUXC_UART1_TX 835 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
848 <MX8MM_IOMUXC_UART2_RX 836 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
849 <MX8MM_IOMUXC_UART2_TX 837 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
850 }; 838 };
851 839
852 pinctrl_fec1: fec1grp { 840 pinctrl_fec1: fec1grp {
853 fsl,pins = 841 fsl,pins =
854 <MX8MM_IOMUXC_ENET_MDC 842 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
855 <MX8MM_IOMUXC_ENET_MDI 843 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
856 <MX8MM_IOMUXC_ENET_RD0 844 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
857 <MX8MM_IOMUXC_ENET_RD1 845 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
858 <MX8MM_IOMUXC_ENET_RD2 846 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
859 <MX8MM_IOMUXC_ENET_RD3 847 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
860 <MX8MM_IOMUXC_ENET_RXC 848 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
861 <MX8MM_IOMUXC_ENET_RX_ 849 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
862 <MX8MM_IOMUXC_ENET_TD0 850 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
863 <MX8MM_IOMUXC_ENET_TD1 851 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
864 <MX8MM_IOMUXC_ENET_TD2 852 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
865 <MX8MM_IOMUXC_ENET_TD3 853 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
866 <MX8MM_IOMUXC_ENET_TXC 854 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
867 <MX8MM_IOMUXC_ENET_TX_ 855 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
868 <MX8MM_IOMUXC_GPIO1_IO 856 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
869 }; 857 };
870 858
871 pinctrl_fec1_sleep: fec1-sleepgrp { 859 pinctrl_fec1_sleep: fec1-sleepgrp {
872 fsl,pins = 860 fsl,pins =
873 <MX8MM_IOMUXC_ENET_MDC 861 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
874 <MX8MM_IOMUXC_ENET_MDI 862 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
875 <MX8MM_IOMUXC_ENET_RD0 863 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
876 <MX8MM_IOMUXC_ENET_RD1 864 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
877 <MX8MM_IOMUXC_ENET_RD2 865 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
878 <MX8MM_IOMUXC_ENET_RD3 866 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
879 <MX8MM_IOMUXC_ENET_RXC 867 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
880 <MX8MM_IOMUXC_ENET_RX_ 868 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
881 <MX8MM_IOMUXC_ENET_TD0 869 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
882 <MX8MM_IOMUXC_ENET_TD1 870 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
883 <MX8MM_IOMUXC_ENET_TD2 871 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
884 <MX8MM_IOMUXC_ENET_TD3 872 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
885 <MX8MM_IOMUXC_ENET_TXC 873 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
886 <MX8MM_IOMUXC_ENET_TX_ 874 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
887 <MX8MM_IOMUXC_GPIO1_IO 875 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
888 }; 876 };
889 877
890 pinctrl_flexspi0: flexspi0grp { 878 pinctrl_flexspi0: flexspi0grp {
891 fsl,pins = 879 fsl,pins =
892 <MX8MM_IOMUXC_NAND_ALE 880 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
893 <MX8MM_IOMUXC_NAND_CE0 881 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
894 <MX8MM_IOMUXC_NAND_CE1 882 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
895 <MX8MM_IOMUXC_NAND_DAT 883 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
896 <MX8MM_IOMUXC_NAND_DAT 884 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
897 <MX8MM_IOMUXC_NAND_DAT 885 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
898 <MX8MM_IOMUXC_NAND_DAT 886 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
899 <MX8MM_IOMUXC_NAND_DQS 887 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
900 }; 888 };
901 889
902 pinctrl_gpio1: gpio1grp { 890 pinctrl_gpio1: gpio1grp {
903 fsl,pins = 891 fsl,pins =
904 <MX8MM_IOMUXC_NAND_CE3 892 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
905 }; 893 };
906 894
907 pinctrl_gpio2: gpio2grp { 895 pinctrl_gpio2: gpio2grp {
908 fsl,pins = 896 fsl,pins =
909 <MX8MM_IOMUXC_SPDIF_EX 897 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
910 }; 898 };
911 899
912 pinctrl_gpio3: gpio3grp { 900 pinctrl_gpio3: gpio3grp {
913 fsl,pins = 901 fsl,pins =
914 <MX8MM_IOMUXC_UART3_RX 902 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
915 }; 903 };
916 904
917 pinctrl_gpio4: gpio4grp { 905 pinctrl_gpio4: gpio4grp {
918 fsl,pins = 906 fsl,pins =
919 <MX8MM_IOMUXC_UART3_TX 907 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
920 }; 908 };
921 909
922 pinctrl_gpio5: gpio5grp { 910 pinctrl_gpio5: gpio5grp {
923 fsl,pins = 911 fsl,pins =
924 <MX8MM_IOMUXC_GPIO1_IO 912 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
925 }; 913 };
926 914
927 pinctrl_gpio6: gpio6grp { 915 pinctrl_gpio6: gpio6grp {
928 fsl,pins = 916 fsl,pins =
929 <MX8MM_IOMUXC_GPIO1_IO 917 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
930 }; 918 };
931 919
932 pinctrl_gpio7: gpio7grp { 920 pinctrl_gpio7: gpio7grp {
933 fsl,pins = 921 fsl,pins =
934 <MX8MM_IOMUXC_GPIO1_IO 922 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
935 }; 923 };
936 924
937 pinctrl_gpio8: gpio8grp { 925 pinctrl_gpio8: gpio8grp {
938 fsl,pins = 926 fsl,pins =
939 <MX8MM_IOMUXC_GPIO1_IO 927 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
940 }; 928 };
941 929
942 /* Verdin GPIO_9_DSI (pulled-up as act 930 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
943 pinctrl_gpio_9_dsi: gpio9dsigrp { 931 pinctrl_gpio_9_dsi: gpio9dsigrp {
944 fsl,pins = 932 fsl,pins =
945 <MX8MM_IOMUXC_NAND_RE_ 933 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */
946 }; 934 };
947 935
948 /* Verdin GPIO_10_DSI (pulled-up as ac 936 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
949 pinctrl_gpio_10_dsi: gpio10dsigrp { 937 pinctrl_gpio_10_dsi: gpio10dsigrp {
950 fsl,pins = 938 fsl,pins =
951 <MX8MM_IOMUXC_NAND_CE2 939 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
952 }; 940 };
953 941
954 pinctrl_gpio_hog1: gpiohog1grp { 942 pinctrl_gpio_hog1: gpiohog1grp {
955 fsl,pins = 943 fsl,pins =
956 <MX8MM_IOMUXC_SAI1_MCL 944 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
957 <MX8MM_IOMUXC_SAI1_RXC 945 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
958 <MX8MM_IOMUXC_SAI1_RXD 946 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
959 <MX8MM_IOMUXC_SAI1_RXD 947 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
960 <MX8MM_IOMUXC_SAI1_RXD 948 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
961 <MX8MM_IOMUXC_SAI1_RXD 949 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
962 <MX8MM_IOMUXC_SAI1_RXF 950 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
963 <MX8MM_IOMUXC_SAI1_TXC 951 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
964 <MX8MM_IOMUXC_SAI1_TXD 952 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
965 <MX8MM_IOMUXC_SAI1_TXD 953 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
966 <MX8MM_IOMUXC_SAI1_TXD 954 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
967 <MX8MM_IOMUXC_SAI1_TXD 955 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
968 <MX8MM_IOMUXC_SAI1_TXD 956 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
969 <MX8MM_IOMUXC_SAI1_TXD 957 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
970 <MX8MM_IOMUXC_SAI1_TXF 958 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
971 }; 959 };
972 960
973 pinctrl_gpio_hog2: gpiohog2grp { 961 pinctrl_gpio_hog2: gpiohog2grp {
974 fsl,pins = 962 fsl,pins =
975 <MX8MM_IOMUXC_SAI3_MCL 963 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
976 }; 964 };
977 965
978 pinctrl_gpio_hog3: gpiohog3grp { 966 pinctrl_gpio_hog3: gpiohog3grp {
979 fsl,pins = 967 fsl,pins =
980 <MX8MM_IOMUXC_GPIO1_IO 968 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
981 <MX8MM_IOMUXC_GPIO1_IO 969 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
982 }; 970 };
983 971
984 pinctrl_gpio_keys: gpiokeysgrp { 972 pinctrl_gpio_keys: gpiokeysgrp {
985 fsl,pins = 973 fsl,pins =
986 <MX8MM_IOMUXC_SAI3_RXF 974 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
987 }; 975 };
988 976
989 /* On-module I2C */ 977 /* On-module I2C */
990 pinctrl_i2c1: i2c1grp { 978 pinctrl_i2c1: i2c1grp {
991 fsl,pins = 979 fsl,pins =
992 <MX8MM_IOMUXC_I2C1_SCL 980 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
993 <MX8MM_IOMUXC_I2C1_SDA 981 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
994 }; 982 };
995 983
996 pinctrl_i2c1_gpio: i2c1gpiogrp { 984 pinctrl_i2c1_gpio: i2c1gpiogrp {
997 fsl,pins = 985 fsl,pins =
998 <MX8MM_IOMUXC_I2C1_SCL 986 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
999 <MX8MM_IOMUXC_I2C1_SDA 987 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
1000 }; 988 };
1001 989
1002 /* Verdin I2C_4_CSI */ 990 /* Verdin I2C_4_CSI */
1003 pinctrl_i2c2: i2c2grp { 991 pinctrl_i2c2: i2c2grp {
1004 fsl,pins = 992 fsl,pins =
1005 <MX8MM_IOMUXC_I2C2_SC 993 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
1006 <MX8MM_IOMUXC_I2C2_SD 994 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
1007 }; 995 };
1008 996
1009 pinctrl_i2c2_gpio: i2c2gpiogrp { 997 pinctrl_i2c2_gpio: i2c2gpiogrp {
1010 fsl,pins = 998 fsl,pins =
1011 <MX8MM_IOMUXC_I2C2_SC 999 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
1012 <MX8MM_IOMUXC_I2C2_SD 1000 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1013 }; 1001 };
1014 1002
1015 /* Verdin I2C_2_DSI */ 1003 /* Verdin I2C_2_DSI */
1016 pinctrl_i2c3: i2c3grp { 1004 pinctrl_i2c3: i2c3grp {
1017 fsl,pins = 1005 fsl,pins =
1018 <MX8MM_IOMUXC_I2C3_SC 1006 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1019 <MX8MM_IOMUXC_I2C3_SD 1007 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1020 }; 1008 };
1021 1009
1022 pinctrl_i2c3_gpio: i2c3gpiogrp { 1010 pinctrl_i2c3_gpio: i2c3gpiogrp {
1023 fsl,pins = 1011 fsl,pins =
1024 <MX8MM_IOMUXC_I2C3_SC 1012 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1025 <MX8MM_IOMUXC_I2C3_SD 1013 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1026 }; 1014 };
1027 1015
1028 /* Verdin I2C_1 */ 1016 /* Verdin I2C_1 */
1029 pinctrl_i2c4: i2c4grp { 1017 pinctrl_i2c4: i2c4grp {
1030 fsl,pins = 1018 fsl,pins =
1031 <MX8MM_IOMUXC_I2C4_SC 1019 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1032 <MX8MM_IOMUXC_I2C4_SD 1020 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1033 }; 1021 };
1034 1022
1035 pinctrl_i2c4_gpio: i2c4gpiogrp { 1023 pinctrl_i2c4_gpio: i2c4gpiogrp {
1036 fsl,pins = 1024 fsl,pins =
1037 <MX8MM_IOMUXC_I2C4_SC 1025 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1038 <MX8MM_IOMUXC_I2C4_SD 1026 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1039 }; 1027 };
1040 1028
1041 /* Verdin I2S_2_BCLK (TOUCH_RESET#) * 1029 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1042 pinctrl_i2s_2_bclk_touch_reset: i2s2b 1030 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1043 fsl,pins = 1031 fsl,pins =
1044 <MX8MM_IOMUXC_SAI5_RX 1032 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1045 }; 1033 };
1046 1034
1047 /* Verdin I2S_2_D_OUT shared with SAI 1035 /* Verdin I2S_2_D_OUT shared with SAI5 */
1048 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s 1036 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1049 fsl,pins = 1037 fsl,pins =
1050 <MX8MM_IOMUXC_SAI5_RX 1038 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1051 }; 1039 };
1052 1040
1053 pinctrl_pcie0: pcie0grp { 1041 pinctrl_pcie0: pcie0grp {
1054 fsl,pins = 1042 fsl,pins =
1055 <MX8MM_IOMUXC_SAI5_RX 1043 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1056 /* PMIC_EN_PCIe_CLK, 1044 /* PMIC_EN_PCIe_CLK, unused */
1057 <MX8MM_IOMUXC_SD2_RES 1045 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1058 }; 1046 };
1059 1047
1060 pinctrl_pmic: pmicirqgrp { 1048 pinctrl_pmic: pmicirqgrp {
1061 fsl,pins = 1049 fsl,pins =
1062 <MX8MM_IOMUXC_GPIO1_I 1050 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1063 }; 1051 };
1064 1052
1065 /* Verdin PWM_3_DSI shared with GPIO1 1053 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1066 pinctrl_pwm_1: pwm1grp { 1054 pinctrl_pwm_1: pwm1grp {
1067 fsl,pins = 1055 fsl,pins =
1068 <MX8MM_IOMUXC_GPIO1_I 1056 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1069 }; 1057 };
1070 1058
1071 pinctrl_pwm_2: pwm2grp { 1059 pinctrl_pwm_2: pwm2grp {
1072 fsl,pins = 1060 fsl,pins =
1073 <MX8MM_IOMUXC_SPDIF_R 1061 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1074 }; 1062 };
1075 1063
1076 pinctrl_pwm_3: pwm3grp { 1064 pinctrl_pwm_3: pwm3grp {
1077 fsl,pins = 1065 fsl,pins =
1078 <MX8MM_IOMUXC_SPDIF_T 1066 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1079 }; 1067 };
1080 1068
1081 /* Verdin PWM_3_DSI (pulled-down as a 1069 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1082 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihp 1070 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1083 fsl,pins = 1071 fsl,pins =
1084 <MX8MM_IOMUXC_GPIO1_I 1072 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1085 }; 1073 };
1086 1074
1087 pinctrl_reg_eth: regethgrp { 1075 pinctrl_reg_eth: regethgrp {
1088 fsl,pins = 1076 fsl,pins =
1089 <MX8MM_IOMUXC_SD2_WP_ 1077 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1090 }; 1078 };
1091 1079
1092 pinctrl_reg_usb1_en: regusb1engrp { 1080 pinctrl_reg_usb1_en: regusb1engrp {
1093 fsl,pins = 1081 fsl,pins =
1094 <MX8MM_IOMUXC_GPIO1_I 1082 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1095 }; 1083 };
1096 1084
1097 pinctrl_reg_usb2_en: regusb2engrp { 1085 pinctrl_reg_usb2_en: regusb2engrp {
1098 fsl,pins = 1086 fsl,pins =
1099 <MX8MM_IOMUXC_GPIO1_I 1087 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1100 }; 1088 };
1101 1089
1102 pinctrl_sai2: sai2grp { 1090 pinctrl_sai2: sai2grp {
1103 fsl,pins = 1091 fsl,pins =
1104 <MX8MM_IOMUXC_SAI2_MC 1092 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1105 <MX8MM_IOMUXC_SAI2_TX 1093 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1106 <MX8MM_IOMUXC_SAI2_TX 1094 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1107 <MX8MM_IOMUXC_SAI2_RX 1095 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1108 <MX8MM_IOMUXC_SAI2_TX 1096 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1109 }; 1097 };
1110 1098
1111 pinctrl_sai5: sai5grp { 1099 pinctrl_sai5: sai5grp {
1112 fsl,pins = 1100 fsl,pins =
1113 <MX8MM_IOMUXC_SAI5_RX 1101 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1114 <MX8MM_IOMUXC_SAI5_RX 1102 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1115 <MX8MM_IOMUXC_SAI5_RX 1103 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1116 <MX8MM_IOMUXC_SAI5_RX 1104 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1117 }; 1105 };
1118 1106
1119 /* control signal for optional ATTPM2 1107 /* control signal for optional ATTPM20P or SE050 */
1120 pinctrl_tpm_spi_cs: tpmspicsgrp { !! 1108 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1121 fsl,pins = 1109 fsl,pins =
1122 <MX8MM_IOMUXC_SAI1_TX 1110 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1123 }; 1111 };
1124 1112
1125 pinctrl_tsp: tspgrp { 1113 pinctrl_tsp: tspgrp {
1126 fsl,pins = 1114 fsl,pins =
1127 <MX8MM_IOMUXC_SAI1_RX 1115 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1128 <MX8MM_IOMUXC_SAI1_RX 1116 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1129 <MX8MM_IOMUXC_SAI1_RX 1117 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1130 <MX8MM_IOMUXC_SAI1_RX 1118 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1131 <MX8MM_IOMUXC_SAI1_TX 1119 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1132 }; 1120 };
1133 1121
1134 pinctrl_uart1: uart1grp { 1122 pinctrl_uart1: uart1grp {
1135 fsl,pins = 1123 fsl,pins =
1136 <MX8MM_IOMUXC_SAI2_RX 1124 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1137 <MX8MM_IOMUXC_SAI2_RX 1125 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1138 }; 1126 };
1139 1127
1140 pinctrl_uart2: uart2grp { 1128 pinctrl_uart2: uart2grp {
1141 fsl,pins = 1129 fsl,pins =
1142 <MX8MM_IOMUXC_SAI3_RX 1130 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1143 <MX8MM_IOMUXC_SAI3_RX 1131 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1144 <MX8MM_IOMUXC_SAI3_TX 1132 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1145 <MX8MM_IOMUXC_SAI3_TX 1133 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1146 }; 1134 };
1147 1135
1148 pinctrl_uart3: uart3grp { 1136 pinctrl_uart3: uart3grp {
1149 fsl,pins = 1137 fsl,pins =
1150 <MX8MM_IOMUXC_ECSPI1_ 1138 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1151 <MX8MM_IOMUXC_ECSPI1_ 1139 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1152 <MX8MM_IOMUXC_ECSPI1_ 1140 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1153 <MX8MM_IOMUXC_ECSPI1_ 1141 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1154 }; 1142 };
1155 1143
1156 pinctrl_uart4: uart4grp { 1144 pinctrl_uart4: uart4grp {
1157 fsl,pins = 1145 fsl,pins =
1158 <MX8MM_IOMUXC_UART4_R 1146 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1159 <MX8MM_IOMUXC_UART4_T 1147 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1160 }; 1148 };
1161 1149
1162 pinctrl_usdhc1: usdhc1grp { 1150 pinctrl_usdhc1: usdhc1grp {
1163 fsl,pins = 1151 fsl,pins =
1164 <MX8MM_IOMUXC_SD1_CLK 1152 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1165 <MX8MM_IOMUXC_SD1_CMD 1153 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1166 <MX8MM_IOMUXC_SD1_DAT 1154 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1167 <MX8MM_IOMUXC_SD1_DAT 1155 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1168 <MX8MM_IOMUXC_SD1_DAT 1156 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1169 <MX8MM_IOMUXC_SD1_DAT 1157 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1170 <MX8MM_IOMUXC_SD1_DAT 1158 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1171 <MX8MM_IOMUXC_SD1_DAT 1159 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1172 <MX8MM_IOMUXC_SD1_DAT 1160 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1173 <MX8MM_IOMUXC_SD1_DAT 1161 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1174 <MX8MM_IOMUXC_SD1_RES 1162 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1175 <MX8MM_IOMUXC_SD1_STR 1163 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1176 }; 1164 };
1177 1165
1178 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1166 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1179 fsl,pins = 1167 fsl,pins =
1180 <MX8MM_IOMUXC_SD1_CLK 1168 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1181 <MX8MM_IOMUXC_SD1_CMD 1169 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1182 <MX8MM_IOMUXC_SD1_DAT 1170 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1183 <MX8MM_IOMUXC_SD1_DAT 1171 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1184 <MX8MM_IOMUXC_SD1_DAT 1172 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1185 <MX8MM_IOMUXC_SD1_DAT 1173 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1186 <MX8MM_IOMUXC_SD1_DAT 1174 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1187 <MX8MM_IOMUXC_SD1_DAT 1175 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1188 <MX8MM_IOMUXC_SD1_DAT 1176 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1189 <MX8MM_IOMUXC_SD1_DAT 1177 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1190 <MX8MM_IOMUXC_SD1_RES 1178 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1191 <MX8MM_IOMUXC_SD1_STR 1179 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1192 }; 1180 };
1193 1181
1194 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1182 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1195 fsl,pins = 1183 fsl,pins =
1196 <MX8MM_IOMUXC_SD1_CLK 1184 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1197 <MX8MM_IOMUXC_SD1_CMD 1185 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1198 <MX8MM_IOMUXC_SD1_DAT 1186 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1199 <MX8MM_IOMUXC_SD1_DAT 1187 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1200 <MX8MM_IOMUXC_SD1_DAT 1188 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1201 <MX8MM_IOMUXC_SD1_DAT 1189 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1202 <MX8MM_IOMUXC_SD1_DAT 1190 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1203 <MX8MM_IOMUXC_SD1_DAT 1191 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1204 <MX8MM_IOMUXC_SD1_DAT 1192 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1205 <MX8MM_IOMUXC_SD1_DAT 1193 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1206 <MX8MM_IOMUXC_SD1_RES 1194 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1207 <MX8MM_IOMUXC_SD1_STR 1195 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1208 }; 1196 };
1209 1197
1210 pinctrl_usdhc2_cd: usdhc2cdgrp { 1198 pinctrl_usdhc2_cd: usdhc2cdgrp {
1211 fsl,pins = 1199 fsl,pins =
1212 <MX8MM_IOMUXC_SD2_CD_ 1200 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1213 }; 1201 };
1214 1202
1215 pinctrl_usdhc2_cd_sleep: usdhc2cdslpg 1203 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1216 fsl,pins = 1204 fsl,pins =
1217 <MX8MM_IOMUXC_SD2_CD_ 1205 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1218 }; 1206 };
1219 1207
1220 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp 1208 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1221 fsl,pins = 1209 fsl,pins =
1222 <MX8MM_IOMUXC_NAND_CL 1210 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1223 }; 1211 };
1224 1212
1225 /* 1213 /*
1226 * Note: Due to ERR050080 we use disc 1214 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1227 * on-module +V3.3_1.8_SD (LDO5) rail 1215 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1228 */ 1216 */
1229 pinctrl_usdhc2: usdhc2grp { 1217 pinctrl_usdhc2: usdhc2grp {
1230 fsl,pins = 1218 fsl,pins =
1231 <MX8MM_IOMUXC_GPIO1_I 1219 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1232 <MX8MM_IOMUXC_SD2_CLK 1220 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1233 <MX8MM_IOMUXC_SD2_CMD 1221 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1234 <MX8MM_IOMUXC_SD2_DAT 1222 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1235 <MX8MM_IOMUXC_SD2_DAT 1223 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1236 <MX8MM_IOMUXC_SD2_DAT 1224 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1237 <MX8MM_IOMUXC_SD2_DAT 1225 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1238 }; 1226 };
1239 1227
1240 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1228 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1241 fsl,pins = 1229 fsl,pins =
1242 <MX8MM_IOMUXC_GPIO1_I 1230 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1243 <MX8MM_IOMUXC_SD2_CLK 1231 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1244 <MX8MM_IOMUXC_SD2_CMD 1232 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1245 <MX8MM_IOMUXC_SD2_DAT 1233 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1246 <MX8MM_IOMUXC_SD2_DAT 1234 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1247 <MX8MM_IOMUXC_SD2_DAT 1235 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1248 <MX8MM_IOMUXC_SD2_DAT 1236 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1249 }; 1237 };
1250 1238
1251 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1239 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1252 fsl,pins = 1240 fsl,pins =
1253 <MX8MM_IOMUXC_GPIO1_I 1241 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1254 <MX8MM_IOMUXC_SD2_CLK 1242 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1255 <MX8MM_IOMUXC_SD2_CMD 1243 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1256 <MX8MM_IOMUXC_SD2_DAT 1244 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1257 <MX8MM_IOMUXC_SD2_DAT 1245 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1258 <MX8MM_IOMUXC_SD2_DAT 1246 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1259 <MX8MM_IOMUXC_SD2_DAT 1247 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1260 }; 1248 };
1261 1249
1262 /* Avoid backfeeding with removed car 1250 /* Avoid backfeeding with removed card power */
1263 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1251 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1264 fsl,pins = 1252 fsl,pins =
1265 <MX8MM_IOMUXC_GPIO1_I 1253 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1266 <MX8MM_IOMUXC_SD2_CLK 1254 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1267 <MX8MM_IOMUXC_SD2_CMD 1255 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1268 <MX8MM_IOMUXC_SD2_DAT 1256 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1269 <MX8MM_IOMUXC_SD2_DAT 1257 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1270 <MX8MM_IOMUXC_SD2_DAT 1258 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1271 <MX8MM_IOMUXC_SD2_DAT 1259 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1272 }; 1260 };
1273 1261
1274 /* 1262 /*
1275 * On-module Wi-Fi/BT or type specifi 1263 * On-module Wi-Fi/BT or type specific SDHC interface
1276 * (e.g. on X52 extension slot of Ver 1264 * (e.g. on X52 extension slot of Verdin Development Board)
1277 */ 1265 */
1278 pinctrl_usdhc3: usdhc3grp { 1266 pinctrl_usdhc3: usdhc3grp {
1279 fsl,pins = 1267 fsl,pins =
1280 <MX8MM_IOMUXC_NAND_DA 1268 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1281 <MX8MM_IOMUXC_NAND_DA 1269 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1282 <MX8MM_IOMUXC_NAND_DA 1270 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1283 <MX8MM_IOMUXC_NAND_DA 1271 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1284 <MX8MM_IOMUXC_NAND_WE 1272 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1285 <MX8MM_IOMUXC_NAND_WP 1273 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1286 }; 1274 };
1287 1275
1288 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1276 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1289 fsl,pins = 1277 fsl,pins =
1290 <MX8MM_IOMUXC_NAND_DA 1278 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1291 <MX8MM_IOMUXC_NAND_DA 1279 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1292 <MX8MM_IOMUXC_NAND_DA 1280 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1293 <MX8MM_IOMUXC_NAND_DA 1281 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1294 <MX8MM_IOMUXC_NAND_WE 1282 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1295 <MX8MM_IOMUXC_NAND_WP 1283 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1296 }; 1284 };
1297 1285
1298 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1286 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1299 fsl,pins = 1287 fsl,pins =
1300 <MX8MM_IOMUXC_NAND_DA 1288 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1301 <MX8MM_IOMUXC_NAND_DA 1289 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1302 <MX8MM_IOMUXC_NAND_DA 1290 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1303 <MX8MM_IOMUXC_NAND_DA 1291 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1304 <MX8MM_IOMUXC_NAND_WE 1292 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1305 <MX8MM_IOMUXC_NAND_WP 1293 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1306 }; 1294 };
1307 1295
1308 pinctrl_wdog: wdoggrp { 1296 pinctrl_wdog: wdoggrp {
1309 fsl,pins = 1297 fsl,pins =
1310 <MX8MM_IOMUXC_GPIO1_I 1298 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1311 }; 1299 };
1312 1300
1313 pinctrl_wifi_ctrl: wifictrlgrp { 1301 pinctrl_wifi_ctrl: wifictrlgrp {
1314 fsl,pins = 1302 fsl,pins =
1315 <MX8MM_IOMUXC_NAND_RE 1303 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1316 <MX8MM_IOMUXC_SAI1_RX 1304 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1317 <MX8MM_IOMUXC_SAI5_RX 1305 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1318 }; 1306 };
1319 1307
1320 pinctrl_wifi_i2s: bti2sgrp { 1308 pinctrl_wifi_i2s: bti2sgrp {
1321 fsl,pins = 1309 fsl,pins =
1322 <MX8MM_IOMUXC_SAI1_RX 1310 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1323 <MX8MM_IOMUXC_SAI1_RX 1311 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1324 <MX8MM_IOMUXC_SAI1_RX 1312 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1325 <MX8MM_IOMUXC_SAI1_TX 1313 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1326 }; 1314 };
1327 1315
1328 pinctrl_wifi_pwr_en: wifipwrengrp { 1316 pinctrl_wifi_pwr_en: wifipwrengrp {
1329 fsl,pins = 1317 fsl,pins =
1330 <MX8MM_IOMUXC_SAI5_MC 1318 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1331 }; 1319 };
1332 }; 1320 };
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