1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy-imx8-pcie.h> 6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h> 7 #include <dt-bindings/pwm/pwm.h>
8 #include "imx8mm.dtsi" 8 #include "imx8mm.dtsi"
9 #include "imx8mm-overdrive.dtsi" <<
10 9
11 / { 10 / {
12 chosen { 11 chosen {
13 stdout-path = &uart1; 12 stdout-path = &uart1;
14 }; 13 };
15 14
16 aliases { 15 aliases {
17 rtc0 = &rtc_i2c; 16 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc; 17 rtc1 = &snvs_rtc;
19 }; 18 };
20 19
21 backlight: backlight { 20 backlight: backlight {
22 compatible = "pwm-backlight"; 21 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 8 22 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4> 23 default-brightness-level = <4>;
25 /* Verdin I2S_2_D_OUT (DSI_1_B 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
26 enable-gpios = <&gpio3 24 GPIO 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default"; 26 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_i2s_2_d_ 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
29 power-supply = <®_3p3v>; 28 power-supply = <®_3p3v>;
30 /* Verdin PWM_3_DSI/PWM_3_DSI_ 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
31 pwms = <&pwm1 0 6666667 PWM_PO 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 /* Fixed clock dedicated to SPI CAN co 34 /* Fixed clock dedicated to SPI CAN controller */
36 clk40m: oscillator { 35 clk40m: oscillator {
37 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
38 #clock-cells = <0>; 37 #clock-cells = <0>;
39 clock-frequency = <40000000>; 38 clock-frequency = <40000000>;
40 }; 39 };
41 40
42 gpio-keys { 41 gpio-keys {
43 compatible = "gpio-keys"; 42 compatible = "gpio-keys";
44 pinctrl-names = "default"; 43 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_key 44 pinctrl-0 = <&pinctrl_gpio_keys>;
46 45
47 key-wakeup { 46 key-wakeup {
48 debounce-interval = <1 47 debounce-interval = <10>;
49 /* Verdin CTRL_WAKE1_M 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
50 gpios = <&gpio4 28 GPI 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 label = "Wake-Up"; 50 label = "Wake-Up";
52 linux,code = <KEY_WAKE 51 linux,code = <KEY_WAKEUP>;
53 wakeup-source; 52 wakeup-source;
54 }; 53 };
55 }; 54 };
56 55
57 hdmi_connector: hdmi-connector { 56 hdmi_connector: hdmi-connector {
58 compatible = "hdmi-connector"; 57 compatible = "hdmi-connector";
59 ddc-i2c-bus = <&i2c2>; 58 ddc-i2c-bus = <&i2c2>;
60 /* Verdin PWM_3_DSI (SODIMM 19 59 /* Verdin PWM_3_DSI (SODIMM 19) */
61 hpd-gpios = <&gpio1 1 GPIO_ACT 60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
62 label = "hdmi"; 61 label = "hdmi";
63 pinctrl-names = "default"; 62 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pwm_3_ds 63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
65 type = "a"; 64 type = "a";
66 status = "disabled"; 65 status = "disabled";
67 }; 66 };
68 67
69 panel_lvds: panel-lvds { 68 panel_lvds: panel-lvds {
70 compatible = "panel-lvds"; 69 compatible = "panel-lvds";
71 backlight = <&backlight>; 70 backlight = <&backlight>;
72 data-mapping = "vesa-24"; 71 data-mapping = "vesa-24";
73 status = "disabled"; 72 status = "disabled";
74 }; 73 };
75 74
76 /* Carrier Board Supplies */ 75 /* Carrier Board Supplies */
77 reg_1p8v: regulator-1p8v { 76 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed" 77 compatible = "regulator-fixed";
79 regulator-max-microvolt = <180 78 regulator-max-microvolt = <1800000>;
80 regulator-min-microvolt = <180 79 regulator-min-microvolt = <1800000>;
81 regulator-name = "+V1.8_SW"; 80 regulator-name = "+V1.8_SW";
82 }; 81 };
83 82
84 reg_3p3v: regulator-3p3v { 83 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed" 84 compatible = "regulator-fixed";
86 regulator-max-microvolt = <330 85 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <330 86 regulator-min-microvolt = <3300000>;
88 regulator-name = "+V3.3_SW"; 87 regulator-name = "+V3.3_SW";
89 }; 88 };
90 89
91 reg_5p0v: regulator-5p0v { 90 reg_5p0v: regulator-5p0v {
92 compatible = "regulator-fixed" 91 compatible = "regulator-fixed";
93 regulator-max-microvolt = <500 92 regulator-max-microvolt = <5000000>;
94 regulator-min-microvolt = <500 93 regulator-min-microvolt = <5000000>;
95 regulator-name = "+V5_SW"; 94 regulator-name = "+V5_SW";
96 }; 95 };
97 96
98 /* Non PMIC On-module Supplies */ 97 /* Non PMIC On-module Supplies */
99 reg_ethphy: regulator-ethphy { 98 reg_ethphy: regulator-ethphy {
100 compatible = "regulator-fixed" 99 compatible = "regulator-fixed";
101 enable-active-high; 100 enable-active-high;
102 gpio = <&gpio2 20 GPIO_ACTIVE_ 101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
103 off-on-delay-us = <500000>; 102 off-on-delay-us = <500000>;
104 pinctrl-names = "default"; 103 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_eth> 104 pinctrl-0 = <&pinctrl_reg_eth>;
106 regulator-always-on; 105 regulator-always-on;
107 regulator-boot-on; 106 regulator-boot-on;
108 regulator-max-microvolt = <330 107 regulator-max-microvolt = <3300000>;
109 regulator-min-microvolt = <330 108 regulator-min-microvolt = <3300000>;
110 regulator-name = "On-module +V 109 regulator-name = "On-module +V3.3_ETH";
111 startup-delay-us = <200000>; 110 startup-delay-us = <200000>;
112 }; 111 };
113 112
114 /* <<
115 * By default we enable CTRL_SLEEP_MOC <<
116 * peripherals on the carrier board po <<
117 * If more granularity or power saving <<
118 * in the carrier board device tree fi <<
119 */ <<
120 reg_force_sleep_moci: regulator-force- <<
121 compatible = "regulator-fixed" <<
122 enable-active-high; <<
123 /* Verdin CTRL_SLEEP_MOCI# (SO <<
124 gpio = <&gpio5 1 GPIO_ACTIVE_H <<
125 regulator-always-on; <<
126 regulator-boot-on; <<
127 regulator-name = "CTRL_SLEEP_M <<
128 }; <<
129 <<
130 reg_usb_otg1_vbus: regulator-usb-otg1 113 reg_usb_otg1_vbus: regulator-usb-otg1 {
131 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
132 enable-active-high; 115 enable-active-high;
133 /* Verdin USB_1_EN (SODIMM 155 116 /* Verdin USB_1_EN (SODIMM 155) */
134 gpio = <&gpio1 12 GPIO_ACTIVE_ 117 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
135 pinctrl-names = "default"; 118 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_usb1 119 pinctrl-0 = <&pinctrl_reg_usb1_en>;
137 regulator-max-microvolt = <500 120 regulator-max-microvolt = <5000000>;
138 regulator-min-microvolt = <500 121 regulator-min-microvolt = <5000000>;
139 regulator-name = "USB_1_EN"; 122 regulator-name = "USB_1_EN";
140 }; 123 };
141 124
142 reg_usb_otg2_vbus: regulator-usb-otg2 125 reg_usb_otg2_vbus: regulator-usb-otg2 {
143 compatible = "regulator-fixed" 126 compatible = "regulator-fixed";
144 enable-active-high; 127 enable-active-high;
145 /* Verdin USB_2_EN (SODIMM 185 128 /* Verdin USB_2_EN (SODIMM 185) */
146 gpio = <&gpio1 14 GPIO_ACTIVE_ 129 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
147 pinctrl-names = "default"; 130 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb2 131 pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 regulator-max-microvolt = <500 132 regulator-max-microvolt = <5000000>;
150 regulator-min-microvolt = <500 133 regulator-min-microvolt = <5000000>;
151 regulator-name = "USB_2_EN"; 134 regulator-name = "USB_2_EN";
152 }; 135 };
153 136
154 reg_usdhc2_vmmc: regulator-usdhc2 { 137 reg_usdhc2_vmmc: regulator-usdhc2 {
155 compatible = "regulator-fixed" 138 compatible = "regulator-fixed";
156 enable-active-high; 139 enable-active-high;
157 /* Verdin SD_1_PWR_EN (SODIMM 140 /* Verdin SD_1_PWR_EN (SODIMM 76) */
158 gpio = <&gpio3 5 GPIO_ACTIVE_H 141 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
159 off-on-delay-us = <100000>; 142 off-on-delay-us = <100000>;
160 pinctrl-names = "default"; 143 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc2_p 144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
162 regulator-max-microvolt = <330 145 regulator-max-microvolt = <3300000>;
163 regulator-min-microvolt = <330 146 regulator-min-microvolt = <3300000>;
164 regulator-name = "+V3.3_SD"; 147 regulator-name = "+V3.3_SD";
165 startup-delay-us = <2000>; 148 startup-delay-us = <2000>;
166 }; 149 };
167 150
168 reserved-memory { 151 reserved-memory {
169 #address-cells = <2>; 152 #address-cells = <2>;
170 #size-cells = <2>; 153 #size-cells = <2>;
171 ranges; 154 ranges;
172 155
173 /* Use the kernel configuratio 156 /* Use the kernel configuration settings instead */
174 /delete-node/ linux,cma; 157 /delete-node/ linux,cma;
175 }; 158 };
176 }; 159 };
177 160
178 &A53_0 { 161 &A53_0 {
179 cpu-supply = <®_vdd_arm>; 162 cpu-supply = <®_vdd_arm>;
180 }; 163 };
181 164
182 &A53_1 { 165 &A53_1 {
183 cpu-supply = <®_vdd_arm>; 166 cpu-supply = <®_vdd_arm>;
184 }; 167 };
185 168
186 &A53_2 { 169 &A53_2 {
187 cpu-supply = <®_vdd_arm>; 170 cpu-supply = <®_vdd_arm>;
188 }; 171 };
189 172
190 &A53_3 { 173 &A53_3 {
191 cpu-supply = <®_vdd_arm>; 174 cpu-supply = <®_vdd_arm>;
192 }; 175 };
193 176
194 &cpu_alert0 { 177 &cpu_alert0 {
195 temperature = <95000>; 178 temperature = <95000>;
196 }; 179 };
197 180
198 &cpu_crit0 { 181 &cpu_crit0 {
199 temperature = <105000>; 182 temperature = <105000>;
200 }; 183 };
201 184
202 &ddrc { 185 &ddrc {
203 operating-points-v2 = <&ddrc_opp_table 186 operating-points-v2 = <&ddrc_opp_table>;
204 187
205 ddrc_opp_table: opp-table { 188 ddrc_opp_table: opp-table {
206 compatible = "operating-points 189 compatible = "operating-points-v2";
207 190
208 opp-25000000 { 191 opp-25000000 {
209 opp-hz = /bits/ 64 <25 192 opp-hz = /bits/ 64 <25000000>;
210 }; 193 };
211 194
212 opp-100000000 { 195 opp-100000000 {
213 opp-hz = /bits/ 64 <10 196 opp-hz = /bits/ 64 <100000000>;
214 }; 197 };
215 198
216 opp-750000000 { 199 opp-750000000 {
217 opp-hz = /bits/ 64 <75 200 opp-hz = /bits/ 64 <750000000>;
218 }; 201 };
219 }; 202 };
220 }; 203 };
221 204
222 /* Verdin SPI_1 */ 205 /* Verdin SPI_1 */
223 &ecspi2 { 206 &ecspi2 {
224 #address-cells = <1>; 207 #address-cells = <1>;
225 #size-cells = <0>; 208 #size-cells = <0>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 209 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 pinctrl-names = "default"; 210 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ecspi2>; 211 pinctrl-0 = <&pinctrl_ecspi2>;
229 }; 212 };
230 213
231 /* On-module SPI */ !! 214 /* Verdin CAN_1 (On-module) */
232 &ecspi3 { 215 &ecspi3 {
233 #address-cells = <1>; 216 #address-cells = <1>;
234 #size-cells = <0>; 217 #size-cells = <0>;
235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW> !! 218 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
236 pinctrl-names = "default"; 219 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi3>, <&pinct !! 220 pinctrl-0 = <&pinctrl_ecspi3>;
238 status = "okay"; 221 status = "okay";
239 222
240 /* Verdin CAN_1 */ <<
241 can1: can@0 { 223 can1: can@0 {
242 compatible = "microchip,mcp251 224 compatible = "microchip,mcp251xfd";
243 clocks = <&clk40m>; 225 clocks = <&clk40m>;
244 interrupts-extended = <&gpio1 226 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
245 pinctrl-names = "default"; 227 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_can1_int 228 pinctrl-0 = <&pinctrl_can1_int>;
247 reg = <0>; 229 reg = <0>;
248 spi-max-frequency = <8500000>; 230 spi-max-frequency = <8500000>;
249 }; 231 };
250 <<
251 verdin_som_tpm: tpm@1 { <<
252 compatible = "atmel,attpm20p", <<
253 reg = <0x1>; <<
254 spi-max-frequency = <36000000> <<
255 }; <<
256 }; 232 };
257 233
258 /* Verdin ETH_1 (On-module PHY) */ 234 /* Verdin ETH_1 (On-module PHY) */
259 &fec1 { 235 &fec1 {
260 fsl,magic-packet; 236 fsl,magic-packet;
261 phy-handle = <ðphy0>; 237 phy-handle = <ðphy0>;
262 phy-mode = "rgmii-id"; 238 phy-mode = "rgmii-id";
263 phy-supply = <®_ethphy>; 239 phy-supply = <®_ethphy>;
264 pinctrl-names = "default", "sleep"; 240 pinctrl-names = "default", "sleep";
265 pinctrl-0 = <&pinctrl_fec1>; 241 pinctrl-0 = <&pinctrl_fec1>;
266 pinctrl-1 = <&pinctrl_fec1_sleep>; 242 pinctrl-1 = <&pinctrl_fec1_sleep>;
267 243
268 mdio { 244 mdio {
269 #address-cells = <1>; 245 #address-cells = <1>;
270 #size-cells = <0>; 246 #size-cells = <0>;
271 247
272 ethphy0: ethernet-phy@7 { 248 ethphy0: ethernet-phy@7 {
273 compatible = "ethernet 249 compatible = "ethernet-phy-ieee802.3-c22";
274 interrupt-parent = <&g 250 interrupt-parent = <&gpio1>;
275 interrupts = <10 IRQ_T 251 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
276 micrel,led-mode = <0>; 252 micrel,led-mode = <0>;
277 reg = <7>; 253 reg = <7>;
278 }; 254 };
279 }; 255 };
280 }; 256 };
281 257
282 /* Verdin QSPI_1 */ 258 /* Verdin QSPI_1 */
283 &flexspi { 259 &flexspi {
284 pinctrl-names = "default"; 260 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexspi0>; 261 pinctrl-0 = <&pinctrl_flexspi0>;
286 }; 262 };
287 263
288 &gpio1 { 264 &gpio1 {
289 gpio-line-names = "SODIMM_216", 265 gpio-line-names = "SODIMM_216",
290 "SODIMM_19", 266 "SODIMM_19",
291 "", 267 "",
292 "", 268 "",
293 "", 269 "",
294 "", 270 "",
295 "", 271 "",
296 "", 272 "",
297 "SODIMM_220", 273 "SODIMM_220",
298 "SODIMM_222", 274 "SODIMM_222",
299 "", 275 "",
300 "SODIMM_218", 276 "SODIMM_218",
301 "SODIMM_155", 277 "SODIMM_155",
302 "SODIMM_157", 278 "SODIMM_157",
303 "SODIMM_185", 279 "SODIMM_185",
304 "SODIMM_187"; 280 "SODIMM_187";
305 }; 281 };
306 282
307 &gpio2 { 283 &gpio2 {
308 gpio-line-names = "", 284 gpio-line-names = "",
309 "", 285 "",
310 "", 286 "",
311 "", 287 "",
312 "", 288 "",
313 "", 289 "",
314 "", 290 "",
315 "", 291 "",
316 "", 292 "",
317 "", 293 "",
318 "", 294 "",
319 "", 295 "",
320 "SODIMM_84", 296 "SODIMM_84",
321 "SODIMM_78", 297 "SODIMM_78",
322 "SODIMM_74", 298 "SODIMM_74",
323 "SODIMM_80", 299 "SODIMM_80",
324 "SODIMM_82", 300 "SODIMM_82",
325 "SODIMM_70", 301 "SODIMM_70",
326 "SODIMM_72"; 302 "SODIMM_72";
327 }; 303 };
328 304
329 &gpio5 { 305 &gpio5 {
330 gpio-line-names = "SODIMM_131", 306 gpio-line-names = "SODIMM_131",
331 "", 307 "",
332 "SODIMM_91", 308 "SODIMM_91",
333 "SODIMM_16", 309 "SODIMM_16",
334 "SODIMM_15", 310 "SODIMM_15",
335 "SODIMM_208", 311 "SODIMM_208",
336 "SODIMM_137", 312 "SODIMM_137",
337 "SODIMM_139", 313 "SODIMM_139",
338 "SODIMM_141", 314 "SODIMM_141",
339 "SODIMM_143", 315 "SODIMM_143",
340 "SODIMM_196", 316 "SODIMM_196",
341 "SODIMM_200", 317 "SODIMM_200",
342 "SODIMM_198", 318 "SODIMM_198",
343 "SODIMM_202", 319 "SODIMM_202",
344 "", 320 "",
345 "", 321 "",
346 "SODIMM_55", 322 "SODIMM_55",
347 "SODIMM_53", 323 "SODIMM_53",
348 "SODIMM_95", 324 "SODIMM_95",
349 "SODIMM_93", 325 "SODIMM_93",
350 "SODIMM_14", 326 "SODIMM_14",
351 "SODIMM_12", 327 "SODIMM_12",
352 "", 328 "",
353 "", 329 "",
354 "", 330 "",
355 "", 331 "",
356 "SODIMM_210", 332 "SODIMM_210",
357 "SODIMM_212", 333 "SODIMM_212",
358 "SODIMM_151", 334 "SODIMM_151",
359 "SODIMM_153"; 335 "SODIMM_153";
>> 336
>> 337 ctrl-sleep-moci-hog {
>> 338 gpio-hog;
>> 339 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
>> 340 gpios = <1 GPIO_ACTIVE_HIGH>;
>> 341 line-name = "CTRL_SLEEP_MOCI#";
>> 342 output-high;
>> 343 pinctrl-names = "default";
>> 344 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
>> 345 };
360 }; 346 };
361 347
362 /* On-module I2C */ 348 /* On-module I2C */
363 &i2c1 { 349 &i2c1 {
364 clock-frequency = <400000>; 350 clock-frequency = <400000>;
365 pinctrl-names = "default", "gpio"; 351 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c1>; 352 pinctrl-0 = <&pinctrl_i2c1>;
367 pinctrl-1 = <&pinctrl_i2c1_gpio>; 353 pinctrl-1 = <&pinctrl_i2c1_gpio>;
368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 354 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 355 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
370 status = "okay"; 356 status = "okay";
371 357
372 pca9450: pmic@25 { 358 pca9450: pmic@25 {
373 compatible = "nxp,pca9450a"; 359 compatible = "nxp,pca9450a";
374 interrupt-parent = <&gpio1>; 360 interrupt-parent = <&gpio1>;
375 /* PMIC PCA9450 PMIC_nINT GPIO 361 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
376 interrupts = <3 IRQ_TYPE_LEVEL 362 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
377 pinctrl-names = "default"; 363 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pmic>; 364 pinctrl-0 = <&pinctrl_pmic>;
379 reg = <0x25>; 365 reg = <0x25>;
380 366
381 /* 367 /*
382 * The bootloader is expected 368 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
383 * behind this PMIC. 369 * behind this PMIC.
384 */ 370 */
385 371
386 regulators { 372 regulators {
387 reg_vdd_soc: BUCK1 { 373 reg_vdd_soc: BUCK1 {
388 nxp,dvs-run-vo 374 nxp,dvs-run-voltage = <850000>;
389 nxp,dvs-standb 375 nxp,dvs-standby-voltage = <800000>;
390 regulator-alwa 376 regulator-always-on;
391 regulator-boot 377 regulator-boot-on;
392 regulator-max- 378 regulator-max-microvolt = <850000>;
393 regulator-min- 379 regulator-min-microvolt = <800000>;
394 regulator-name 380 regulator-name = "On-module +VDD_SOC (BUCK1)";
395 regulator-ramp 381 regulator-ramp-delay = <3125>;
396 }; 382 };
397 383
398 reg_vdd_arm: BUCK2 { 384 reg_vdd_arm: BUCK2 {
399 nxp,dvs-run-vo 385 nxp,dvs-run-voltage = <950000>;
400 nxp,dvs-standb 386 nxp,dvs-standby-voltage = <850000>;
401 regulator-alwa 387 regulator-always-on;
402 regulator-boot 388 regulator-boot-on;
403 regulator-max- 389 regulator-max-microvolt = <1050000>;
404 regulator-min- 390 regulator-min-microvolt = <805000>;
405 regulator-name 391 regulator-name = "On-module +VDD_ARM (BUCK2)";
406 regulator-ramp 392 regulator-ramp-delay = <3125>;
407 }; 393 };
408 394
409 reg_vdd_dram: BUCK3 { 395 reg_vdd_dram: BUCK3 {
410 regulator-alwa 396 regulator-always-on;
411 regulator-boot 397 regulator-boot-on;
412 regulator-max- 398 regulator-max-microvolt = <1000000>;
413 regulator-min- 399 regulator-min-microvolt = <805000>;
414 regulator-name 400 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
415 }; 401 };
416 402
417 reg_vdd_3v3: BUCK4 { 403 reg_vdd_3v3: BUCK4 {
418 regulator-alwa 404 regulator-always-on;
419 regulator-boot 405 regulator-boot-on;
420 regulator-max- 406 regulator-max-microvolt = <3300000>;
421 regulator-min- 407 regulator-min-microvolt = <3300000>;
422 regulator-name 408 regulator-name = "On-module +V3.3 (BUCK4)";
423 }; 409 };
424 410
425 reg_vdd_1v8: BUCK5 { 411 reg_vdd_1v8: BUCK5 {
426 regulator-alwa 412 regulator-always-on;
427 regulator-boot 413 regulator-boot-on;
428 regulator-max- 414 regulator-max-microvolt = <1800000>;
429 regulator-min- 415 regulator-min-microvolt = <1800000>;
430 regulator-name 416 regulator-name = "PWR_1V8_MOCI (BUCK5)";
431 }; 417 };
432 418
433 reg_nvcc_dram: BUCK6 { 419 reg_nvcc_dram: BUCK6 {
434 regulator-alwa 420 regulator-always-on;
435 regulator-boot 421 regulator-boot-on;
436 regulator-max- 422 regulator-max-microvolt = <1100000>;
437 regulator-min- 423 regulator-min-microvolt = <1100000>;
438 regulator-name 424 regulator-name = "On-module +VDD_DDR (BUCK6)";
439 }; 425 };
440 426
441 reg_nvcc_snvs: LDO1 { 427 reg_nvcc_snvs: LDO1 {
442 regulator-alwa 428 regulator-always-on;
443 regulator-boot 429 regulator-boot-on;
444 regulator-max- 430 regulator-max-microvolt = <1800000>;
445 regulator-min- 431 regulator-min-microvolt = <1800000>;
446 regulator-name 432 regulator-name = "On-module +V1.8_SNVS (LDO1)";
447 }; 433 };
448 434
449 reg_vdd_snvs: LDO2 { 435 reg_vdd_snvs: LDO2 {
450 regulator-alwa 436 regulator-always-on;
451 regulator-boot 437 regulator-boot-on;
452 regulator-max- 438 regulator-max-microvolt = <800000>;
453 regulator-min- 439 regulator-min-microvolt = <800000>;
454 regulator-name 440 regulator-name = "On-module +V0.8_SNVS (LDO2)";
455 }; 441 };
456 442
457 reg_vdda: LDO3 { 443 reg_vdda: LDO3 {
458 regulator-alwa 444 regulator-always-on;
459 regulator-boot 445 regulator-boot-on;
460 regulator-max- 446 regulator-max-microvolt = <1800000>;
461 regulator-min- 447 regulator-min-microvolt = <1800000>;
462 regulator-name 448 regulator-name = "On-module +V1.8A (LDO3)";
463 }; 449 };
464 450
465 reg_vdd_phy: LDO4 { 451 reg_vdd_phy: LDO4 {
466 regulator-alwa 452 regulator-always-on;
467 regulator-boot 453 regulator-boot-on;
468 regulator-max- 454 regulator-max-microvolt = <900000>;
469 regulator-min- 455 regulator-min-microvolt = <900000>;
470 regulator-name 456 regulator-name = "On-module +V0.9_MIPI (LDO4)";
471 }; 457 };
472 458
473 reg_nvcc_sd: LDO5 { 459 reg_nvcc_sd: LDO5 {
474 regulator-max- 460 regulator-max-microvolt = <3300000>;
475 regulator-min- 461 regulator-min-microvolt = <1800000>;
476 regulator-name 462 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
477 }; 463 };
478 }; 464 };
479 }; 465 };
480 466
481 rtc_i2c: rtc@32 { 467 rtc_i2c: rtc@32 {
482 compatible = "epson,rx8130"; 468 compatible = "epson,rx8130";
483 reg = <0x32>; 469 reg = <0x32>;
484 }; 470 };
485 471
486 adc@49 { 472 adc@49 {
487 compatible = "ti,ads1015"; 473 compatible = "ti,ads1015";
488 reg = <0x49>; 474 reg = <0x49>;
489 #address-cells = <1>; 475 #address-cells = <1>;
490 #size-cells = <0>; 476 #size-cells = <0>;
491 477
492 /* Verdin I2C_1 (ADC_4 - ADC_3 478 /* Verdin I2C_1 (ADC_4 - ADC_3) */
493 channel@0 { 479 channel@0 {
494 reg = <0>; 480 reg = <0>;
495 ti,datarate = <4>; 481 ti,datarate = <4>;
496 ti,gain = <2>; 482 ti,gain = <2>;
497 }; 483 };
498 484
499 /* Verdin I2C_1 (ADC_4 - ADC_1 485 /* Verdin I2C_1 (ADC_4 - ADC_1) */
500 channel@1 { 486 channel@1 {
501 reg = <1>; 487 reg = <1>;
502 ti,datarate = <4>; 488 ti,datarate = <4>;
503 ti,gain = <2>; 489 ti,gain = <2>;
504 }; 490 };
505 491
506 /* Verdin I2C_1 (ADC_3 - ADC_1 492 /* Verdin I2C_1 (ADC_3 - ADC_1) */
507 channel@2 { 493 channel@2 {
508 reg = <2>; 494 reg = <2>;
509 ti,datarate = <4>; 495 ti,datarate = <4>;
510 ti,gain = <2>; 496 ti,gain = <2>;
511 }; 497 };
512 498
513 /* Verdin I2C_1 (ADC_2 - ADC_1 499 /* Verdin I2C_1 (ADC_2 - ADC_1) */
514 channel@3 { 500 channel@3 {
515 reg = <3>; 501 reg = <3>;
516 ti,datarate = <4>; 502 ti,datarate = <4>;
517 ti,gain = <2>; 503 ti,gain = <2>;
518 }; 504 };
519 505
520 /* Verdin I2C_1 ADC_4 */ 506 /* Verdin I2C_1 ADC_4 */
521 channel@4 { 507 channel@4 {
522 reg = <4>; 508 reg = <4>;
523 ti,datarate = <4>; 509 ti,datarate = <4>;
524 ti,gain = <2>; 510 ti,gain = <2>;
525 }; 511 };
526 512
527 /* Verdin I2C_1 ADC_3 */ 513 /* Verdin I2C_1 ADC_3 */
528 channel@5 { 514 channel@5 {
529 reg = <5>; 515 reg = <5>;
530 ti,datarate = <4>; 516 ti,datarate = <4>;
531 ti,gain = <2>; 517 ti,gain = <2>;
532 }; 518 };
533 519
534 /* Verdin I2C_1 ADC_2 */ 520 /* Verdin I2C_1 ADC_2 */
535 channel@6 { 521 channel@6 {
536 reg = <6>; 522 reg = <6>;
537 ti,datarate = <4>; 523 ti,datarate = <4>;
538 ti,gain = <2>; 524 ti,gain = <2>;
539 }; 525 };
540 526
541 /* Verdin I2C_1 ADC_1 */ 527 /* Verdin I2C_1 ADC_1 */
542 channel@7 { 528 channel@7 {
543 reg = <7>; 529 reg = <7>;
544 ti,datarate = <4>; 530 ti,datarate = <4>;
545 ti,gain = <2>; 531 ti,gain = <2>;
546 }; 532 };
547 }; 533 };
548 534
549 eeprom@50 { 535 eeprom@50 {
550 compatible = "st,24c02"; 536 compatible = "st,24c02";
551 pagesize = <16>; 537 pagesize = <16>;
552 reg = <0x50>; 538 reg = <0x50>;
553 }; 539 };
554 }; 540 };
555 541
556 /* Verdin I2C_2_DSI */ 542 /* Verdin I2C_2_DSI */
557 &i2c2 { 543 &i2c2 {
558 clock-frequency = <400000>; !! 544 clock-frequency = <10000>;
559 pinctrl-names = "default", "gpio"; 545 pinctrl-names = "default", "gpio";
560 pinctrl-0 = <&pinctrl_i2c2>; 546 pinctrl-0 = <&pinctrl_i2c2>;
561 pinctrl-1 = <&pinctrl_i2c2_gpio>; 547 pinctrl-1 = <&pinctrl_i2c2_gpio>;
562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 548 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 549 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
564 status = "disabled"; 550 status = "disabled";
565 }; 551 };
566 552
567 /* Verdin I2C_3_HDMI N/A */ 553 /* Verdin I2C_3_HDMI N/A */
568 554
569 /* Verdin I2C_4_CSI */ 555 /* Verdin I2C_4_CSI */
570 &i2c3 { 556 &i2c3 {
571 clock-frequency = <400000>; 557 clock-frequency = <400000>;
572 pinctrl-names = "default", "gpio"; 558 pinctrl-names = "default", "gpio";
573 pinctrl-0 = <&pinctrl_i2c3>; 559 pinctrl-0 = <&pinctrl_i2c3>;
574 pinctrl-1 = <&pinctrl_i2c3_gpio>; 560 pinctrl-1 = <&pinctrl_i2c3_gpio>;
575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 561 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 562 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577 }; 563 };
578 564
579 /* Verdin I2C_1 */ 565 /* Verdin I2C_1 */
580 &i2c4 { 566 &i2c4 {
581 clock-frequency = <400000>; 567 clock-frequency = <400000>;
582 pinctrl-names = "default", "gpio"; 568 pinctrl-names = "default", "gpio";
583 pinctrl-0 = <&pinctrl_i2c4>; 569 pinctrl-0 = <&pinctrl_i2c4>;
584 pinctrl-1 = <&pinctrl_i2c4_gpio>; 570 pinctrl-1 = <&pinctrl_i2c4_gpio>;
585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 571 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 572 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
587 573
588 gpio_expander_21: gpio-expander@21 { 574 gpio_expander_21: gpio-expander@21 {
589 compatible = "nxp,pcal6416"; 575 compatible = "nxp,pcal6416";
590 #gpio-cells = <2>; 576 #gpio-cells = <2>;
591 gpio-controller; 577 gpio-controller;
592 reg = <0x21>; 578 reg = <0x21>;
593 vcc-supply = <®_3p3v>; 579 vcc-supply = <®_3p3v>;
594 status = "disabled"; 580 status = "disabled";
595 }; 581 };
596 582
597 lvds_ti_sn65dsi84: bridge@2c { 583 lvds_ti_sn65dsi84: bridge@2c {
598 compatible = "ti,sn65dsi84"; 584 compatible = "ti,sn65dsi84";
599 /* Verdin GPIO_9_DSI (SN65DSI8 585 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
600 /* Verdin GPIO_10_DSI (SODIMM 586 /* Verdin GPIO_10_DSI (SODIMM 21) */
601 enable-gpios = <&gpio3 3 GPIO_ 587 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
602 pinctrl-names = "default"; 588 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_gpio_10_ 589 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
604 reg = <0x2c>; 590 reg = <0x2c>;
605 status = "disabled"; 591 status = "disabled";
606 }; 592 };
607 593
608 /* Current measurement into module VCC 594 /* Current measurement into module VCC */
609 hwmon: hwmon@40 { 595 hwmon: hwmon@40 {
610 compatible = "ti,ina219"; 596 compatible = "ti,ina219";
611 reg = <0x40>; 597 reg = <0x40>;
612 shunt-resistor = <10000>; 598 shunt-resistor = <10000>;
613 status = "disabled"; 599 status = "disabled";
614 }; 600 };
615 601
616 hdmi_lontium_lt8912: hdmi@48 { 602 hdmi_lontium_lt8912: hdmi@48 {
617 compatible = "lontium,lt8912b" 603 compatible = "lontium,lt8912b";
618 pinctrl-names = "default"; 604 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_gpio_10_ 605 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
620 reg = <0x48>; 606 reg = <0x48>;
621 /* Verdin GPIO_9_DSI (LT8912 I 607 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
622 /* Verdin GPIO_10_DSI (SODIMM 608 /* Verdin GPIO_10_DSI (SODIMM 21) */
623 reset-gpios = <&gpio3 3 GPIO_A 609 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
624 status = "disabled"; 610 status = "disabled";
625 }; 611 };
626 612
627 atmel_mxt_ts: touch@4a { 613 atmel_mxt_ts: touch@4a {
628 compatible = "atmel,maxtouch"; 614 compatible = "atmel,maxtouch";
629 /* 615 /*
630 * Verdin GPIO_9_DSI 616 * Verdin GPIO_9_DSI
631 * (TOUCH_INT#, SODIMM 17, als 617 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
632 */ 618 */
633 interrupt-parent = <&gpio3>; 619 interrupt-parent = <&gpio3>;
634 interrupts = <15 IRQ_TYPE_EDGE 620 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
635 pinctrl-names = "default"; 621 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_gpio_9_d 622 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
637 reg = <0x4a>; 623 reg = <0x4a>;
638 /* Verdin I2S_2_BCLK (TOUCH_RE 624 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
639 reset-gpios = <&gpio3 23 GPIO_ 625 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
640 status = "disabled"; 626 status = "disabled";
641 }; 627 };
642 628
643 /* Temperature sensor on carrier board 629 /* Temperature sensor on carrier board */
644 hwmon_temp: sensor@4f { 630 hwmon_temp: sensor@4f {
645 compatible = "ti,tmp75c"; 631 compatible = "ti,tmp75c";
646 reg = <0x4f>; 632 reg = <0x4f>;
647 status = "disabled"; 633 status = "disabled";
648 }; 634 };
649 635
650 /* EEPROM on display adapter (MIPI DSI 636 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
651 eeprom_display_adapter: eeprom@50 { 637 eeprom_display_adapter: eeprom@50 {
652 compatible = "st,24c02"; 638 compatible = "st,24c02";
653 pagesize = <16>; 639 pagesize = <16>;
654 reg = <0x50>; 640 reg = <0x50>;
655 status = "disabled"; 641 status = "disabled";
656 }; 642 };
657 643
658 /* EEPROM on carrier board */ 644 /* EEPROM on carrier board */
659 eeprom_carrier_board: eeprom@57 { 645 eeprom_carrier_board: eeprom@57 {
660 compatible = "st,24c02"; 646 compatible = "st,24c02";
661 pagesize = <16>; 647 pagesize = <16>;
662 reg = <0x57>; 648 reg = <0x57>;
663 status = "disabled"; 649 status = "disabled";
664 }; 650 };
665 }; 651 };
666 652
667 /* Verdin PCIE_1 */ 653 /* Verdin PCIE_1 */
668 &pcie0 { 654 &pcie0 {
669 assigned-clocks = <&clk IMX8MM_CLK_PCI 655 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
670 <&clk IMX8MM_CLK_PCI 656 <&clk IMX8MM_CLK_PCIE1_CTRL>;
671 assigned-clock-parents = <&clk IMX8MM_ 657 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
672 <&clk IMX8MM_ 658 <&clk IMX8MM_SYS_PLL2_250M>;
673 assigned-clock-rates = <10000000>, <25 659 assigned-clock-rates = <10000000>, <250000000>;
674 pinctrl-names = "default"; 660 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pcie0>; 661 pinctrl-0 = <&pinctrl_pcie0>;
676 /* PCIE_1_RESET# (SODIMM 244) */ 662 /* PCIE_1_RESET# (SODIMM 244) */
677 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LO 663 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
678 }; 664 };
679 665
680 &pcie_phy { 666 &pcie_phy {
681 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 667 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
682 clock-names = "ref"; 668 clock-names = "ref";
683 fsl,clkreq-unsupported; 669 fsl,clkreq-unsupported;
684 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
685 fsl,tx-deemph-gen1 = <0x2d>; 671 fsl,tx-deemph-gen1 = <0x2d>;
686 fsl,tx-deemph-gen2 = <0xf>; 672 fsl,tx-deemph-gen2 = <0xf>;
687 }; 673 };
688 674
689 /* Verdin PWM_3_DSI */ 675 /* Verdin PWM_3_DSI */
690 &pwm1 { 676 &pwm1 {
691 pinctrl-names = "default"; 677 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_1>; 678 pinctrl-0 = <&pinctrl_pwm_1>;
693 #pwm-cells = <3>; 679 #pwm-cells = <3>;
694 }; 680 };
695 681
696 /* Verdin PWM_1 */ 682 /* Verdin PWM_1 */
697 &pwm2 { 683 &pwm2 {
698 pinctrl-names = "default"; 684 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_pwm_2>; 685 pinctrl-0 = <&pinctrl_pwm_2>;
700 #pwm-cells = <3>; 686 #pwm-cells = <3>;
701 }; 687 };
702 688
703 /* Verdin PWM_2 */ 689 /* Verdin PWM_2 */
704 &pwm3 { 690 &pwm3 {
705 pinctrl-names = "default"; 691 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_pwm_3>; 692 pinctrl-0 = <&pinctrl_pwm_3>;
707 #pwm-cells = <3>; 693 #pwm-cells = <3>;
708 }; 694 };
709 695
710 /* Verdin I2S_1 */ 696 /* Verdin I2S_1 */
711 &sai2 { 697 &sai2 {
712 #sound-dai-cells = <0>; 698 #sound-dai-cells = <0>;
713 assigned-clock-parents = <&clk IMX8MM_ 699 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
714 assigned-clock-rates = <24576000>; 700 assigned-clock-rates = <24576000>;
715 assigned-clocks = <&clk IMX8MM_CLK_SAI 701 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
716 pinctrl-names = "default"; 702 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_sai2>; 703 pinctrl-0 = <&pinctrl_sai2>;
718 }; 704 };
719 705
720 &snvs_pwrkey { 706 &snvs_pwrkey {
721 status = "okay"; 707 status = "okay";
722 }; 708 };
723 709
724 /* Verdin UART_3, used as the Linux console */ 710 /* Verdin UART_3, used as the Linux console */
725 &uart1 { 711 &uart1 {
726 pinctrl-names = "default"; 712 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_uart1>; 713 pinctrl-0 = <&pinctrl_uart1>;
728 }; 714 };
729 715
730 /* Verdin UART_1 */ 716 /* Verdin UART_1 */
731 &uart2 { 717 &uart2 {
732 pinctrl-names = "default"; 718 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_uart2>; 719 pinctrl-0 = <&pinctrl_uart2>;
734 uart-has-rtscts; 720 uart-has-rtscts;
735 }; 721 };
736 722
737 /* Verdin UART_2 */ 723 /* Verdin UART_2 */
738 &uart3 { 724 &uart3 {
739 pinctrl-names = "default"; 725 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_uart3>; 726 pinctrl-0 = <&pinctrl_uart3>;
741 uart-has-rtscts; 727 uart-has-rtscts;
742 }; 728 };
743 729
744 /* 730 /*
745 * Verdin UART_4 731 * Verdin UART_4
746 * Resource allocated to M4 by default, must n 732 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
747 */ 733 */
748 &uart4 { 734 &uart4 {
749 pinctrl-names = "default"; 735 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_uart4>; 736 pinctrl-0 = <&pinctrl_uart4>;
751 }; 737 };
752 738
753 /* Verdin USB_1 */ 739 /* Verdin USB_1 */
754 &usbotg1 { 740 &usbotg1 {
755 adp-disable; 741 adp-disable;
756 dr_mode = "otg"; 742 dr_mode = "otg";
757 hnp-disable; 743 hnp-disable;
758 samsung,picophy-dc-vol-level-adjust = 744 samsung,picophy-dc-vol-level-adjust = <7>;
759 samsung,picophy-pre-emp-curr-control = 745 samsung,picophy-pre-emp-curr-control = <3>;
760 srp-disable; 746 srp-disable;
761 vbus-supply = <®_usb_otg1_vbus>; 747 vbus-supply = <®_usb_otg1_vbus>;
762 }; 748 };
763 749
764 /* Verdin USB_2 */ 750 /* Verdin USB_2 */
765 &usbotg2 { 751 &usbotg2 {
766 dr_mode = "host"; 752 dr_mode = "host";
767 samsung,picophy-dc-vol-level-adjust = 753 samsung,picophy-dc-vol-level-adjust = <7>;
768 samsung,picophy-pre-emp-curr-control = 754 samsung,picophy-pre-emp-curr-control = <3>;
769 vbus-supply = <®_usb_otg2_vbus>; 755 vbus-supply = <®_usb_otg2_vbus>;
770 }; 756 };
771 757
772 &usbphynop1 { 758 &usbphynop1 {
773 vcc-supply = <®_vdd_3v3>; 759 vcc-supply = <®_vdd_3v3>;
774 }; 760 };
775 761
776 &usbphynop2 { 762 &usbphynop2 {
777 power-domains = <&pgc_otg2>; 763 power-domains = <&pgc_otg2>;
778 vcc-supply = <®_vdd_3v3>; 764 vcc-supply = <®_vdd_3v3>;
779 }; 765 };
780 766
781 /* On-module eMMC */ 767 /* On-module eMMC */
782 &usdhc1 { 768 &usdhc1 {
783 bus-width = <8>; 769 bus-width = <8>;
784 keep-power-in-suspend; 770 keep-power-in-suspend;
785 non-removable; 771 non-removable;
786 pinctrl-names = "default", "state_100m 772 pinctrl-names = "default", "state_100mhz", "state_200mhz";
787 pinctrl-0 = <&pinctrl_usdhc1>; 773 pinctrl-0 = <&pinctrl_usdhc1>;
788 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 774 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
789 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 775 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
790 status = "okay"; 776 status = "okay";
791 }; 777 };
792 778
793 /* Verdin SD_1 */ 779 /* Verdin SD_1 */
794 &usdhc2 { 780 &usdhc2 {
795 bus-width = <4>; 781 bus-width = <4>;
796 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 782 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
797 disable-wp; 783 disable-wp;
798 pinctrl-names = "default", "state_100m 784 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
799 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 785 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
800 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
801 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
802 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 788 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
803 vmmc-supply = <®_usdhc2_vmmc>; 789 vmmc-supply = <®_usdhc2_vmmc>;
804 }; 790 };
805 791
806 &wdog1 { 792 &wdog1 {
807 fsl,ext-reset-output; 793 fsl,ext-reset-output;
808 pinctrl-names = "default"; 794 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_wdog>; 795 pinctrl-0 = <&pinctrl_wdog>;
810 status = "okay"; 796 status = "okay";
811 }; 797 };
812 798
813 &iomuxc { 799 &iomuxc {
814 pinctrl-names = "default"; 800 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_gpio1>, <&pinctr 801 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
816 <&pinctrl_gpio3>, <&pinctr 802 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
817 <&pinctrl_gpio7>, <&pinctr 803 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
818 <&pinctrl_gpio_hog1>, <&pi !! 804 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
>> 805 <&pinctrl_pmic_tpm_ena>;
819 806
820 pinctrl_can1_int: can1intgrp { 807 pinctrl_can1_int: can1intgrp {
821 fsl,pins = 808 fsl,pins =
822 <MX8MM_IOMUXC_GPIO1_IO 809 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
823 }; 810 };
824 811
825 pinctrl_can2_int: can2intgrp { 812 pinctrl_can2_int: can2intgrp {
826 fsl,pins = 813 fsl,pins =
827 <MX8MM_IOMUXC_GPIO1_IO 814 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
828 }; 815 };
829 816
830 pinctrl_ctrl_sleep_moci: ctrlsleepmoci 817 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
831 fsl,pins = 818 fsl,pins =
832 <MX8MM_IOMUXC_SAI3_TXD 819 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
833 }; 820 };
834 821
835 pinctrl_ecspi2: ecspi2grp { 822 pinctrl_ecspi2: ecspi2grp {
836 fsl,pins = 823 fsl,pins =
837 <MX8MM_IOMUXC_ECSPI2_M 824 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
838 <MX8MM_IOMUXC_ECSPI2_M 825 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
839 <MX8MM_IOMUXC_ECSPI2_S 826 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
840 <MX8MM_IOMUXC_ECSPI2_S 827 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
841 }; 828 };
842 829
843 pinctrl_ecspi3: ecspi3grp { 830 pinctrl_ecspi3: ecspi3grp {
844 fsl,pins = 831 fsl,pins =
845 <MX8MM_IOMUXC_GPIO1_IO 832 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
846 <MX8MM_IOMUXC_UART1_RX 833 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
847 <MX8MM_IOMUXC_UART1_TX 834 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
848 <MX8MM_IOMUXC_UART2_RX 835 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
849 <MX8MM_IOMUXC_UART2_TX 836 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
850 }; 837 };
851 838
852 pinctrl_fec1: fec1grp { 839 pinctrl_fec1: fec1grp {
853 fsl,pins = 840 fsl,pins =
854 <MX8MM_IOMUXC_ENET_MDC 841 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
855 <MX8MM_IOMUXC_ENET_MDI 842 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
856 <MX8MM_IOMUXC_ENET_RD0 843 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
857 <MX8MM_IOMUXC_ENET_RD1 844 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
858 <MX8MM_IOMUXC_ENET_RD2 845 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
859 <MX8MM_IOMUXC_ENET_RD3 846 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
860 <MX8MM_IOMUXC_ENET_RXC 847 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
861 <MX8MM_IOMUXC_ENET_RX_ 848 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
862 <MX8MM_IOMUXC_ENET_TD0 849 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
863 <MX8MM_IOMUXC_ENET_TD1 850 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
864 <MX8MM_IOMUXC_ENET_TD2 851 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
865 <MX8MM_IOMUXC_ENET_TD3 852 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
866 <MX8MM_IOMUXC_ENET_TXC 853 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
867 <MX8MM_IOMUXC_ENET_TX_ 854 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
868 <MX8MM_IOMUXC_GPIO1_IO 855 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
869 }; 856 };
870 857
871 pinctrl_fec1_sleep: fec1-sleepgrp { 858 pinctrl_fec1_sleep: fec1-sleepgrp {
872 fsl,pins = 859 fsl,pins =
873 <MX8MM_IOMUXC_ENET_MDC 860 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
874 <MX8MM_IOMUXC_ENET_MDI 861 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
875 <MX8MM_IOMUXC_ENET_RD0 862 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
876 <MX8MM_IOMUXC_ENET_RD1 863 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
877 <MX8MM_IOMUXC_ENET_RD2 864 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
878 <MX8MM_IOMUXC_ENET_RD3 865 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
879 <MX8MM_IOMUXC_ENET_RXC 866 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
880 <MX8MM_IOMUXC_ENET_RX_ 867 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
881 <MX8MM_IOMUXC_ENET_TD0 868 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
882 <MX8MM_IOMUXC_ENET_TD1 869 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
883 <MX8MM_IOMUXC_ENET_TD2 870 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
884 <MX8MM_IOMUXC_ENET_TD3 871 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
885 <MX8MM_IOMUXC_ENET_TXC 872 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
886 <MX8MM_IOMUXC_ENET_TX_ 873 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
887 <MX8MM_IOMUXC_GPIO1_IO 874 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
888 }; 875 };
889 876
890 pinctrl_flexspi0: flexspi0grp { 877 pinctrl_flexspi0: flexspi0grp {
891 fsl,pins = 878 fsl,pins =
892 <MX8MM_IOMUXC_NAND_ALE 879 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
893 <MX8MM_IOMUXC_NAND_CE0 880 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
894 <MX8MM_IOMUXC_NAND_CE1 881 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
895 <MX8MM_IOMUXC_NAND_DAT 882 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
896 <MX8MM_IOMUXC_NAND_DAT 883 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
897 <MX8MM_IOMUXC_NAND_DAT 884 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
898 <MX8MM_IOMUXC_NAND_DAT 885 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
899 <MX8MM_IOMUXC_NAND_DQS 886 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
900 }; 887 };
901 888
902 pinctrl_gpio1: gpio1grp { 889 pinctrl_gpio1: gpio1grp {
903 fsl,pins = 890 fsl,pins =
904 <MX8MM_IOMUXC_NAND_CE3 891 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
905 }; 892 };
906 893
907 pinctrl_gpio2: gpio2grp { 894 pinctrl_gpio2: gpio2grp {
908 fsl,pins = 895 fsl,pins =
909 <MX8MM_IOMUXC_SPDIF_EX 896 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
910 }; 897 };
911 898
912 pinctrl_gpio3: gpio3grp { 899 pinctrl_gpio3: gpio3grp {
913 fsl,pins = 900 fsl,pins =
914 <MX8MM_IOMUXC_UART3_RX 901 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
915 }; 902 };
916 903
917 pinctrl_gpio4: gpio4grp { 904 pinctrl_gpio4: gpio4grp {
918 fsl,pins = 905 fsl,pins =
919 <MX8MM_IOMUXC_UART3_TX 906 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
920 }; 907 };
921 908
922 pinctrl_gpio5: gpio5grp { 909 pinctrl_gpio5: gpio5grp {
923 fsl,pins = 910 fsl,pins =
924 <MX8MM_IOMUXC_GPIO1_IO 911 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
925 }; 912 };
926 913
927 pinctrl_gpio6: gpio6grp { 914 pinctrl_gpio6: gpio6grp {
928 fsl,pins = 915 fsl,pins =
929 <MX8MM_IOMUXC_GPIO1_IO 916 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
930 }; 917 };
931 918
932 pinctrl_gpio7: gpio7grp { 919 pinctrl_gpio7: gpio7grp {
933 fsl,pins = 920 fsl,pins =
934 <MX8MM_IOMUXC_GPIO1_IO 921 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
935 }; 922 };
936 923
937 pinctrl_gpio8: gpio8grp { 924 pinctrl_gpio8: gpio8grp {
938 fsl,pins = 925 fsl,pins =
939 <MX8MM_IOMUXC_GPIO1_IO 926 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
940 }; 927 };
941 928
942 /* Verdin GPIO_9_DSI (pulled-up as act 929 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
943 pinctrl_gpio_9_dsi: gpio9dsigrp { 930 pinctrl_gpio_9_dsi: gpio9dsigrp {
944 fsl,pins = 931 fsl,pins =
945 <MX8MM_IOMUXC_NAND_RE_ !! 932 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
946 }; 933 };
947 934
948 /* Verdin GPIO_10_DSI (pulled-up as ac 935 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
949 pinctrl_gpio_10_dsi: gpio10dsigrp { 936 pinctrl_gpio_10_dsi: gpio10dsigrp {
950 fsl,pins = 937 fsl,pins =
951 <MX8MM_IOMUXC_NAND_CE2 938 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
952 }; 939 };
953 940
954 pinctrl_gpio_hog1: gpiohog1grp { 941 pinctrl_gpio_hog1: gpiohog1grp {
955 fsl,pins = 942 fsl,pins =
956 <MX8MM_IOMUXC_SAI1_MCL 943 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
957 <MX8MM_IOMUXC_SAI1_RXC 944 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
958 <MX8MM_IOMUXC_SAI1_RXD 945 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
959 <MX8MM_IOMUXC_SAI1_RXD 946 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
960 <MX8MM_IOMUXC_SAI1_RXD 947 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
961 <MX8MM_IOMUXC_SAI1_RXD 948 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
962 <MX8MM_IOMUXC_SAI1_RXF 949 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
963 <MX8MM_IOMUXC_SAI1_TXC 950 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
964 <MX8MM_IOMUXC_SAI1_TXD 951 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
965 <MX8MM_IOMUXC_SAI1_TXD 952 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
966 <MX8MM_IOMUXC_SAI1_TXD 953 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
967 <MX8MM_IOMUXC_SAI1_TXD 954 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
968 <MX8MM_IOMUXC_SAI1_TXD 955 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
969 <MX8MM_IOMUXC_SAI1_TXD 956 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
970 <MX8MM_IOMUXC_SAI1_TXF 957 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
971 }; 958 };
972 959
973 pinctrl_gpio_hog2: gpiohog2grp { 960 pinctrl_gpio_hog2: gpiohog2grp {
974 fsl,pins = 961 fsl,pins =
975 <MX8MM_IOMUXC_SAI3_MCL 962 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
976 }; 963 };
977 964
978 pinctrl_gpio_hog3: gpiohog3grp { 965 pinctrl_gpio_hog3: gpiohog3grp {
979 fsl,pins = 966 fsl,pins =
980 <MX8MM_IOMUXC_GPIO1_IO 967 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
981 <MX8MM_IOMUXC_GPIO1_IO 968 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
982 }; 969 };
983 970
984 pinctrl_gpio_keys: gpiokeysgrp { 971 pinctrl_gpio_keys: gpiokeysgrp {
985 fsl,pins = 972 fsl,pins =
986 <MX8MM_IOMUXC_SAI3_RXF 973 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
987 }; 974 };
988 975
989 /* On-module I2C */ 976 /* On-module I2C */
990 pinctrl_i2c1: i2c1grp { 977 pinctrl_i2c1: i2c1grp {
991 fsl,pins = 978 fsl,pins =
992 <MX8MM_IOMUXC_I2C1_SCL 979 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
993 <MX8MM_IOMUXC_I2C1_SDA 980 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
994 }; 981 };
995 982
996 pinctrl_i2c1_gpio: i2c1gpiogrp { 983 pinctrl_i2c1_gpio: i2c1gpiogrp {
997 fsl,pins = 984 fsl,pins =
998 <MX8MM_IOMUXC_I2C1_SCL 985 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
999 <MX8MM_IOMUXC_I2C1_SDA 986 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
1000 }; 987 };
1001 988
1002 /* Verdin I2C_4_CSI */ 989 /* Verdin I2C_4_CSI */
1003 pinctrl_i2c2: i2c2grp { 990 pinctrl_i2c2: i2c2grp {
1004 fsl,pins = 991 fsl,pins =
1005 <MX8MM_IOMUXC_I2C2_SC 992 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
1006 <MX8MM_IOMUXC_I2C2_SD 993 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
1007 }; 994 };
1008 995
1009 pinctrl_i2c2_gpio: i2c2gpiogrp { 996 pinctrl_i2c2_gpio: i2c2gpiogrp {
1010 fsl,pins = 997 fsl,pins =
1011 <MX8MM_IOMUXC_I2C2_SC 998 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
1012 <MX8MM_IOMUXC_I2C2_SD 999 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1013 }; 1000 };
1014 1001
1015 /* Verdin I2C_2_DSI */ 1002 /* Verdin I2C_2_DSI */
1016 pinctrl_i2c3: i2c3grp { 1003 pinctrl_i2c3: i2c3grp {
1017 fsl,pins = 1004 fsl,pins =
1018 <MX8MM_IOMUXC_I2C3_SC 1005 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1019 <MX8MM_IOMUXC_I2C3_SD 1006 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1020 }; 1007 };
1021 1008
1022 pinctrl_i2c3_gpio: i2c3gpiogrp { 1009 pinctrl_i2c3_gpio: i2c3gpiogrp {
1023 fsl,pins = 1010 fsl,pins =
1024 <MX8MM_IOMUXC_I2C3_SC 1011 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1025 <MX8MM_IOMUXC_I2C3_SD 1012 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1026 }; 1013 };
1027 1014
1028 /* Verdin I2C_1 */ 1015 /* Verdin I2C_1 */
1029 pinctrl_i2c4: i2c4grp { 1016 pinctrl_i2c4: i2c4grp {
1030 fsl,pins = 1017 fsl,pins =
1031 <MX8MM_IOMUXC_I2C4_SC 1018 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1032 <MX8MM_IOMUXC_I2C4_SD 1019 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1033 }; 1020 };
1034 1021
1035 pinctrl_i2c4_gpio: i2c4gpiogrp { 1022 pinctrl_i2c4_gpio: i2c4gpiogrp {
1036 fsl,pins = 1023 fsl,pins =
1037 <MX8MM_IOMUXC_I2C4_SC 1024 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1038 <MX8MM_IOMUXC_I2C4_SD 1025 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1039 }; 1026 };
1040 1027
1041 /* Verdin I2S_2_BCLK (TOUCH_RESET#) * 1028 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1042 pinctrl_i2s_2_bclk_touch_reset: i2s2b 1029 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1043 fsl,pins = 1030 fsl,pins =
1044 <MX8MM_IOMUXC_SAI5_RX 1031 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1045 }; 1032 };
1046 1033
1047 /* Verdin I2S_2_D_OUT shared with SAI 1034 /* Verdin I2S_2_D_OUT shared with SAI5 */
1048 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s 1035 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1049 fsl,pins = 1036 fsl,pins =
1050 <MX8MM_IOMUXC_SAI5_RX 1037 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1051 }; 1038 };
1052 1039
1053 pinctrl_pcie0: pcie0grp { 1040 pinctrl_pcie0: pcie0grp {
1054 fsl,pins = 1041 fsl,pins =
1055 <MX8MM_IOMUXC_SAI5_RX 1042 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1056 /* PMIC_EN_PCIe_CLK, 1043 /* PMIC_EN_PCIe_CLK, unused */
1057 <MX8MM_IOMUXC_SD2_RES 1044 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1058 }; 1045 };
1059 1046
1060 pinctrl_pmic: pmicirqgrp { 1047 pinctrl_pmic: pmicirqgrp {
1061 fsl,pins = 1048 fsl,pins =
1062 <MX8MM_IOMUXC_GPIO1_I 1049 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1063 }; 1050 };
1064 1051
1065 /* Verdin PWM_3_DSI shared with GPIO1 1052 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1066 pinctrl_pwm_1: pwm1grp { 1053 pinctrl_pwm_1: pwm1grp {
1067 fsl,pins = 1054 fsl,pins =
1068 <MX8MM_IOMUXC_GPIO1_I 1055 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1069 }; 1056 };
1070 1057
1071 pinctrl_pwm_2: pwm2grp { 1058 pinctrl_pwm_2: pwm2grp {
1072 fsl,pins = 1059 fsl,pins =
1073 <MX8MM_IOMUXC_SPDIF_R 1060 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1074 }; 1061 };
1075 1062
1076 pinctrl_pwm_3: pwm3grp { 1063 pinctrl_pwm_3: pwm3grp {
1077 fsl,pins = 1064 fsl,pins =
1078 <MX8MM_IOMUXC_SPDIF_T 1065 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1079 }; 1066 };
1080 1067
1081 /* Verdin PWM_3_DSI (pulled-down as a 1068 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1082 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihp 1069 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1083 fsl,pins = 1070 fsl,pins =
1084 <MX8MM_IOMUXC_GPIO1_I 1071 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1085 }; 1072 };
1086 1073
1087 pinctrl_reg_eth: regethgrp { 1074 pinctrl_reg_eth: regethgrp {
1088 fsl,pins = 1075 fsl,pins =
1089 <MX8MM_IOMUXC_SD2_WP_ 1076 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1090 }; 1077 };
1091 1078
1092 pinctrl_reg_usb1_en: regusb1engrp { 1079 pinctrl_reg_usb1_en: regusb1engrp {
1093 fsl,pins = 1080 fsl,pins =
1094 <MX8MM_IOMUXC_GPIO1_I 1081 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1095 }; 1082 };
1096 1083
1097 pinctrl_reg_usb2_en: regusb2engrp { 1084 pinctrl_reg_usb2_en: regusb2engrp {
1098 fsl,pins = 1085 fsl,pins =
1099 <MX8MM_IOMUXC_GPIO1_I 1086 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1100 }; 1087 };
1101 1088
1102 pinctrl_sai2: sai2grp { 1089 pinctrl_sai2: sai2grp {
1103 fsl,pins = 1090 fsl,pins =
1104 <MX8MM_IOMUXC_SAI2_MC 1091 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1105 <MX8MM_IOMUXC_SAI2_TX 1092 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1106 <MX8MM_IOMUXC_SAI2_TX 1093 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1107 <MX8MM_IOMUXC_SAI2_RX 1094 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1108 <MX8MM_IOMUXC_SAI2_TX 1095 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1109 }; 1096 };
1110 1097
1111 pinctrl_sai5: sai5grp { 1098 pinctrl_sai5: sai5grp {
1112 fsl,pins = 1099 fsl,pins =
1113 <MX8MM_IOMUXC_SAI5_RX 1100 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1114 <MX8MM_IOMUXC_SAI5_RX 1101 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1115 <MX8MM_IOMUXC_SAI5_RX 1102 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1116 <MX8MM_IOMUXC_SAI5_RX 1103 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1117 }; 1104 };
1118 1105
1119 /* control signal for optional ATTPM2 1106 /* control signal for optional ATTPM20P or SE050 */
1120 pinctrl_tpm_spi_cs: tpmspicsgrp { !! 1107 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1121 fsl,pins = 1108 fsl,pins =
1122 <MX8MM_IOMUXC_SAI1_TX 1109 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1123 }; 1110 };
1124 1111
1125 pinctrl_tsp: tspgrp { 1112 pinctrl_tsp: tspgrp {
1126 fsl,pins = 1113 fsl,pins =
1127 <MX8MM_IOMUXC_SAI1_RX 1114 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1128 <MX8MM_IOMUXC_SAI1_RX 1115 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1129 <MX8MM_IOMUXC_SAI1_RX 1116 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1130 <MX8MM_IOMUXC_SAI1_RX 1117 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1131 <MX8MM_IOMUXC_SAI1_TX 1118 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1132 }; 1119 };
1133 1120
1134 pinctrl_uart1: uart1grp { 1121 pinctrl_uart1: uart1grp {
1135 fsl,pins = 1122 fsl,pins =
1136 <MX8MM_IOMUXC_SAI2_RX 1123 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1137 <MX8MM_IOMUXC_SAI2_RX 1124 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1138 }; 1125 };
1139 1126
1140 pinctrl_uart2: uart2grp { 1127 pinctrl_uart2: uart2grp {
1141 fsl,pins = 1128 fsl,pins =
1142 <MX8MM_IOMUXC_SAI3_RX 1129 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1143 <MX8MM_IOMUXC_SAI3_RX 1130 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1144 <MX8MM_IOMUXC_SAI3_TX 1131 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1145 <MX8MM_IOMUXC_SAI3_TX 1132 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1146 }; 1133 };
1147 1134
1148 pinctrl_uart3: uart3grp { 1135 pinctrl_uart3: uart3grp {
1149 fsl,pins = 1136 fsl,pins =
1150 <MX8MM_IOMUXC_ECSPI1_ 1137 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1151 <MX8MM_IOMUXC_ECSPI1_ 1138 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1152 <MX8MM_IOMUXC_ECSPI1_ 1139 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1153 <MX8MM_IOMUXC_ECSPI1_ 1140 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1154 }; 1141 };
1155 1142
1156 pinctrl_uart4: uart4grp { 1143 pinctrl_uart4: uart4grp {
1157 fsl,pins = 1144 fsl,pins =
1158 <MX8MM_IOMUXC_UART4_R 1145 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1159 <MX8MM_IOMUXC_UART4_T 1146 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1160 }; 1147 };
1161 1148
1162 pinctrl_usdhc1: usdhc1grp { 1149 pinctrl_usdhc1: usdhc1grp {
1163 fsl,pins = 1150 fsl,pins =
1164 <MX8MM_IOMUXC_SD1_CLK 1151 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1165 <MX8MM_IOMUXC_SD1_CMD 1152 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1166 <MX8MM_IOMUXC_SD1_DAT 1153 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1167 <MX8MM_IOMUXC_SD1_DAT 1154 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1168 <MX8MM_IOMUXC_SD1_DAT 1155 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1169 <MX8MM_IOMUXC_SD1_DAT 1156 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1170 <MX8MM_IOMUXC_SD1_DAT 1157 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1171 <MX8MM_IOMUXC_SD1_DAT 1158 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1172 <MX8MM_IOMUXC_SD1_DAT 1159 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1173 <MX8MM_IOMUXC_SD1_DAT 1160 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1174 <MX8MM_IOMUXC_SD1_RES 1161 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1175 <MX8MM_IOMUXC_SD1_STR 1162 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1176 }; 1163 };
1177 1164
1178 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1165 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1179 fsl,pins = 1166 fsl,pins =
1180 <MX8MM_IOMUXC_SD1_CLK 1167 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1181 <MX8MM_IOMUXC_SD1_CMD 1168 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1182 <MX8MM_IOMUXC_SD1_DAT 1169 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1183 <MX8MM_IOMUXC_SD1_DAT 1170 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1184 <MX8MM_IOMUXC_SD1_DAT 1171 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1185 <MX8MM_IOMUXC_SD1_DAT 1172 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1186 <MX8MM_IOMUXC_SD1_DAT 1173 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1187 <MX8MM_IOMUXC_SD1_DAT 1174 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1188 <MX8MM_IOMUXC_SD1_DAT 1175 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1189 <MX8MM_IOMUXC_SD1_DAT 1176 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1190 <MX8MM_IOMUXC_SD1_RES 1177 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1191 <MX8MM_IOMUXC_SD1_STR 1178 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1192 }; 1179 };
1193 1180
1194 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1181 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1195 fsl,pins = 1182 fsl,pins =
1196 <MX8MM_IOMUXC_SD1_CLK 1183 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1197 <MX8MM_IOMUXC_SD1_CMD 1184 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1198 <MX8MM_IOMUXC_SD1_DAT 1185 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1199 <MX8MM_IOMUXC_SD1_DAT 1186 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1200 <MX8MM_IOMUXC_SD1_DAT 1187 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1201 <MX8MM_IOMUXC_SD1_DAT 1188 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1202 <MX8MM_IOMUXC_SD1_DAT 1189 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1203 <MX8MM_IOMUXC_SD1_DAT 1190 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1204 <MX8MM_IOMUXC_SD1_DAT 1191 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1205 <MX8MM_IOMUXC_SD1_DAT 1192 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1206 <MX8MM_IOMUXC_SD1_RES 1193 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1207 <MX8MM_IOMUXC_SD1_STR 1194 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1208 }; 1195 };
1209 1196
1210 pinctrl_usdhc2_cd: usdhc2cdgrp { 1197 pinctrl_usdhc2_cd: usdhc2cdgrp {
1211 fsl,pins = 1198 fsl,pins =
1212 <MX8MM_IOMUXC_SD2_CD_ 1199 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1213 }; 1200 };
1214 1201
1215 pinctrl_usdhc2_cd_sleep: usdhc2cdslpg 1202 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1216 fsl,pins = 1203 fsl,pins =
1217 <MX8MM_IOMUXC_SD2_CD_ 1204 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1218 }; 1205 };
1219 1206
1220 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp 1207 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1221 fsl,pins = 1208 fsl,pins =
1222 <MX8MM_IOMUXC_NAND_CL 1209 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1223 }; 1210 };
1224 1211
1225 /* 1212 /*
1226 * Note: Due to ERR050080 we use disc 1213 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1227 * on-module +V3.3_1.8_SD (LDO5) rail 1214 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1228 */ 1215 */
1229 pinctrl_usdhc2: usdhc2grp { 1216 pinctrl_usdhc2: usdhc2grp {
1230 fsl,pins = 1217 fsl,pins =
1231 <MX8MM_IOMUXC_GPIO1_I 1218 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1232 <MX8MM_IOMUXC_SD2_CLK 1219 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1233 <MX8MM_IOMUXC_SD2_CMD 1220 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1234 <MX8MM_IOMUXC_SD2_DAT 1221 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1235 <MX8MM_IOMUXC_SD2_DAT 1222 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1236 <MX8MM_IOMUXC_SD2_DAT 1223 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1237 <MX8MM_IOMUXC_SD2_DAT 1224 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1238 }; 1225 };
1239 1226
1240 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1227 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1241 fsl,pins = 1228 fsl,pins =
1242 <MX8MM_IOMUXC_GPIO1_I 1229 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1243 <MX8MM_IOMUXC_SD2_CLK 1230 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1244 <MX8MM_IOMUXC_SD2_CMD 1231 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1245 <MX8MM_IOMUXC_SD2_DAT 1232 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1246 <MX8MM_IOMUXC_SD2_DAT 1233 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1247 <MX8MM_IOMUXC_SD2_DAT 1234 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1248 <MX8MM_IOMUXC_SD2_DAT 1235 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1249 }; 1236 };
1250 1237
1251 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1238 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1252 fsl,pins = 1239 fsl,pins =
1253 <MX8MM_IOMUXC_GPIO1_I 1240 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1254 <MX8MM_IOMUXC_SD2_CLK 1241 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1255 <MX8MM_IOMUXC_SD2_CMD 1242 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1256 <MX8MM_IOMUXC_SD2_DAT 1243 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1257 <MX8MM_IOMUXC_SD2_DAT 1244 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1258 <MX8MM_IOMUXC_SD2_DAT 1245 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1259 <MX8MM_IOMUXC_SD2_DAT 1246 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1260 }; 1247 };
1261 1248
1262 /* Avoid backfeeding with removed car 1249 /* Avoid backfeeding with removed card power */
1263 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1250 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1264 fsl,pins = 1251 fsl,pins =
1265 <MX8MM_IOMUXC_GPIO1_I 1252 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1266 <MX8MM_IOMUXC_SD2_CLK 1253 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1267 <MX8MM_IOMUXC_SD2_CMD 1254 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1268 <MX8MM_IOMUXC_SD2_DAT 1255 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1269 <MX8MM_IOMUXC_SD2_DAT 1256 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1270 <MX8MM_IOMUXC_SD2_DAT 1257 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1271 <MX8MM_IOMUXC_SD2_DAT 1258 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1272 }; 1259 };
1273 1260
1274 /* 1261 /*
1275 * On-module Wi-Fi/BT or type specifi 1262 * On-module Wi-Fi/BT or type specific SDHC interface
1276 * (e.g. on X52 extension slot of Ver 1263 * (e.g. on X52 extension slot of Verdin Development Board)
1277 */ 1264 */
1278 pinctrl_usdhc3: usdhc3grp { 1265 pinctrl_usdhc3: usdhc3grp {
1279 fsl,pins = 1266 fsl,pins =
1280 <MX8MM_IOMUXC_NAND_DA 1267 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1281 <MX8MM_IOMUXC_NAND_DA 1268 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1282 <MX8MM_IOMUXC_NAND_DA 1269 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1283 <MX8MM_IOMUXC_NAND_DA 1270 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1284 <MX8MM_IOMUXC_NAND_WE 1271 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1285 <MX8MM_IOMUXC_NAND_WP 1272 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1286 }; 1273 };
1287 1274
1288 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1275 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1289 fsl,pins = 1276 fsl,pins =
1290 <MX8MM_IOMUXC_NAND_DA 1277 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1291 <MX8MM_IOMUXC_NAND_DA 1278 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1292 <MX8MM_IOMUXC_NAND_DA 1279 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1293 <MX8MM_IOMUXC_NAND_DA 1280 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1294 <MX8MM_IOMUXC_NAND_WE 1281 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1295 <MX8MM_IOMUXC_NAND_WP 1282 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1296 }; 1283 };
1297 1284
1298 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1285 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1299 fsl,pins = 1286 fsl,pins =
1300 <MX8MM_IOMUXC_NAND_DA 1287 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1301 <MX8MM_IOMUXC_NAND_DA 1288 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1302 <MX8MM_IOMUXC_NAND_DA 1289 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1303 <MX8MM_IOMUXC_NAND_DA 1290 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1304 <MX8MM_IOMUXC_NAND_WE 1291 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1305 <MX8MM_IOMUXC_NAND_WP 1292 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1306 }; 1293 };
1307 1294
1308 pinctrl_wdog: wdoggrp { 1295 pinctrl_wdog: wdoggrp {
1309 fsl,pins = 1296 fsl,pins =
1310 <MX8MM_IOMUXC_GPIO1_I 1297 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1311 }; 1298 };
1312 1299
1313 pinctrl_wifi_ctrl: wifictrlgrp { 1300 pinctrl_wifi_ctrl: wifictrlgrp {
1314 fsl,pins = 1301 fsl,pins =
1315 <MX8MM_IOMUXC_NAND_RE 1302 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1316 <MX8MM_IOMUXC_SAI1_RX 1303 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1317 <MX8MM_IOMUXC_SAI5_RX 1304 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1318 }; 1305 };
1319 1306
1320 pinctrl_wifi_i2s: bti2sgrp { 1307 pinctrl_wifi_i2s: bti2sgrp {
1321 fsl,pins = 1308 fsl,pins =
1322 <MX8MM_IOMUXC_SAI1_RX 1309 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1323 <MX8MM_IOMUXC_SAI1_RX 1310 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1324 <MX8MM_IOMUXC_SAI1_RX 1311 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1325 <MX8MM_IOMUXC_SAI1_TX 1312 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1326 }; 1313 };
1327 1314
1328 pinctrl_wifi_pwr_en: wifipwrengrp { 1315 pinctrl_wifi_pwr_en: wifipwrengrp {
1329 fsl,pins = 1316 fsl,pins =
1330 <MX8MM_IOMUXC_SAI5_MC 1317 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1331 }; 1318 };
1332 }; 1319 };
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