1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 #include "imx8mm-pinfunc.h"
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &fec1;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 idle-states {
49 entry-method = "psci";
50
51 cpu_pd_wait: cpu-pd-wa
52 compatible = "
53 arm,psci-suspe
54 local-timer-st
55 entry-latency-
56 exit-latency-u
57 min-residency-
58 };
59 };
60
61 A53_0: cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cort
64 reg = <0x0>;
65 clock-latency = <61036
66 clocks = <&clk IMX8MM_
67 enable-method = "psci"
68 i-cache-size = <0x8000
69 i-cache-line-size = <6
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000
72 d-cache-line-size = <6
73 d-cache-sets = <128>;
74 next-level-cache = <&A
75 operating-points-v2 =
76 nvmem-cells = <&cpu_sp
77 nvmem-cell-names = "sp
78 cpu-idle-states = <&cp
79 #cooling-cells = <2>;
80 };
81
82 A53_1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cort
85 reg = <0x1>;
86 clock-latency = <61036
87 clocks = <&clk IMX8MM_
88 enable-method = "psci"
89 i-cache-size = <0x8000
90 i-cache-line-size = <6
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000
93 d-cache-line-size = <6
94 d-cache-sets = <128>;
95 next-level-cache = <&A
96 operating-points-v2 =
97 cpu-idle-states = <&cp
98 #cooling-cells = <2>;
99 };
100
101 A53_2: cpu@2 {
102 device_type = "cpu";
103 compatible = "arm,cort
104 reg = <0x2>;
105 clock-latency = <61036
106 clocks = <&clk IMX8MM_
107 enable-method = "psci"
108 i-cache-size = <0x8000
109 i-cache-line-size = <6
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000
112 d-cache-line-size = <6
113 d-cache-sets = <128>;
114 next-level-cache = <&A
115 operating-points-v2 =
116 cpu-idle-states = <&cp
117 #cooling-cells = <2>;
118 };
119
120 A53_3: cpu@3 {
121 device_type = "cpu";
122 compatible = "arm,cort
123 reg = <0x3>;
124 clock-latency = <61036
125 clocks = <&clk IMX8MM_
126 enable-method = "psci"
127 i-cache-size = <0x8000
128 i-cache-line-size = <6
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000
131 d-cache-line-size = <6
132 d-cache-sets = <128>;
133 next-level-cache = <&A
134 operating-points-v2 =
135 cpu-idle-states = <&cp
136 #cooling-cells = <2>;
137 };
138
139 A53_L2: l2-cache0 {
140 compatible = "cache";
141 cache-level = <2>;
142 cache-unified;
143 cache-size = <0x80000>
144 cache-line-size = <64>
145 cache-sets = <512>;
146 };
147 };
148
149 a53_opp_table: opp-table {
150 compatible = "operating-points
151 opp-shared;
152
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <12
155 opp-microvolt = <85000
156 opp-supported-hw = <0x
157 clock-latency-ns = <15
158 opp-suspend;
159 };
160
161 opp-1600000000 {
162 opp-hz = /bits/ 64 <16
163 opp-microvolt = <95000
164 opp-supported-hw = <0x
165 clock-latency-ns = <15
166 opp-suspend;
167 };
168
169 opp-1800000000 {
170 opp-hz = /bits/ 64 <18
171 opp-microvolt = <10000
172 opp-supported-hw = <0x
173 clock-latency-ns = <15
174 opp-suspend;
175 };
176 };
177
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k"
183 };
184
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m"
190 };
191
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1
197 };
198
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2
204 };
205
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3
211 };
212
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4
218 };
219
220 psci {
221 compatible = "arm,psci-1.0";
222 method = "smc";
223 };
224
225 pmu {
226 compatible = "arm,cortex-a53-p
227 interrupts = <GIC_PPI 7
228 (GIC_CPU_MASK_SIM
229 };
230
231 timer {
232 compatible = "arm,armv8-timer"
233 interrupts = <GIC_PPI 13 (GIC_
234 <GIC_PPI 14 (GIC_
235 <GIC_PPI 11 (GIC_
236 <GIC_PPI 10 (GIC_
237 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend;
239 };
240
241 thermal-zones {
242 cpu-thermal {
243 polling-delay-passive
244 polling-delay = <2000>
245 thermal-sensors = <&tm
246 trips {
247 cpu_alert0: tr
248 temper
249 hyster
250 type =
251 };
252
253 cpu_crit0: tri
254 temper
255 hyster
256 type =
257 };
258 };
259
260 cooling-maps {
261 map0 {
262 trip =
263 coolin
264
265
266
267
268 };
269 };
270 };
271 };
272
273 usbphynop1: usbphynop1 {
274 #phy-cells = <0>;
275 compatible = "usb-nop-xceiv";
276 clocks = <&clk IMX8MM_CLK_USB_
277 assigned-clocks = <&clk IMX8MM
278 assigned-clock-parents = <&clk
279 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>;
281 };
282
283 usbphynop2: usbphynop2 {
284 #phy-cells = <0>;
285 compatible = "usb-nop-xceiv";
286 clocks = <&clk IMX8MM_CLK_USB_
287 assigned-clocks = <&clk IMX8MM
288 assigned-clock-parents = <&clk
289 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>;
291 };
292
293 soc: soc@0 {
294 compatible = "fsl,imx8mm-soc",
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges = <0x0 0x0 0x0 0x3e0000
298 dma-ranges = <0x40000000 0x0 0
299 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique
301
302 aips1: bus@30000000 {
303 compatible = "fsl,aips
304 reg = <0x30000000 0x40
305 #address-cells = <1>;
306 #size-cells = <1>;
307 ranges = <0x30000000 0
308
309 spba2: spba-bus@300000
310 compatible = "
311 #address-cells
312 #size-cells =
313 reg = <0x30000
314 ranges;
315
316 sai1: sai@3001
317 #sound
318 compat
319 reg =
320 interr
321 clocks
322
323
324 clock-
325 dmas =
326 dma-na
327 status
328 };
329
330 sai2: sai@3002
331 #sound
332 compat
333 reg =
334 interr
335 clocks
336
337
338 clock-
339 dmas =
340 dma-na
341 status
342 };
343
344 sai3: sai@3003
345 #sound
346 compat
347 reg =
348 interr
349 clocks
350
351
352 clock-
353 dmas =
354 dma-na
355 status
356 };
357
358 sai5: sai@3005
359 #sound
360 compat
361 reg =
362 interr
363 clocks
364
365
366 clock-
367 dmas =
368 dma-na
369 status
370 };
371
372 sai6: sai@3006
373 #sound
374 compat
375 reg =
376 interr
377 clocks
378
379
380 clock-
381 dmas =
382 dma-na
383 status
384 };
385
386 micfil: audio-
387 compat
388 reg =
389 interr
390
391
392
393 clocks
394
395
396
397
398 clock-
399
400 dmas =
401 dma-na
402 #sound
403 status
404 };
405
406 spdif1: spdif@
407 compat
408 reg =
409 interr
410 clocks
411
412
413
414
415
416
417
418
419
420 clock-
421
422
423
424
425 dmas =
426 dma-na
427 status
428 };
429 };
430
431 gpio1: gpio@30200000 {
432 compatible = "
433 reg = <0x30200
434 interrupts = <
435 <
436 clocks = <&clk
437 gpio-controlle
438 #gpio-cells =
439 interrupt-cont
440 #interrupt-cel
441 gpio-ranges =
442 };
443
444 gpio2: gpio@30210000 {
445 compatible = "
446 reg = <0x30210
447 interrupts = <
448 <
449 clocks = <&clk
450 gpio-controlle
451 #gpio-cells =
452 interrupt-cont
453 #interrupt-cel
454 gpio-ranges =
455 };
456
457 gpio3: gpio@30220000 {
458 compatible = "
459 reg = <0x30220
460 interrupts = <
461 <
462 clocks = <&clk
463 gpio-controlle
464 #gpio-cells =
465 interrupt-cont
466 #interrupt-cel
467 gpio-ranges =
468 };
469
470 gpio4: gpio@30230000 {
471 compatible = "
472 reg = <0x30230
473 interrupts = <
474 <
475 clocks = <&clk
476 gpio-controlle
477 #gpio-cells =
478 interrupt-cont
479 #interrupt-cel
480 gpio-ranges =
481 };
482
483 gpio5: gpio@30240000 {
484 compatible = "
485 reg = <0x30240
486 interrupts = <
487 <
488 clocks = <&clk
489 gpio-controlle
490 #gpio-cells =
491 interrupt-cont
492 #interrupt-cel
493 gpio-ranges =
494 };
495
496 tmu: tmu@30260000 {
497 compatible = "
498 reg = <0x30260
499 clocks = <&clk
500 nvmem-cells =
501 nvmem-cell-nam
502 #thermal-senso
503 };
504
505 wdog1: watchdog@302800
506 compatible = "
507 reg = <0x30280
508 interrupts = <
509 clocks = <&clk
510 status = "disa
511 };
512
513 wdog2: watchdog@302900
514 compatible = "
515 reg = <0x30290
516 interrupts = <
517 clocks = <&clk
518 status = "disa
519 };
520
521 wdog3: watchdog@302a00
522 compatible = "
523 reg = <0x302a0
524 interrupts = <
525 clocks = <&clk
526 status = "disa
527 };
528
529 sdma2: dma-controller@
530 compatible = "
531 reg = <0x302c0
532 interrupts = <
533 clocks = <&clk
534 <&clk
535 clock-names =
536 #dma-cells = <
537 fsl,sdma-ram-s
538 };
539
540 sdma3: dma-controller@
541 compatible = "
542 reg = <0x302b0
543 interrupts = <
544 clocks = <&clk
545 <&clk IMX8MM_
546 clock-names =
547 #dma-cells = <
548 fsl,sdma-ram-s
549 };
550
551 iomuxc: pinctrl@303300
552 compatible = "
553 reg = <0x30330
554 };
555
556 gpr: syscon@30340000 {
557 compatible = "
558 reg = <0x30340
559 };
560
561 ocotp: efuse@30350000
562 compatible = "
563 reg = <0x30350
564 clocks = <&clk
565 /* For nvmem s
566 #address-cells
567 #size-cells =
568
569 /*
570 * The registe
571 * Fusemap Des
572 * Assuming
573 * reg = <AD
574 * then
575 * Fuse Addr
576 * Note that i
577 * each subseq
578 * +0x10 in Fu
579 * reg = <0x4
580 * 0x420).
581 */
582 imx8mm_uid: un
583 reg =
584 };
585
586 cpu_speed_grad
587 reg =
588 };
589
590 tmu_calib: cal
591 reg =
592 };
593
594 fec_mac_addres
595 reg =
596 };
597 };
598
599 anatop: clock-controll
600 compatible = "
601 reg = <0x30360
602 #clock-cells =
603 };
604
605 snvs: snvs@30370000 {
606 compatible = "
607 reg = <0x30370
608
609 snvs_rtc: snvs
610 compat
611 regmap
612 offset
613 interr
614
615 clocks
616 clock-
617 };
618
619 snvs_pwrkey: s
620 compat
621 regmap
622 interr
623 clocks
624 clock-
625 linux,
626 wakeup
627 status
628 };
629
630 snvs_lpgpr: sn
631 compat
632
633 };
634 };
635
636 clk: clock-controller@
637 compatible = "
638 reg = <0x30380
639 interrupts = <
640 <
641 #clock-cells =
642 clocks = <&osc
643 <&clk
644 clock-names =
645
646 assigned-clock
647
648
649
650
651
652
653 assigned-clock
654
655
656
657 assigned-clock
658
659
660
661
662 };
663
664 src: reset-controller@
665 compatible = "
666 reg = <0x30390
667 interrupts = <
668 #reset-cells =
669 };
670
671 gpc: gpc@303a0000 {
672 compatible = "
673 reg = <0x303a0
674 interrupts = <
675 interrupt-pare
676 interrupt-cont
677 #interrupt-cel
678
679 pgc {
680 #addre
681 #size-
682
683 pgc_hs
684
685
686
687
688
689 };
690
691 pgc_pc
692
693
694
695
696 };
697
698 pgc_ot
699
700
701 };
702
703 pgc_ot
704
705
706 };
707
708 pgc_gp
709
710
711
712
713
714
715
716
717
718 };
719
720 pgc_gp
721
722
723
724
725
726
727
728
729 };
730
731 pgc_vp
732
733
734
735
736
737 };
738
739 pgc_vp
740
741
742 };
743
744 pgc_vp
745
746
747 };
748
749 pgc_vp
750
751
752 };
753
754 pgc_di
755
756
757
758
759
760
761
762
763
764 };
765
766 pgc_mi
767
768
769 };
770 };
771 };
772 };
773
774 aips2: bus@30400000 {
775 compatible = "fsl,aips
776 reg = <0x30400000 0x40
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges = <0x30400000 0
780
781 pwm1: pwm@30660000 {
782 compatible = "
783 reg = <0x30660
784 interrupts = <
785 clocks = <&clk
786 <&clk
787 clock-names =
788 #pwm-cells = <
789 status = "disa
790 };
791
792 pwm2: pwm@30670000 {
793 compatible = "
794 reg = <0x30670
795 interrupts = <
796 clocks = <&clk
797 <&clk
798 clock-names =
799 #pwm-cells = <
800 status = "disa
801 };
802
803 pwm3: pwm@30680000 {
804 compatible = "
805 reg = <0x30680
806 interrupts = <
807 clocks = <&clk
808 <&clk
809 clock-names =
810 #pwm-cells = <
811 status = "disa
812 };
813
814 pwm4: pwm@30690000 {
815 compatible = "
816 reg = <0x30690
817 interrupts = <
818 clocks = <&clk
819 <&clk
820 clock-names =
821 #pwm-cells = <
822 status = "disa
823 };
824
825 system_counter: timer@
826 compatible = "
827 reg = <0x306a0
828 interrupts = <
829 clocks = <&osc
830 clock-names =
831 };
832 };
833
834 aips3: bus@30800000 {
835 compatible = "fsl,aips
836 reg = <0x30800000 0x40
837 #address-cells = <1>;
838 #size-cells = <1>;
839 ranges = <0x30800000 0
840 <0x8000000 0x
841
842 spba1: spba-bus@308000
843 compatible = "
844 #address-cells
845 #size-cells =
846 reg = <0x30800
847 ranges;
848
849 ecspi1: spi@30
850 compat
851 #addre
852 #size-
853 reg =
854 interr
855 clocks
856
857 clock-
858 dmas =
859 dma-na
860 status
861 };
862
863 ecspi2: spi@30
864 compat
865 #addre
866 #size-
867 reg =
868 interr
869 clocks
870
871 clock-
872 dmas =
873 dma-na
874 status
875 };
876
877 ecspi3: spi@30
878 compat
879 #addre
880 #size-
881 reg =
882 interr
883 clocks
884
885 clock-
886 dmas =
887 dma-na
888 status
889 };
890
891 uart1: serial@
892 compat
893 reg =
894 interr
895 clocks
896
897 clock-
898 dmas =
899 dma-na
900 status
901 };
902
903 uart3: serial@
904 compat
905 reg =
906 interr
907 clocks
908
909 clock-
910 dmas =
911 dma-na
912 status
913 };
914
915 uart2: serial@
916 compat
917 reg =
918 interr
919 clocks
920
921 clock-
922 status
923 };
924 };
925
926 crypto: crypto@3090000
927 compatible = "
928 #address-cells
929 #size-cells =
930 reg = <0x30900
931 ranges = <0 0x
932 interrupts = <
933 clocks = <&clk
934 <&clk
935 clock-names =
936
937 sec_jr0: jr@10
938 compat
939 reg =
940 interr
941 status
942 };
943
944 sec_jr1: jr@20
945 compat
946 reg =
947 interr
948 };
949
950 sec_jr2: jr@30
951 compat
952 reg =
953 interr
954 };
955 };
956
957 i2c1: i2c@30a20000 {
958 compatible = "
959 #address-cells
960 #size-cells =
961 reg = <0x30a20
962 interrupts = <
963 clocks = <&clk
964 status = "disa
965 };
966
967 i2c2: i2c@30a30000 {
968 compatible = "
969 #address-cells
970 #size-cells =
971 reg = <0x30a30
972 interrupts = <
973 clocks = <&clk
974 status = "disa
975 };
976
977 i2c3: i2c@30a40000 {
978 #address-cells
979 #size-cells =
980 compatible = "
981 reg = <0x30a40
982 interrupts = <
983 clocks = <&clk
984 status = "disa
985 };
986
987 i2c4: i2c@30a50000 {
988 compatible = "
989 #address-cells
990 #size-cells =
991 reg = <0x30a50
992 interrupts = <
993 clocks = <&clk
994 status = "disa
995 };
996
997 uart4: serial@30a60000
998 compatible = "
999 reg = <0x30a60
1000 interrupts =
1001 clocks = <&cl
1002 <&cl
1003 clock-names =
1004 dmas = <&sdma
1005 dma-names = "
1006 status = "dis
1007 };
1008
1009 mu: mailbox@30aa0000
1010 compatible =
1011 reg = <0x30aa
1012 interrupts =
1013 clocks = <&cl
1014 #mbox-cells =
1015 };
1016
1017 usdhc1: mmc@30b40000
1018 compatible =
1019 reg = <0x30b4
1020 interrupts =
1021 clocks = <&cl
1022 <&cl
1023 <&cl
1024 clock-names =
1025 fsl,tuning-st
1026 fsl,tuning-st
1027 bus-width = <
1028 status = "dis
1029 };
1030
1031 usdhc2: mmc@30b50000
1032 compatible =
1033 reg = <0x30b5
1034 interrupts =
1035 clocks = <&cl
1036 <&cl
1037 <&cl
1038 clock-names =
1039 fsl,tuning-st
1040 fsl,tuning-st
1041 bus-width = <
1042 status = "dis
1043 };
1044
1045 usdhc3: mmc@30b60000
1046 compatible =
1047 reg = <0x30b6
1048 interrupts =
1049 clocks = <&cl
1050 <&cl
1051 <&cl
1052 clock-names =
1053 fsl,tuning-st
1054 fsl,tuning-st
1055 bus-width = <
1056 status = "dis
1057 };
1058
1059 flexspi: spi@30bb0000
1060 #address-cell
1061 #size-cells =
1062 compatible =
1063 reg = <0x30bb
1064 reg-names = "
1065 interrupts =
1066 clocks = <&cl
1067 <&cl
1068 clock-names =
1069 status = "dis
1070 };
1071
1072 sdma1: dma-controller
1073 compatible =
1074 reg = <0x30bd
1075 interrupts =
1076 clocks = <&cl
1077 <&cl
1078 clock-names =
1079 #dma-cells =
1080 fsl,sdma-ram-
1081 };
1082
1083 fec1: ethernet@30be00
1084 compatible =
1085 reg = <0x30be
1086 interrupts =
1087
1088
1089
1090 clocks = <&cl
1091 <&cl
1092 <&cl
1093 <&cl
1094 <&cl
1095 clock-names =
1096
1097 assigned-cloc
1098
1099
1100
1101 assigned-cloc
1102
1103
1104
1105 assigned-cloc
1106 fsl,num-tx-qu
1107 fsl,num-rx-qu
1108 nvmem-cells =
1109 nvmem-cell-na
1110 fsl,stop-mode
1111 status = "dis
1112 };
1113
1114 };
1115
1116 aips4: bus@32c00000 {
1117 compatible = "fsl,aip
1118 reg = <0x32c00000 0x4
1119 #address-cells = <1>;
1120 #size-cells = <1>;
1121 ranges = <0x32c00000
1122
1123 lcdif: lcdif@32e00000
1124 compatible =
1125 reg = <0x32e0
1126 clocks = <&cl
1127 <&cl
1128 <&cl
1129 clock-names =
1130 assigned-cloc
1131
1132
1133 assigned-cloc
1134
1135
1136 assigned-cloc
1137 interrupts =
1138 power-domains
1139 status = "dis
1140
1141 port {
1142 lcdif
1143
1144 };
1145 };
1146 };
1147
1148 mipi_dsi: dsi@32e1000
1149 compatible =
1150 reg = <0x32e1
1151 clocks = <&cl
1152 <&cl
1153 clock-names =
1154 assigned-cloc
1155 assigned-cloc
1156 interrupts =
1157 power-domains
1158 status = "dis
1159
1160 ports {
1161 #addr
1162 #size
1163
1164 port@
1165
1166
1167
1168
1169
1170 };
1171
1172 port@
1173
1174
1175
1176
1177 };
1178 };
1179 };
1180
1181 csi: csi@32e20000 {
1182 compatible =
1183 reg = <0x32e2
1184 interrupts =
1185 clocks = <&cl
1186 clock-names =
1187 power-domains
1188 status = "dis
1189
1190 port {
1191 csi_i
1192
1193 };
1194 };
1195 };
1196
1197 disp_blk_ctrl: blk-ct
1198 compatible =
1199 reg = <0x32e2
1200 power-domains
1201
1202
1203 power-domain-
1204
1205
1206 clocks = <&cl
1207 <&cl
1208 <&cl
1209 <&cl
1210 <&cl
1211 <&cl
1212 <&cl
1213 <&cl
1214 <&cl
1215 <&cl
1216 clock-names =
1217
1218
1219
1220
1221 #power-domain
1222 };
1223
1224 mipi_csi: mipi-csi@32
1225 compatible =
1226 reg = <0x32e3
1227 interrupts =
1228 assigned-cloc
1229 assigned-cloc
1230
1231 clock-frequen
1232 clocks = <&cl
1233 <&cl
1234 <&cl
1235 <&cl
1236 clock-names =
1237 power-domains
1238 status = "dis
1239
1240 ports {
1241 #addr
1242 #size
1243
1244 port@
1245
1246 };
1247
1248 port@
1249
1250
1251
1252
1253
1254 };
1255 };
1256 };
1257
1258 usbotg1: usb@32e40000
1259 compatible =
1260 reg = <0x32e4
1261 interrupts =
1262 clocks = <&cl
1263 assigned-cloc
1264 assigned-cloc
1265 phys = <&usbp
1266 fsl,usbmisc =
1267 power-domains
1268 status = "dis
1269 };
1270
1271 usbmisc1: usbmisc@32e
1272 compatible =
1273
1274 #index-cells
1275 reg = <0x32e4
1276 };
1277
1278 usbotg2: usb@32e50000
1279 compatible =
1280 reg = <0x32e5
1281 interrupts =
1282 clocks = <&cl
1283 assigned-cloc
1284 assigned-cloc
1285 phys = <&usbp
1286 fsl,usbmisc =
1287 power-domains
1288 status = "dis
1289 };
1290
1291 usbmisc2: usbmisc@32e
1292 compatible =
1293
1294 #index-cells
1295 reg = <0x32e5
1296 };
1297
1298 pcie_phy: pcie-phy@32
1299 compatible =
1300 reg = <0x32f0
1301 clocks = <&cl
1302 clock-names =
1303 assigned-cloc
1304 assigned-cloc
1305 assigned-cloc
1306 resets = <&sr
1307 reset-names =
1308 #phy-cells =
1309 status = "dis
1310 };
1311 };
1312
1313 dma_apbh: dma-controller@3300
1314 compatible = "fsl,imx
1315 reg = <0x33000000 0x2
1316 interrupts = <GIC_SPI
1317 <GIC_SPI
1318 <GIC_SPI
1319 <GIC_SPI
1320 #dma-cells = <1>;
1321 dma-channels = <4>;
1322 clocks = <&clk IMX8MM
1323 };
1324
1325 gpmi: nand-controller@3300200
1326 compatible = "fsl,imx
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329 reg = <0x33002000 0x2
1330 reg-names = "gpmi-nan
1331 interrupts = <GIC_SPI
1332 interrupt-names = "bc
1333 clocks = <&clk IMX8MM
1334 <&clk IMX8MM
1335 clock-names = "gpmi_i
1336 dmas = <&dma_apbh 0>;
1337 dma-names = "rx-tx";
1338 status = "disabled";
1339 };
1340
1341 pcie0: pcie@33800000 {
1342 compatible = "fsl,imx
1343 reg = <0x33800000 0x4
1344 reg-names = "dbi", "c
1345 #address-cells = <3>;
1346 #size-cells = <2>;
1347 device_type = "pci";
1348 bus-range = <0x00 0xf
1349 ranges = <0x81000000
1350 <0x82000000
1351 num-lanes = <1>;
1352 num-viewport = <4>;
1353 interrupts = <GIC_SPI
1354 interrupt-names = "ms
1355 #interrupt-cells = <1
1356 interrupt-map-mask =
1357 interrupt-map = <0 0
1358 <0 0
1359 <0 0
1360 <0 0
1361 fsl,max-link-speed =
1362 linux,pci-domain = <0
1363 clocks = <&clk IMX8MM
1364 <&clk IMX8MM
1365 <&clk IMX8MM
1366 clock-names = "pcie",
1367 power-domains = <&pgc
1368 resets = <&src IMX8MQ
1369 <&src IMX8MQ
1370 reset-names = "apps",
1371 phys = <&pcie_phy>;
1372 phy-names = "pcie-phy
1373 status = "disabled";
1374 };
1375
1376 pcie0_ep: pcie-ep@33800000 {
1377 compatible = "fsl,imx
1378 reg = <0x33800000 0x4
1379 <0x18000000 0x8
1380 reg-names = "dbi", "a
1381 num-lanes = <1>;
1382 interrupts = <GIC_SPI
1383 interrupt-names = "dm
1384 fsl,max-link-speed =
1385 clocks = <&clk IMX8MM
1386 <&clk IMX8MM
1387 <&clk IMX8MM
1388 clock-names = "pcie",
1389 power-domains = <&pgc
1390 resets = <&src IMX8MQ
1391 <&src IMX8MQ
1392 reset-names = "apps",
1393 phys = <&pcie_phy>;
1394 phy-names = "pcie-phy
1395 num-ib-windows = <4>;
1396 num-ob-windows = <4>;
1397 status = "disabled";
1398 };
1399
1400 gpu_3d: gpu@38000000 {
1401 compatible = "vivante
1402 reg = <0x38000000 0x8
1403 interrupts = <GIC_SPI
1404 clocks = <&clk IMX8MM
1405 <&clk IMX8MM
1406 <&clk IMX8MM
1407 <&clk IMX8MM
1408 clock-names = "reg",
1409 assigned-clocks = <&c
1410 <&c
1411 assigned-clock-parent
1412 assigned-clock-rates
1413 power-domains = <&pgc
1414 };
1415
1416 gpu_2d: gpu@38008000 {
1417 compatible = "vivante
1418 reg = <0x38008000 0x8
1419 interrupts = <GIC_SPI
1420 clocks = <&clk IMX8MM
1421 <&clk IMX8MM
1422 <&clk IMX8MM
1423 clock-names = "reg",
1424 assigned-clocks = <&c
1425 <&c
1426 assigned-clock-parent
1427 assigned-clock-rates
1428 power-domains = <&pgc
1429 };
1430
1431 vpu_g1: video-codec@38300000
1432 compatible = "nxp,imx
1433 reg = <0x38300000 0x1
1434 interrupts = <GIC_SPI
1435 clocks = <&clk IMX8MM
1436 power-domains = <&vpu
1437 };
1438
1439 vpu_g2: video-codec@38310000
1440 compatible = "nxp,imx
1441 reg = <0x38310000 0x1
1442 interrupts = <GIC_SPI
1443 clocks = <&clk IMX8MM
1444 power-domains = <&vpu
1445 };
1446
1447 vpu_blk_ctrl: blk-ctrl@383300
1448 compatible = "fsl,imx
1449 reg = <0x38330000 0x1
1450 power-domains = <&pgc
1451 <&pgc
1452 power-domain-names =
1453 clocks = <&clk IMX8MM
1454 <&clk IMX8MM
1455 <&clk IMX8MM
1456 clock-names = "g1", "
1457 assigned-clocks = <&c
1458 <&c
1459 assigned-clock-parent
1460
1461 assigned-clock-rates
1462
1463 #power-domain-cells =
1464 };
1465
1466 gic: interrupt-controller@388
1467 compatible = "arm,gic
1468 reg = <0x38800000 0x1
1469 <0x38880000 0xc
1470 #interrupt-cells = <3
1471 interrupt-controller;
1472 interrupts = <GIC_PPI
1473 };
1474
1475 ddrc: memory-controller@3d400
1476 compatible = "fsl,imx
1477 reg = <0x3d400000 0x4
1478 clock-names = "core",
1479 clocks = <&clk IMX8MM
1480 <&clk IMX8MM
1481 <&clk IMX8MM
1482 <&clk IMX8MM
1483 };
1484
1485 ddr-pmu@3d800000 {
1486 compatible = "fsl,imx
1487 reg = <0x3d800000 0x4
1488 interrupts = <GIC_SPI
1489 };
1490 };
1491 };
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