1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mm-clock.h> 6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h> <<
11 #include <dt-bindings/reset/imx8mq-reset.h> <<
12 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
13 11
14 #include "imx8mm-pinfunc.h" 12 #include "imx8mm-pinfunc.h"
15 13
16 / { 14 / {
17 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 aliases { 19 aliases {
22 ethernet0 = &fec1; 20 ethernet0 = &fec1;
23 gpio0 = &gpio1; 21 gpio0 = &gpio1;
24 gpio1 = &gpio2; 22 gpio1 = &gpio2;
25 gpio2 = &gpio3; 23 gpio2 = &gpio3;
26 gpio3 = &gpio4; 24 gpio3 = &gpio4;
27 gpio4 = &gpio5; 25 gpio4 = &gpio5;
28 i2c0 = &i2c1; 26 i2c0 = &i2c1;
29 i2c1 = &i2c2; 27 i2c1 = &i2c2;
30 i2c2 = &i2c3; 28 i2c2 = &i2c3;
31 i2c3 = &i2c4; 29 i2c3 = &i2c4;
32 mmc0 = &usdhc1; 30 mmc0 = &usdhc1;
33 mmc1 = &usdhc2; 31 mmc1 = &usdhc2;
34 mmc2 = &usdhc3; 32 mmc2 = &usdhc3;
35 serial0 = &uart1; 33 serial0 = &uart1;
36 serial1 = &uart2; 34 serial1 = &uart2;
37 serial2 = &uart3; 35 serial2 = &uart3;
38 serial3 = &uart4; 36 serial3 = &uart4;
39 spi0 = &ecspi1; 37 spi0 = &ecspi1;
40 spi1 = &ecspi2; 38 spi1 = &ecspi2;
41 spi2 = &ecspi3; 39 spi2 = &ecspi3;
42 }; 40 };
43 41
44 cpus { 42 cpus {
45 #address-cells = <1>; 43 #address-cells = <1>;
46 #size-cells = <0>; 44 #size-cells = <0>;
47 45
48 idle-states { 46 idle-states {
49 entry-method = "psci"; 47 entry-method = "psci";
50 48
51 cpu_pd_wait: cpu-pd-wa 49 cpu_pd_wait: cpu-pd-wait {
52 compatible = " 50 compatible = "arm,idle-state";
53 arm,psci-suspe 51 arm,psci-suspend-param = <0x0010033>;
54 local-timer-st 52 local-timer-stop;
55 entry-latency- 53 entry-latency-us = <1000>;
56 exit-latency-u 54 exit-latency-us = <700>;
57 min-residency- 55 min-residency-us = <2700>;
58 }; 56 };
59 }; 57 };
60 58
61 A53_0: cpu@0 { 59 A53_0: cpu@0 {
62 device_type = "cpu"; 60 device_type = "cpu";
63 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
64 reg = <0x0>; 62 reg = <0x0>;
65 clock-latency = <61036 63 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_ 64 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci" 65 enable-method = "psci";
68 i-cache-size = <0x8000 <<
69 i-cache-line-size = <6 <<
70 i-cache-sets = <256>; <<
71 d-cache-size = <0x8000 <<
72 d-cache-line-size = <6 <<
73 d-cache-sets = <128>; <<
74 next-level-cache = <&A 66 next-level-cache = <&A53_L2>;
75 operating-points-v2 = 67 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_sp 68 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "sp 69 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cp 70 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>; 71 #cooling-cells = <2>;
80 }; 72 };
81 73
82 A53_1: cpu@1 { 74 A53_1: cpu@1 {
83 device_type = "cpu"; 75 device_type = "cpu";
84 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
85 reg = <0x1>; 77 reg = <0x1>;
86 clock-latency = <61036 78 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_ 79 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci" 80 enable-method = "psci";
89 i-cache-size = <0x8000 <<
90 i-cache-line-size = <6 <<
91 i-cache-sets = <256>; <<
92 d-cache-size = <0x8000 <<
93 d-cache-line-size = <6 <<
94 d-cache-sets = <128>; <<
95 next-level-cache = <&A 81 next-level-cache = <&A53_L2>;
96 operating-points-v2 = 82 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cp 83 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>; 84 #cooling-cells = <2>;
99 }; 85 };
100 86
101 A53_2: cpu@2 { 87 A53_2: cpu@2 {
102 device_type = "cpu"; 88 device_type = "cpu";
103 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
104 reg = <0x2>; 90 reg = <0x2>;
105 clock-latency = <61036 91 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_ 92 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci" 93 enable-method = "psci";
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&A 94 next-level-cache = <&A53_L2>;
115 operating-points-v2 = 95 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cp 96 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>; 97 #cooling-cells = <2>;
118 }; 98 };
119 99
120 A53_3: cpu@3 { 100 A53_3: cpu@3 {
121 device_type = "cpu"; 101 device_type = "cpu";
122 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
123 reg = <0x3>; 103 reg = <0x3>;
124 clock-latency = <61036 104 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_ 105 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci" 106 enable-method = "psci";
127 i-cache-size = <0x8000 <<
128 i-cache-line-size = <6 <<
129 i-cache-sets = <256>; <<
130 d-cache-size = <0x8000 <<
131 d-cache-line-size = <6 <<
132 d-cache-sets = <128>; <<
133 next-level-cache = <&A 107 next-level-cache = <&A53_L2>;
134 operating-points-v2 = 108 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cp 109 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>; 110 #cooling-cells = <2>;
137 }; 111 };
138 112
139 A53_L2: l2-cache0 { 113 A53_L2: l2-cache0 {
140 compatible = "cache"; 114 compatible = "cache";
141 cache-level = <2>; <<
142 cache-unified; <<
143 cache-size = <0x80000> <<
144 cache-line-size = <64> <<
145 cache-sets = <512>; <<
146 }; 115 };
147 }; 116 };
148 117
149 a53_opp_table: opp-table { 118 a53_opp_table: opp-table {
150 compatible = "operating-points 119 compatible = "operating-points-v2";
151 opp-shared; 120 opp-shared;
152 121
153 opp-1200000000 { 122 opp-1200000000 {
154 opp-hz = /bits/ 64 <12 123 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <85000 124 opp-microvolt = <850000>;
156 opp-supported-hw = <0x 125 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <15 126 clock-latency-ns = <150000>;
158 opp-suspend; 127 opp-suspend;
159 }; 128 };
160 129
161 opp-1600000000 { 130 opp-1600000000 {
162 opp-hz = /bits/ 64 <16 131 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <95000 132 opp-microvolt = <950000>;
164 opp-supported-hw = <0x 133 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <15 134 clock-latency-ns = <150000>;
166 opp-suspend; 135 opp-suspend;
167 }; 136 };
168 137
169 opp-1800000000 { 138 opp-1800000000 {
170 opp-hz = /bits/ 64 <18 139 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <10000 140 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x 141 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <15 142 clock-latency-ns = <150000>;
174 opp-suspend; 143 opp-suspend;
175 }; 144 };
176 }; 145 };
177 146
178 osc_32k: clock-osc-32k { 147 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock"; 148 compatible = "fixed-clock";
180 #clock-cells = <0>; 149 #clock-cells = <0>;
181 clock-frequency = <32768>; 150 clock-frequency = <32768>;
182 clock-output-names = "osc_32k" 151 clock-output-names = "osc_32k";
183 }; 152 };
184 153
185 osc_24m: clock-osc-24m { 154 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock"; 155 compatible = "fixed-clock";
187 #clock-cells = <0>; 156 #clock-cells = <0>;
188 clock-frequency = <24000000>; 157 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m" 158 clock-output-names = "osc_24m";
190 }; 159 };
191 160
192 clk_ext1: clock-ext1 { 161 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock"; 162 compatible = "fixed-clock";
194 #clock-cells = <0>; 163 #clock-cells = <0>;
195 clock-frequency = <133000000>; 164 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1 165 clock-output-names = "clk_ext1";
197 }; 166 };
198 167
199 clk_ext2: clock-ext2 { 168 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock"; 169 compatible = "fixed-clock";
201 #clock-cells = <0>; 170 #clock-cells = <0>;
202 clock-frequency = <133000000>; 171 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2 172 clock-output-names = "clk_ext2";
204 }; 173 };
205 174
206 clk_ext3: clock-ext3 { 175 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock"; 176 compatible = "fixed-clock";
208 #clock-cells = <0>; 177 #clock-cells = <0>;
209 clock-frequency = <133000000>; 178 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3 179 clock-output-names = "clk_ext3";
211 }; 180 };
212 181
213 clk_ext4: clock-ext4 { 182 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock"; 183 compatible = "fixed-clock";
215 #clock-cells = <0>; 184 #clock-cells = <0>;
216 clock-frequency = <133000000>; !! 185 clock-frequency= <133000000>;
217 clock-output-names = "clk_ext4 186 clock-output-names = "clk_ext4";
218 }; 187 };
219 188
220 psci { 189 psci {
221 compatible = "arm,psci-1.0"; 190 compatible = "arm,psci-1.0";
222 method = "smc"; 191 method = "smc";
223 }; 192 };
224 193
225 pmu { 194 pmu {
226 compatible = "arm,cortex-a53-p !! 195 compatible = "arm,armv8-pmuv3";
227 interrupts = <GIC_PPI 7 196 interrupts = <GIC_PPI 7
228 (GIC_CPU_MASK_SIM 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> 198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
229 }; 199 };
230 200
231 timer { 201 timer {
232 compatible = "arm,armv8-timer" 202 compatible = "arm,armv8-timer";
233 interrupts = <GIC_PPI 13 (GIC_ 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
234 <GIC_PPI 14 (GIC_ 204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
235 <GIC_PPI 11 (GIC_ 205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
236 <GIC_PPI 10 (GIC_ 206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
237 clock-frequency = <8000000>; 207 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend; 208 arm,no-tick-in-suspend;
239 }; 209 };
240 210
241 thermal-zones { 211 thermal-zones {
242 cpu-thermal { 212 cpu-thermal {
243 polling-delay-passive 213 polling-delay-passive = <250>;
244 polling-delay = <2000> 214 polling-delay = <2000>;
245 thermal-sensors = <&tm 215 thermal-sensors = <&tmu>;
246 trips { 216 trips {
247 cpu_alert0: tr 217 cpu_alert0: trip0 {
248 temper 218 temperature = <85000>;
249 hyster 219 hysteresis = <2000>;
250 type = 220 type = "passive";
251 }; 221 };
252 222
253 cpu_crit0: tri 223 cpu_crit0: trip1 {
254 temper 224 temperature = <95000>;
255 hyster 225 hysteresis = <2000>;
256 type = 226 type = "critical";
257 }; 227 };
258 }; 228 };
259 229
260 cooling-maps { 230 cooling-maps {
261 map0 { 231 map0 {
262 trip = 232 trip = <&cpu_alert0>;
263 coolin 233 cooling-device =
264 234 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 235 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 236 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
267 237 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
268 }; 238 };
269 }; 239 };
270 }; 240 };
271 }; 241 };
272 242
273 usbphynop1: usbphynop1 { 243 usbphynop1: usbphynop1 {
274 #phy-cells = <0>; <<
275 compatible = "usb-nop-xceiv"; 244 compatible = "usb-nop-xceiv";
276 clocks = <&clk IMX8MM_CLK_USB_ 245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clocks = <&clk IMX8MM 246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk 247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk"; 248 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>; <<
281 }; 249 };
282 250
283 usbphynop2: usbphynop2 { 251 usbphynop2: usbphynop2 {
284 #phy-cells = <0>; <<
285 compatible = "usb-nop-xceiv"; 252 compatible = "usb-nop-xceiv";
286 clocks = <&clk IMX8MM_CLK_USB_ 253 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clocks = <&clk IMX8MM 254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk 255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk"; 256 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>; <<
291 }; 257 };
292 258
293 soc: soc@0 { !! 259 soc@0 {
294 compatible = "fsl,imx8mm-soc", 260 compatible = "fsl,imx8mm-soc", "simple-bus";
295 #address-cells = <1>; 261 #address-cells = <1>;
296 #size-cells = <1>; 262 #size-cells = <1>;
297 ranges = <0x0 0x0 0x0 0x3e0000 263 ranges = <0x0 0x0 0x0 0x3e000000>;
298 dma-ranges = <0x40000000 0x0 0 <<
299 nvmem-cells = <&imx8mm_uid>; 264 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique 265 nvmem-cell-names = "soc_unique_id";
301 266
302 aips1: bus@30000000 { 267 aips1: bus@30000000 {
303 compatible = "fsl,aips 268 compatible = "fsl,aips-bus", "simple-bus";
304 reg = <0x30000000 0x40 269 reg = <0x30000000 0x400000>;
305 #address-cells = <1>; 270 #address-cells = <1>;
306 #size-cells = <1>; 271 #size-cells = <1>;
307 ranges = <0x30000000 0 272 ranges = <0x30000000 0x30000000 0x400000>;
308 273
309 spba2: spba-bus@300000 !! 274 sai1: sai@30010000 {
310 compatible = " !! 275 #sound-dai-cells = <0>;
311 #address-cells !! 276 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
312 #size-cells = !! 277 reg = <0x30010000 0x10000>;
313 reg = <0x30000 !! 278 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
314 ranges; !! 279 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
315 !! 280 <&clk IMX8MM_CLK_SAI1_ROOT>,
316 sai1: sai@3001 !! 281 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
317 #sound !! 282 clock-names = "bus", "mclk1", "mclk2", "mclk3";
318 compat !! 283 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
319 reg = !! 284 dma-names = "rx", "tx";
320 interr !! 285 status = "disabled";
321 clocks !! 286 };
322 <<
323 <<
324 clock- <<
325 dmas = <<
326 dma-na <<
327 status <<
328 }; <<
329 287
330 sai2: sai@3002 !! 288 sai2: sai@30020000 {
331 #sound !! 289 #sound-dai-cells = <0>;
332 compat !! 290 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333 reg = !! 291 reg = <0x30020000 0x10000>;
334 interr !! 292 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
335 clocks !! 293 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
336 !! 294 <&clk IMX8MM_CLK_SAI2_ROOT>,
337 !! 295 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
338 clock- !! 296 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dmas = !! 297 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
340 dma-na !! 298 dma-names = "rx", "tx";
341 status !! 299 status = "disabled";
342 }; !! 300 };
343 301
344 sai3: sai@3003 !! 302 sai3: sai@30030000 {
345 #sound !! 303 #sound-dai-cells = <0>;
346 compat !! 304 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
347 reg = !! 305 reg = <0x30030000 0x10000>;
348 interr !! 306 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
349 clocks !! 307 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
350 !! 308 <&clk IMX8MM_CLK_SAI3_ROOT>,
351 !! 309 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
352 clock- !! 310 clock-names = "bus", "mclk1", "mclk2", "mclk3";
353 dmas = !! 311 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
354 dma-na !! 312 dma-names = "rx", "tx";
355 status !! 313 status = "disabled";
356 }; !! 314 };
357 315
358 sai5: sai@3005 !! 316 sai5: sai@30050000 {
359 #sound !! 317 #sound-dai-cells = <0>;
360 compat !! 318 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
361 reg = !! 319 reg = <0x30050000 0x10000>;
362 interr !! 320 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
363 clocks !! 321 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
364 !! 322 <&clk IMX8MM_CLK_SAI5_ROOT>,
365 !! 323 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
366 clock- !! 324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
367 dmas = !! 325 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
368 dma-na !! 326 dma-names = "rx", "tx";
369 status !! 327 status = "disabled";
370 }; !! 328 };
371 329
372 sai6: sai@3006 !! 330 sai6: sai@30060000 {
373 #sound !! 331 #sound-dai-cells = <0>;
374 compat !! 332 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
375 reg = !! 333 reg = <0x30060000 0x10000>;
376 interr !! 334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
377 clocks !! 335 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
378 !! 336 <&clk IMX8MM_CLK_SAI6_ROOT>,
379 !! 337 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
380 clock- !! 338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dmas = !! 339 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
382 dma-na !! 340 dma-names = "rx", "tx";
383 status !! 341 status = "disabled";
384 }; !! 342 };
385 343
386 micfil: audio- !! 344 micfil: audio-controller@30080000 {
387 compat !! 345 compatible = "fsl,imx8mm-micfil";
388 reg = !! 346 reg = <0x30080000 0x10000>;
389 interr !! 347 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
390 !! 348 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
391 !! 349 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
392 !! 350 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393 clocks !! 351 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
394 !! 352 <&clk IMX8MM_CLK_PDM_ROOT>,
395 !! 353 <&clk IMX8MM_AUDIO_PLL1_OUT>,
396 !! 354 <&clk IMX8MM_AUDIO_PLL2_OUT>,
397 !! 355 <&clk IMX8MM_CLK_EXT3>;
398 clock- !! 356 clock-names = "ipg_clk", "ipg_clk_app",
399 !! 357 "pll8k", "pll11k", "clkext3";
400 dmas = !! 358 dmas = <&sdma2 24 25 0x80000000>;
401 dma-na !! 359 dma-names = "rx";
402 #sound !! 360 status = "disabled";
403 status !! 361 };
404 }; <<
405 362
406 spdif1: spdif@ !! 363 spdif1: spdif@30090000 {
407 compat !! 364 compatible = "fsl,imx35-spdif";
408 reg = !! 365 reg = <0x30090000 0x10000>;
409 interr !! 366 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
410 clocks !! 367 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
411 !! 368 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
412 !! 369 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
413 !! 370 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
414 !! 371 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
415 !! 372 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
416 !! 373 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
417 !! 374 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
418 !! 375 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
419 !! 376 <&clk IMX8MM_CLK_DUMMY>; /* spba */
420 clock- !! 377 clock-names = "core", "rxtx0",
421 !! 378 "rxtx1", "rxtx2",
422 !! 379 "rxtx3", "rxtx4",
423 !! 380 "rxtx5", "rxtx6",
424 !! 381 "rxtx7", "spba";
425 dmas = !! 382 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
426 dma-na !! 383 dma-names = "rx", "tx";
427 status !! 384 status = "disabled";
428 }; <<
429 }; 385 };
430 386
431 gpio1: gpio@30200000 { 387 gpio1: gpio@30200000 {
432 compatible = " 388 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
433 reg = <0x30200 389 reg = <0x30200000 0x10000>;
434 interrupts = < 390 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435 < 391 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk 392 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
437 gpio-controlle 393 gpio-controller;
438 #gpio-cells = 394 #gpio-cells = <2>;
439 interrupt-cont 395 interrupt-controller;
440 #interrupt-cel 396 #interrupt-cells = <2>;
441 gpio-ranges = 397 gpio-ranges = <&iomuxc 0 10 30>;
442 }; 398 };
443 399
444 gpio2: gpio@30210000 { 400 gpio2: gpio@30210000 {
445 compatible = " 401 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
446 reg = <0x30210 402 reg = <0x30210000 0x10000>;
447 interrupts = < 403 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448 < 404 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk 405 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
450 gpio-controlle 406 gpio-controller;
451 #gpio-cells = 407 #gpio-cells = <2>;
452 interrupt-cont 408 interrupt-controller;
453 #interrupt-cel 409 #interrupt-cells = <2>;
454 gpio-ranges = 410 gpio-ranges = <&iomuxc 0 40 21>;
455 }; 411 };
456 412
457 gpio3: gpio@30220000 { 413 gpio3: gpio@30220000 {
458 compatible = " 414 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
459 reg = <0x30220 415 reg = <0x30220000 0x10000>;
460 interrupts = < 416 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461 < 417 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clk 418 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
463 gpio-controlle 419 gpio-controller;
464 #gpio-cells = 420 #gpio-cells = <2>;
465 interrupt-cont 421 interrupt-controller;
466 #interrupt-cel 422 #interrupt-cells = <2>;
467 gpio-ranges = 423 gpio-ranges = <&iomuxc 0 61 26>;
468 }; 424 };
469 425
470 gpio4: gpio@30230000 { 426 gpio4: gpio@30230000 {
471 compatible = " 427 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
472 reg = <0x30230 428 reg = <0x30230000 0x10000>;
473 interrupts = < 429 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474 < 430 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk 431 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
476 gpio-controlle 432 gpio-controller;
477 #gpio-cells = 433 #gpio-cells = <2>;
478 interrupt-cont 434 interrupt-controller;
479 #interrupt-cel 435 #interrupt-cells = <2>;
480 gpio-ranges = 436 gpio-ranges = <&iomuxc 0 87 32>;
481 }; 437 };
482 438
483 gpio5: gpio@30240000 { 439 gpio5: gpio@30240000 {
484 compatible = " 440 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
485 reg = <0x30240 441 reg = <0x30240000 0x10000>;
486 interrupts = < 442 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487 < 443 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk 444 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
489 gpio-controlle 445 gpio-controller;
490 #gpio-cells = 446 #gpio-cells = <2>;
491 interrupt-cont 447 interrupt-controller;
492 #interrupt-cel 448 #interrupt-cells = <2>;
493 gpio-ranges = 449 gpio-ranges = <&iomuxc 0 119 30>;
494 }; 450 };
495 451
496 tmu: tmu@30260000 { 452 tmu: tmu@30260000 {
497 compatible = " 453 compatible = "fsl,imx8mm-tmu";
498 reg = <0x30260 454 reg = <0x30260000 0x10000>;
499 clocks = <&clk 455 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
500 nvmem-cells = <<
501 nvmem-cell-nam <<
502 #thermal-senso 456 #thermal-sensor-cells = <0>;
503 }; 457 };
504 458
505 wdog1: watchdog@302800 459 wdog1: watchdog@30280000 {
506 compatible = " 460 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
507 reg = <0x30280 461 reg = <0x30280000 0x10000>;
508 interrupts = < 462 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clk 463 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510 status = "disa 464 status = "disabled";
511 }; 465 };
512 466
513 wdog2: watchdog@302900 467 wdog2: watchdog@30290000 {
514 compatible = " 468 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
515 reg = <0x30290 469 reg = <0x30290000 0x10000>;
516 interrupts = < 470 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk 471 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518 status = "disa 472 status = "disabled";
519 }; 473 };
520 474
521 wdog3: watchdog@302a00 475 wdog3: watchdog@302a0000 {
522 compatible = " 476 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
523 reg = <0x302a0 477 reg = <0x302a0000 0x10000>;
524 interrupts = < 478 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clk 479 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526 status = "disa 480 status = "disabled";
527 }; 481 };
528 482
529 sdma2: dma-controller@ 483 sdma2: dma-controller@302c0000 {
530 compatible = " 484 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531 reg = <0x302c0 485 reg = <0x302c0000 0x10000>;
532 interrupts = < 486 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clk 487 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
534 <&clk 488 <&clk IMX8MM_CLK_SDMA2_ROOT>;
535 clock-names = 489 clock-names = "ipg", "ahb";
536 #dma-cells = < 490 #dma-cells = <3>;
537 fsl,sdma-ram-s 491 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
538 }; 492 };
539 493
540 sdma3: dma-controller@ 494 sdma3: dma-controller@302b0000 {
541 compatible = " 495 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542 reg = <0x302b0 496 reg = <0x302b0000 0x10000>;
543 interrupts = < 497 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clk 498 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
545 <&clk IMX8MM_ 499 <&clk IMX8MM_CLK_SDMA3_ROOT>;
546 clock-names = 500 clock-names = "ipg", "ahb";
547 #dma-cells = < 501 #dma-cells = <3>;
548 fsl,sdma-ram-s 502 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
549 }; 503 };
550 504
551 iomuxc: pinctrl@303300 505 iomuxc: pinctrl@30330000 {
552 compatible = " 506 compatible = "fsl,imx8mm-iomuxc";
553 reg = <0x30330 507 reg = <0x30330000 0x10000>;
554 }; 508 };
555 509
556 gpr: syscon@30340000 { !! 510 gpr: iomuxc-gpr@30340000 {
557 compatible = " 511 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
558 reg = <0x30340 512 reg = <0x30340000 0x10000>;
559 }; 513 };
560 514
561 ocotp: efuse@30350000 515 ocotp: efuse@30350000 {
562 compatible = " 516 compatible = "fsl,imx8mm-ocotp", "syscon";
563 reg = <0x30350 517 reg = <0x30350000 0x10000>;
564 clocks = <&clk 518 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
565 /* For nvmem s 519 /* For nvmem subnodes */
566 #address-cells 520 #address-cells = <1>;
567 #size-cells = 521 #size-cells = <1>;
568 522
569 /* !! 523 imx8mm_uid: unique-id@410 {
570 * The registe <<
571 * Fusemap Des <<
572 * Assuming <<
573 * reg = <AD <<
574 * then <<
575 * Fuse Addr <<
576 * Note that i <<
577 * each subseq <<
578 * +0x10 in Fu <<
579 * reg = <0x4 <<
580 * 0x420). <<
581 */ <<
582 imx8mm_uid: un <<
583 reg = 524 reg = <0x4 0x8>;
584 }; 525 };
585 526
586 cpu_speed_grad !! 527 cpu_speed_grade: speed-grade@10 {
587 reg = 528 reg = <0x10 4>;
588 }; 529 };
589 530
590 tmu_calib: cal !! 531 fec_mac_address: mac-address@90 {
591 reg = <<
592 }; <<
593 <<
594 fec_mac_addres <<
595 reg = 532 reg = <0x90 6>;
596 }; 533 };
597 }; 534 };
598 535
599 anatop: clock-controll !! 536 anatop: anatop@30360000 {
600 compatible = " !! 537 compatible = "fsl,imx8mm-anatop", "syscon";
601 reg = <0x30360 538 reg = <0x30360000 0x10000>;
602 #clock-cells = <<
603 }; 539 };
604 540
605 snvs: snvs@30370000 { 541 snvs: snvs@30370000 {
606 compatible = " 542 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607 reg = <0x30370 543 reg = <0x30370000 0x10000>;
608 544
609 snvs_rtc: snvs 545 snvs_rtc: snvs-rtc-lp {
610 compat 546 compatible = "fsl,sec-v4.0-mon-rtc-lp";
611 regmap 547 regmap = <&snvs>;
612 offset 548 offset = <0x34>;
613 interr 549 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614 550 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
615 clocks 551 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
616 clock- 552 clock-names = "snvs-rtc";
617 }; 553 };
618 554
619 snvs_pwrkey: s 555 snvs_pwrkey: snvs-powerkey {
620 compat 556 compatible = "fsl,sec-v4.0-pwrkey";
621 regmap 557 regmap = <&snvs>;
622 interr 558 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
623 clocks 559 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
624 clock- 560 clock-names = "snvs-pwrkey";
625 linux, 561 linux,keycode = <KEY_POWER>;
626 wakeup 562 wakeup-source;
627 status 563 status = "disabled";
628 }; 564 };
629 <<
630 snvs_lpgpr: sn <<
631 compat <<
632 <<
633 }; <<
634 }; 565 };
635 566
636 clk: clock-controller@ 567 clk: clock-controller@30380000 {
637 compatible = " 568 compatible = "fsl,imx8mm-ccm";
638 reg = <0x30380 569 reg = <0x30380000 0x10000>;
639 interrupts = < <<
640 < <<
641 #clock-cells = 570 #clock-cells = <1>;
642 clocks = <&osc 571 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
643 <&clk 572 <&clk_ext3>, <&clk_ext4>;
644 clock-names = 573 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
645 574 "clk_ext3", "clk_ext4";
646 assigned-clock 575 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
647 576 <&clk IMX8MM_CLK_A53_CORE>,
648 577 <&clk IMX8MM_CLK_NOC>,
649 578 <&clk IMX8MM_CLK_AUDIO_AHB>,
650 579 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
651 580 <&clk IMX8MM_SYS_PLL3>,
652 !! 581 <&clk IMX8MM_VIDEO_PLL1>,
>> 582 <&clk IMX8MM_AUDIO_PLL1>,
>> 583 <&clk IMX8MM_AUDIO_PLL2>;
653 assigned-clock 584 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
654 585 <&clk IMX8MM_ARM_PLL_OUT>,
655 586 <&clk IMX8MM_SYS_PLL3_OUT>,
656 587 <&clk IMX8MM_SYS_PLL1_800M>;
657 assigned-clock 588 assigned-clock-rates = <0>, <0>, <0>,
658 589 <400000000>,
659 590 <400000000>,
660 591 <750000000>,
661 !! 592 <594000000>,
>> 593 <393216000>,
>> 594 <361267200>;
662 }; 595 };
663 596
664 src: reset-controller@ 597 src: reset-controller@30390000 {
665 compatible = " 598 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
666 reg = <0x30390 599 reg = <0x30390000 0x10000>;
667 interrupts = < 600 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
668 #reset-cells = 601 #reset-cells = <1>;
669 }; 602 };
670 <<
671 gpc: gpc@303a0000 { <<
672 compatible = " <<
673 reg = <0x303a0 <<
674 interrupts = < <<
675 interrupt-pare <<
676 interrupt-cont <<
677 #interrupt-cel <<
678 <<
679 pgc { <<
680 #addre <<
681 #size- <<
682 <<
683 pgc_hs <<
684 <<
685 <<
686 <<
687 <<
688 <<
689 }; <<
690 <<
691 pgc_pc <<
692 <<
693 <<
694 <<
695 <<
696 }; <<
697 <<
698 pgc_ot <<
699 <<
700 <<
701 }; <<
702 <<
703 pgc_ot <<
704 <<
705 <<
706 }; <<
707 <<
708 pgc_gp <<
709 <<
710 <<
711 <<
712 <<
713 <<
714 <<
715 <<
716 <<
717 <<
718 }; <<
719 <<
720 pgc_gp <<
721 <<
722 <<
723 <<
724 <<
725 <<
726 <<
727 <<
728 <<
729 }; <<
730 <<
731 pgc_vp <<
732 <<
733 <<
734 <<
735 <<
736 <<
737 }; <<
738 <<
739 pgc_vp <<
740 <<
741 <<
742 }; <<
743 <<
744 pgc_vp <<
745 <<
746 <<
747 }; <<
748 <<
749 pgc_vp <<
750 <<
751 <<
752 }; <<
753 <<
754 pgc_di <<
755 <<
756 <<
757 <<
758 <<
759 <<
760 <<
761 <<
762 <<
763 <<
764 }; <<
765 <<
766 pgc_mi <<
767 <<
768 <<
769 }; <<
770 }; <<
771 }; <<
772 }; 603 };
773 604
774 aips2: bus@30400000 { 605 aips2: bus@30400000 {
775 compatible = "fsl,aips 606 compatible = "fsl,aips-bus", "simple-bus";
776 reg = <0x30400000 0x40 607 reg = <0x30400000 0x400000>;
777 #address-cells = <1>; 608 #address-cells = <1>;
778 #size-cells = <1>; 609 #size-cells = <1>;
779 ranges = <0x30400000 0 610 ranges = <0x30400000 0x30400000 0x400000>;
780 611
781 pwm1: pwm@30660000 { 612 pwm1: pwm@30660000 {
782 compatible = " 613 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
783 reg = <0x30660 614 reg = <0x30660000 0x10000>;
784 interrupts = < 615 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk 616 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
786 <&clk 617 <&clk IMX8MM_CLK_PWM1_ROOT>;
787 clock-names = 618 clock-names = "ipg", "per";
788 #pwm-cells = < !! 619 #pwm-cells = <2>;
789 status = "disa 620 status = "disabled";
790 }; 621 };
791 622
792 pwm2: pwm@30670000 { 623 pwm2: pwm@30670000 {
793 compatible = " 624 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
794 reg = <0x30670 625 reg = <0x30670000 0x10000>;
795 interrupts = < 626 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk 627 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
797 <&clk 628 <&clk IMX8MM_CLK_PWM2_ROOT>;
798 clock-names = 629 clock-names = "ipg", "per";
799 #pwm-cells = < !! 630 #pwm-cells = <2>;
800 status = "disa 631 status = "disabled";
801 }; 632 };
802 633
803 pwm3: pwm@30680000 { 634 pwm3: pwm@30680000 {
804 compatible = " 635 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
805 reg = <0x30680 636 reg = <0x30680000 0x10000>;
806 interrupts = < 637 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clk 638 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
808 <&clk 639 <&clk IMX8MM_CLK_PWM3_ROOT>;
809 clock-names = 640 clock-names = "ipg", "per";
810 #pwm-cells = < !! 641 #pwm-cells = <2>;
811 status = "disa 642 status = "disabled";
812 }; 643 };
813 644
814 pwm4: pwm@30690000 { 645 pwm4: pwm@30690000 {
815 compatible = " 646 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
816 reg = <0x30690 647 reg = <0x30690000 0x10000>;
817 interrupts = < 648 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clk 649 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
819 <&clk 650 <&clk IMX8MM_CLK_PWM4_ROOT>;
820 clock-names = 651 clock-names = "ipg", "per";
821 #pwm-cells = < !! 652 #pwm-cells = <2>;
822 status = "disa 653 status = "disabled";
823 }; 654 };
824 655
825 system_counter: timer@ 656 system_counter: timer@306a0000 {
826 compatible = " 657 compatible = "nxp,sysctr-timer";
827 reg = <0x306a0 658 reg = <0x306a0000 0x20000>;
828 interrupts = < 659 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&osc 660 clocks = <&osc_24m>;
830 clock-names = 661 clock-names = "per";
831 }; 662 };
832 }; 663 };
833 664
834 aips3: bus@30800000 { 665 aips3: bus@30800000 {
835 compatible = "fsl,aips 666 compatible = "fsl,aips-bus", "simple-bus";
836 reg = <0x30800000 0x40 667 reg = <0x30800000 0x400000>;
837 #address-cells = <1>; 668 #address-cells = <1>;
838 #size-cells = <1>; 669 #size-cells = <1>;
839 ranges = <0x30800000 0 670 ranges = <0x30800000 0x30800000 0x400000>,
840 <0x8000000 0x 671 <0x8000000 0x8000000 0x10000000>;
841 672
842 spba1: spba-bus@308000 !! 673 ecspi1: spi@30820000 {
843 compatible = " !! 674 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
844 #address-cells 675 #address-cells = <1>;
845 #size-cells = !! 676 #size-cells = <0>;
846 reg = <0x30800 !! 677 reg = <0x30820000 0x10000>;
847 ranges; !! 678 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
848 !! 679 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
849 ecspi1: spi@30 !! 680 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
850 compat !! 681 clock-names = "ipg", "per";
851 #addre !! 682 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
852 #size- !! 683 dma-names = "rx", "tx";
853 reg = !! 684 status = "disabled";
854 interr !! 685 };
855 clocks <<
856 <<
857 clock- <<
858 dmas = <<
859 dma-na <<
860 status <<
861 }; <<
862 686
863 ecspi2: spi@30 !! 687 ecspi2: spi@30830000 {
864 compat !! 688 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
865 #addre !! 689 #address-cells = <1>;
866 #size- !! 690 #size-cells = <0>;
867 reg = !! 691 reg = <0x30830000 0x10000>;
868 interr !! 692 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
869 clocks !! 693 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
870 !! 694 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
871 clock- !! 695 clock-names = "ipg", "per";
872 dmas = !! 696 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
873 dma-na !! 697 dma-names = "rx", "tx";
874 status !! 698 status = "disabled";
875 }; !! 699 };
876 700
877 ecspi3: spi@30 !! 701 ecspi3: spi@30840000 {
878 compat !! 702 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
879 #addre !! 703 #address-cells = <1>;
880 #size- !! 704 #size-cells = <0>;
881 reg = !! 705 reg = <0x30840000 0x10000>;
882 interr !! 706 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
883 clocks !! 707 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
884 !! 708 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
885 clock- !! 709 clock-names = "ipg", "per";
886 dmas = !! 710 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
887 dma-na !! 711 dma-names = "rx", "tx";
888 status !! 712 status = "disabled";
889 }; !! 713 };
890 714
891 uart1: serial@ !! 715 uart1: serial@30860000 {
892 compat !! 716 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
893 reg = !! 717 reg = <0x30860000 0x10000>;
894 interr !! 718 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
895 clocks !! 719 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
896 !! 720 <&clk IMX8MM_CLK_UART1_ROOT>;
897 clock- !! 721 clock-names = "ipg", "per";
898 dmas = !! 722 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
899 dma-na !! 723 dma-names = "rx", "tx";
900 status !! 724 status = "disabled";
901 }; !! 725 };
902 726
903 uart3: serial@ !! 727 uart3: serial@30880000 {
904 compat !! 728 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
905 reg = !! 729 reg = <0x30880000 0x10000>;
906 interr !! 730 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
907 clocks !! 731 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
908 !! 732 <&clk IMX8MM_CLK_UART3_ROOT>;
909 clock- !! 733 clock-names = "ipg", "per";
910 dmas = !! 734 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
911 dma-na !! 735 dma-names = "rx", "tx";
912 status !! 736 status = "disabled";
913 }; !! 737 };
914 738
915 uart2: serial@ !! 739 uart2: serial@30890000 {
916 compat !! 740 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
917 reg = !! 741 reg = <0x30890000 0x10000>;
918 interr !! 742 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
919 clocks !! 743 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
920 !! 744 <&clk IMX8MM_CLK_UART2_ROOT>;
921 clock- !! 745 clock-names = "ipg", "per";
922 status !! 746 status = "disabled";
923 }; <<
924 }; 747 };
925 748
926 crypto: crypto@3090000 749 crypto: crypto@30900000 {
927 compatible = " 750 compatible = "fsl,sec-v4.0";
928 #address-cells 751 #address-cells = <1>;
929 #size-cells = 752 #size-cells = <1>;
930 reg = <0x30900 753 reg = <0x30900000 0x40000>;
931 ranges = <0 0x 754 ranges = <0 0x30900000 0x40000>;
932 interrupts = < 755 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&clk 756 clocks = <&clk IMX8MM_CLK_AHB>,
934 <&clk 757 <&clk IMX8MM_CLK_IPG_ROOT>;
935 clock-names = 758 clock-names = "aclk", "ipg";
936 759
937 sec_jr0: jr@10 760 sec_jr0: jr@1000 {
938 compat 761 compatible = "fsl,sec-v4.0-job-ring";
939 reg = 762 reg = <0x1000 0x1000>;
940 interr 763 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
941 status <<
942 }; 764 };
943 765
944 sec_jr1: jr@20 766 sec_jr1: jr@2000 {
945 compat 767 compatible = "fsl,sec-v4.0-job-ring";
946 reg = 768 reg = <0x2000 0x1000>;
947 interr 769 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
948 }; 770 };
949 771
950 sec_jr2: jr@30 772 sec_jr2: jr@3000 {
951 compat 773 compatible = "fsl,sec-v4.0-job-ring";
952 reg = 774 reg = <0x3000 0x1000>;
953 interr 775 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
954 }; 776 };
955 }; 777 };
956 778
957 i2c1: i2c@30a20000 { 779 i2c1: i2c@30a20000 {
958 compatible = " 780 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
959 #address-cells 781 #address-cells = <1>;
960 #size-cells = 782 #size-cells = <0>;
961 reg = <0x30a20 783 reg = <0x30a20000 0x10000>;
962 interrupts = < 784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk 785 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
964 status = "disa 786 status = "disabled";
965 }; 787 };
966 788
967 i2c2: i2c@30a30000 { 789 i2c2: i2c@30a30000 {
968 compatible = " 790 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969 #address-cells 791 #address-cells = <1>;
970 #size-cells = 792 #size-cells = <0>;
971 reg = <0x30a30 793 reg = <0x30a30000 0x10000>;
972 interrupts = < 794 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clk 795 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
974 status = "disa 796 status = "disabled";
975 }; 797 };
976 798
977 i2c3: i2c@30a40000 { 799 i2c3: i2c@30a40000 {
978 #address-cells 800 #address-cells = <1>;
979 #size-cells = 801 #size-cells = <0>;
980 compatible = " 802 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
981 reg = <0x30a40 803 reg = <0x30a40000 0x10000>;
982 interrupts = < 804 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&clk 805 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
984 status = "disa 806 status = "disabled";
985 }; 807 };
986 808
987 i2c4: i2c@30a50000 { 809 i2c4: i2c@30a50000 {
988 compatible = " 810 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
989 #address-cells 811 #address-cells = <1>;
990 #size-cells = 812 #size-cells = <0>;
991 reg = <0x30a50 813 reg = <0x30a50000 0x10000>;
992 interrupts = < 814 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clk 815 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
994 status = "disa 816 status = "disabled";
995 }; 817 };
996 818
997 uart4: serial@30a60000 819 uart4: serial@30a60000 {
998 compatible = " 820 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
999 reg = <0x30a60 821 reg = <0x30a60000 0x10000>;
1000 interrupts = 822 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cl 823 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
1002 <&cl 824 <&clk IMX8MM_CLK_UART4_ROOT>;
1003 clock-names = 825 clock-names = "ipg", "per";
1004 dmas = <&sdma 826 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1005 dma-names = " 827 dma-names = "rx", "tx";
1006 status = "dis 828 status = "disabled";
1007 }; 829 };
1008 830
1009 mu: mailbox@30aa0000 831 mu: mailbox@30aa0000 {
1010 compatible = 832 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1011 reg = <0x30aa 833 reg = <0x30aa0000 0x10000>;
1012 interrupts = 834 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cl 835 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
1014 #mbox-cells = 836 #mbox-cells = <2>;
1015 }; 837 };
1016 838
1017 usdhc1: mmc@30b40000 839 usdhc1: mmc@30b40000 {
1018 compatible = 840 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1019 reg = <0x30b4 841 reg = <0x30b40000 0x10000>;
1020 interrupts = 842 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cl 843 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1022 <&cl 844 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1023 <&cl 845 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1024 clock-names = 846 clock-names = "ipg", "ahb", "per";
1025 fsl,tuning-st 847 fsl,tuning-start-tap = <20>;
1026 fsl,tuning-st !! 848 fsl,tuning-step= <2>;
1027 bus-width = < 849 bus-width = <4>;
1028 status = "dis 850 status = "disabled";
1029 }; 851 };
1030 852
1031 usdhc2: mmc@30b50000 853 usdhc2: mmc@30b50000 {
1032 compatible = 854 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1033 reg = <0x30b5 855 reg = <0x30b50000 0x10000>;
1034 interrupts = 856 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&cl 857 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1036 <&cl 858 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1037 <&cl 859 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1038 clock-names = 860 clock-names = "ipg", "ahb", "per";
1039 fsl,tuning-st 861 fsl,tuning-start-tap = <20>;
1040 fsl,tuning-st !! 862 fsl,tuning-step= <2>;
1041 bus-width = < 863 bus-width = <4>;
1042 status = "dis 864 status = "disabled";
1043 }; 865 };
1044 866
1045 usdhc3: mmc@30b60000 867 usdhc3: mmc@30b60000 {
1046 compatible = 868 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1047 reg = <0x30b6 869 reg = <0x30b60000 0x10000>;
1048 interrupts = 870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cl 871 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1050 <&cl 872 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1051 <&cl 873 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1052 clock-names = 874 clock-names = "ipg", "ahb", "per";
1053 fsl,tuning-st 875 fsl,tuning-start-tap = <20>;
1054 fsl,tuning-st !! 876 fsl,tuning-step= <2>;
1055 bus-width = < 877 bus-width = <4>;
1056 status = "dis 878 status = "disabled";
1057 }; 879 };
1058 880
1059 flexspi: spi@30bb0000 881 flexspi: spi@30bb0000 {
1060 #address-cell 882 #address-cells = <1>;
1061 #size-cells = 883 #size-cells = <0>;
1062 compatible = 884 compatible = "nxp,imx8mm-fspi";
1063 reg = <0x30bb 885 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1064 reg-names = " 886 reg-names = "fspi_base", "fspi_mmap";
1065 interrupts = 887 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&cl 888 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1067 <&cl 889 <&clk IMX8MM_CLK_QSPI_ROOT>;
1068 clock-names = 890 clock-names = "fspi_en", "fspi";
1069 status = "dis 891 status = "disabled";
1070 }; 892 };
1071 893
1072 sdma1: dma-controller 894 sdma1: dma-controller@30bd0000 {
1073 compatible = 895 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1074 reg = <0x30bd 896 reg = <0x30bd0000 0x10000>;
1075 interrupts = 897 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&cl 898 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1077 <&cl 899 <&clk IMX8MM_CLK_AHB>;
1078 clock-names = 900 clock-names = "ipg", "ahb";
1079 #dma-cells = 901 #dma-cells = <3>;
1080 fsl,sdma-ram- 902 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1081 }; 903 };
1082 904
1083 fec1: ethernet@30be00 905 fec1: ethernet@30be0000 {
1084 compatible = !! 906 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
1085 reg = <0x30be 907 reg = <0x30be0000 0x10000>;
1086 interrupts = 908 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1087 909 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1088 910 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1089 911 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&cl 912 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1091 <&cl 913 <&clk IMX8MM_CLK_ENET1_ROOT>,
1092 <&cl 914 <&clk IMX8MM_CLK_ENET_TIMER>,
1093 <&cl 915 <&clk IMX8MM_CLK_ENET_REF>,
1094 <&cl 916 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1095 clock-names = 917 clock-names = "ipg", "ahb", "ptp",
1096 918 "enet_clk_ref", "enet_out";
1097 assigned-cloc 919 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1098 920 <&clk IMX8MM_CLK_ENET_TIMER>,
1099 921 <&clk IMX8MM_CLK_ENET_REF>,
1100 922 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1101 assigned-cloc 923 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1102 924 <&clk IMX8MM_SYS_PLL2_100M>,
1103 925 <&clk IMX8MM_SYS_PLL2_125M>,
1104 926 <&clk IMX8MM_SYS_PLL2_50M>;
1105 assigned-cloc 927 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1106 fsl,num-tx-qu 928 fsl,num-tx-queues = <3>;
1107 fsl,num-rx-qu 929 fsl,num-rx-queues = <3>;
1108 nvmem-cells = 930 nvmem-cells = <&fec_mac_address>;
1109 nvmem-cell-na 931 nvmem-cell-names = "mac-address";
>> 932 nvmem_macaddr_swap;
1110 fsl,stop-mode 933 fsl,stop-mode = <&gpr 0x10 3>;
1111 status = "dis 934 status = "disabled";
1112 }; 935 };
1113 936
1114 }; 937 };
1115 938
1116 aips4: bus@32c00000 { 939 aips4: bus@32c00000 {
1117 compatible = "fsl,aip 940 compatible = "fsl,aips-bus", "simple-bus";
1118 reg = <0x32c00000 0x4 941 reg = <0x32c00000 0x400000>;
1119 #address-cells = <1>; 942 #address-cells = <1>;
1120 #size-cells = <1>; 943 #size-cells = <1>;
1121 ranges = <0x32c00000 944 ranges = <0x32c00000 0x32c00000 0x400000>;
1122 945
1123 lcdif: lcdif@32e00000 <<
1124 compatible = <<
1125 reg = <0x32e0 <<
1126 clocks = <&cl <<
1127 <&cl <<
1128 <&cl <<
1129 clock-names = <<
1130 assigned-cloc <<
1131 <<
1132 <<
1133 assigned-cloc <<
1134 <<
1135 <<
1136 assigned-cloc <<
1137 interrupts = <<
1138 power-domains <<
1139 status = "dis <<
1140 <<
1141 port { <<
1142 lcdif <<
1143 <<
1144 }; <<
1145 }; <<
1146 }; <<
1147 <<
1148 mipi_dsi: dsi@32e1000 <<
1149 compatible = <<
1150 reg = <0x32e1 <<
1151 clocks = <&cl <<
1152 <&cl <<
1153 clock-names = <<
1154 assigned-cloc <<
1155 assigned-cloc <<
1156 interrupts = <<
1157 power-domains <<
1158 status = "dis <<
1159 <<
1160 ports { <<
1161 #addr <<
1162 #size <<
1163 <<
1164 port@ <<
1165 <<
1166 <<
1167 <<
1168 <<
1169 <<
1170 }; <<
1171 <<
1172 port@ <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 }; <<
1178 }; <<
1179 }; <<
1180 <<
1181 csi: csi@32e20000 { <<
1182 compatible = <<
1183 reg = <0x32e2 <<
1184 interrupts = <<
1185 clocks = <&cl <<
1186 clock-names = <<
1187 power-domains <<
1188 status = "dis <<
1189 <<
1190 port { <<
1191 csi_i <<
1192 <<
1193 }; <<
1194 }; <<
1195 }; <<
1196 <<
1197 disp_blk_ctrl: blk-ct <<
1198 compatible = <<
1199 reg = <0x32e2 <<
1200 power-domains <<
1201 <<
1202 <<
1203 power-domain- <<
1204 <<
1205 <<
1206 clocks = <&cl <<
1207 <&cl <<
1208 <&cl <<
1209 <&cl <<
1210 <&cl <<
1211 <&cl <<
1212 <&cl <<
1213 <&cl <<
1214 <&cl <<
1215 <&cl <<
1216 clock-names = <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 #power-domain <<
1222 }; <<
1223 <<
1224 mipi_csi: mipi-csi@32 <<
1225 compatible = <<
1226 reg = <0x32e3 <<
1227 interrupts = <<
1228 assigned-cloc <<
1229 assigned-cloc <<
1230 <<
1231 clock-frequen <<
1232 clocks = <&cl <<
1233 <&cl <<
1234 <&cl <<
1235 <&cl <<
1236 clock-names = <<
1237 power-domains <<
1238 status = "dis <<
1239 <<
1240 ports { <<
1241 #addr <<
1242 #size <<
1243 <<
1244 port@ <<
1245 <<
1246 }; <<
1247 <<
1248 port@ <<
1249 <<
1250 <<
1251 <<
1252 <<
1253 <<
1254 }; <<
1255 }; <<
1256 }; <<
1257 <<
1258 usbotg1: usb@32e40000 946 usbotg1: usb@32e40000 {
1259 compatible = !! 947 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1260 reg = <0x32e4 948 reg = <0x32e40000 0x200>;
1261 interrupts = 949 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cl 950 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 951 clock-names = "usb1_ctrl_root_clk";
1263 assigned-cloc 952 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1264 assigned-cloc 953 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1265 phys = <&usbp !! 954 fsl,usbphy = <&usbphynop1>;
1266 fsl,usbmisc = 955 fsl,usbmisc = <&usbmisc1 0>;
1267 power-domains <<
1268 status = "dis 956 status = "disabled";
1269 }; 957 };
1270 958
1271 usbmisc1: usbmisc@32e 959 usbmisc1: usbmisc@32e40200 {
1272 compatible = !! 960 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1273 <<
1274 #index-cells 961 #index-cells = <1>;
1275 reg = <0x32e4 962 reg = <0x32e40200 0x200>;
1276 }; 963 };
1277 964
1278 usbotg2: usb@32e50000 965 usbotg2: usb@32e50000 {
1279 compatible = !! 966 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1280 reg = <0x32e5 967 reg = <0x32e50000 0x200>;
1281 interrupts = 968 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&cl 969 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 970 clock-names = "usb1_ctrl_root_clk";
1283 assigned-cloc 971 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1284 assigned-cloc 972 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1285 phys = <&usbp !! 973 fsl,usbphy = <&usbphynop2>;
1286 fsl,usbmisc = 974 fsl,usbmisc = <&usbmisc2 0>;
1287 power-domains <<
1288 status = "dis 975 status = "disabled";
1289 }; 976 };
1290 977
1291 usbmisc2: usbmisc@32e 978 usbmisc2: usbmisc@32e50200 {
1292 compatible = !! 979 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1293 <<
1294 #index-cells 980 #index-cells = <1>;
1295 reg = <0x32e5 981 reg = <0x32e50200 0x200>;
1296 }; 982 };
1297 983
1298 pcie_phy: pcie-phy@32 <<
1299 compatible = <<
1300 reg = <0x32f0 <<
1301 clocks = <&cl <<
1302 clock-names = <<
1303 assigned-cloc <<
1304 assigned-cloc <<
1305 assigned-cloc <<
1306 resets = <&sr <<
1307 reset-names = <<
1308 #phy-cells = <<
1309 status = "dis <<
1310 }; <<
1311 }; 984 };
1312 985
1313 dma_apbh: dma-controller@3300 986 dma_apbh: dma-controller@33000000 {
1314 compatible = "fsl,imx 987 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1315 reg = <0x33000000 0x2 988 reg = <0x33000000 0x2000>;
1316 interrupts = <GIC_SPI 989 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 990 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 991 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 992 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 993 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1320 #dma-cells = <1>; 994 #dma-cells = <1>;
1321 dma-channels = <4>; 995 dma-channels = <4>;
1322 clocks = <&clk IMX8MM 996 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1323 }; 997 };
1324 998
1325 gpmi: nand-controller@3300200 !! 999 gpmi: nand-controller@33002000{
1326 compatible = "fsl,imx 1000 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1327 #address-cells = <1>; 1001 #address-cells = <1>;
1328 #size-cells = <0>; !! 1002 #size-cells = <1>;
1329 reg = <0x33002000 0x2 1003 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1330 reg-names = "gpmi-nan 1004 reg-names = "gpmi-nand", "bch";
1331 interrupts = <GIC_SPI 1005 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "bc 1006 interrupt-names = "bch";
1333 clocks = <&clk IMX8MM 1007 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1334 <&clk IMX8MM 1008 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1335 clock-names = "gpmi_i 1009 clock-names = "gpmi_io", "gpmi_bch_apb";
1336 dmas = <&dma_apbh 0>; 1010 dmas = <&dma_apbh 0>;
1337 dma-names = "rx-tx"; 1011 dma-names = "rx-tx";
1338 status = "disabled"; 1012 status = "disabled";
1339 }; <<
1340 <<
1341 pcie0: pcie@33800000 { <<
1342 compatible = "fsl,imx <<
1343 reg = <0x33800000 0x4 <<
1344 reg-names = "dbi", "c <<
1345 #address-cells = <3>; <<
1346 #size-cells = <2>; <<
1347 device_type = "pci"; <<
1348 bus-range = <0x00 0xf <<
1349 ranges = <0x81000000 <<
1350 <0x82000000 <<
1351 num-lanes = <1>; <<
1352 num-viewport = <4>; <<
1353 interrupts = <GIC_SPI <<
1354 interrupt-names = "ms <<
1355 #interrupt-cells = <1 <<
1356 interrupt-map-mask = <<
1357 interrupt-map = <0 0 <<
1358 <0 0 <<
1359 <0 0 <<
1360 <0 0 <<
1361 fsl,max-link-speed = <<
1362 linux,pci-domain = <0 <<
1363 clocks = <&clk IMX8MM <<
1364 <&clk IMX8MM <<
1365 <&clk IMX8MM <<
1366 clock-names = "pcie", <<
1367 power-domains = <&pgc <<
1368 resets = <&src IMX8MQ <<
1369 <&src IMX8MQ <<
1370 reset-names = "apps", <<
1371 phys = <&pcie_phy>; <<
1372 phy-names = "pcie-phy <<
1373 status = "disabled"; <<
1374 }; <<
1375 <<
1376 pcie0_ep: pcie-ep@33800000 { <<
1377 compatible = "fsl,imx <<
1378 reg = <0x33800000 0x4 <<
1379 <0x18000000 0x8 <<
1380 reg-names = "dbi", "a <<
1381 num-lanes = <1>; <<
1382 interrupts = <GIC_SPI <<
1383 interrupt-names = "dm <<
1384 fsl,max-link-speed = <<
1385 clocks = <&clk IMX8MM <<
1386 <&clk IMX8MM <<
1387 <&clk IMX8MM <<
1388 clock-names = "pcie", <<
1389 power-domains = <&pgc <<
1390 resets = <&src IMX8MQ <<
1391 <&src IMX8MQ <<
1392 reset-names = "apps", <<
1393 phys = <&pcie_phy>; <<
1394 phy-names = "pcie-phy <<
1395 num-ib-windows = <4>; <<
1396 num-ob-windows = <4>; <<
1397 status = "disabled"; <<
1398 }; <<
1399 <<
1400 gpu_3d: gpu@38000000 { <<
1401 compatible = "vivante <<
1402 reg = <0x38000000 0x8 <<
1403 interrupts = <GIC_SPI <<
1404 clocks = <&clk IMX8MM <<
1405 <&clk IMX8MM <<
1406 <&clk IMX8MM <<
1407 <&clk IMX8MM <<
1408 clock-names = "reg", <<
1409 assigned-clocks = <&c <<
1410 <&c <<
1411 assigned-clock-parent <<
1412 assigned-clock-rates <<
1413 power-domains = <&pgc <<
1414 }; <<
1415 <<
1416 gpu_2d: gpu@38008000 { <<
1417 compatible = "vivante <<
1418 reg = <0x38008000 0x8 <<
1419 interrupts = <GIC_SPI <<
1420 clocks = <&clk IMX8MM <<
1421 <&clk IMX8MM <<
1422 <&clk IMX8MM <<
1423 clock-names = "reg", <<
1424 assigned-clocks = <&c <<
1425 <&c <<
1426 assigned-clock-parent <<
1427 assigned-clock-rates <<
1428 power-domains = <&pgc <<
1429 }; <<
1430 <<
1431 vpu_g1: video-codec@38300000 <<
1432 compatible = "nxp,imx <<
1433 reg = <0x38300000 0x1 <<
1434 interrupts = <GIC_SPI <<
1435 clocks = <&clk IMX8MM <<
1436 power-domains = <&vpu <<
1437 }; <<
1438 <<
1439 vpu_g2: video-codec@38310000 <<
1440 compatible = "nxp,imx <<
1441 reg = <0x38310000 0x1 <<
1442 interrupts = <GIC_SPI <<
1443 clocks = <&clk IMX8MM <<
1444 power-domains = <&vpu <<
1445 }; <<
1446 <<
1447 vpu_blk_ctrl: blk-ctrl@383300 <<
1448 compatible = "fsl,imx <<
1449 reg = <0x38330000 0x1 <<
1450 power-domains = <&pgc <<
1451 <&pgc <<
1452 power-domain-names = <<
1453 clocks = <&clk IMX8MM <<
1454 <&clk IMX8MM <<
1455 <&clk IMX8MM <<
1456 clock-names = "g1", " <<
1457 assigned-clocks = <&c <<
1458 <&c <<
1459 assigned-clock-parent <<
1460 <<
1461 assigned-clock-rates <<
1462 <<
1463 #power-domain-cells = <<
1464 }; 1013 };
1465 1014
1466 gic: interrupt-controller@388 1015 gic: interrupt-controller@38800000 {
1467 compatible = "arm,gic 1016 compatible = "arm,gic-v3";
1468 reg = <0x38800000 0x1 1017 reg = <0x38800000 0x10000>, /* GIC Dist */
1469 <0x38880000 0xc 1018 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1470 #interrupt-cells = <3 1019 #interrupt-cells = <3>;
1471 interrupt-controller; 1020 interrupt-controller;
1472 interrupts = <GIC_PPI 1021 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1473 }; 1022 };
1474 1023
1475 ddrc: memory-controller@3d400 1024 ddrc: memory-controller@3d400000 {
1476 compatible = "fsl,imx 1025 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1477 reg = <0x3d400000 0x4 1026 reg = <0x3d400000 0x400000>;
1478 clock-names = "core", 1027 clock-names = "core", "pll", "alt", "apb";
1479 clocks = <&clk IMX8MM 1028 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1480 <&clk IMX8MM 1029 <&clk IMX8MM_DRAM_PLL>,
1481 <&clk IMX8MM 1030 <&clk IMX8MM_CLK_DRAM_ALT>,
1482 <&clk IMX8MM 1031 <&clk IMX8MM_CLK_DRAM_APB>;
1483 }; 1032 };
1484 1033
1485 ddr-pmu@3d800000 { 1034 ddr-pmu@3d800000 {
1486 compatible = "fsl,imx 1035 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1487 reg = <0x3d800000 0x4 1036 reg = <0x3d800000 0x400000>;
1488 interrupts = <GIC_SPI 1037 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1489 }; 1038 };
1490 }; 1039 };
1491 }; 1040 };
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